1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/IntrinsicInst.h" 47 #include "llvm/Support/Debug.h" 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "x86tti" 52 53 extern cl::opt<bool> ExperimentalVectorWideningLegalization; 54 55 //===----------------------------------------------------------------------===// 56 // 57 // X86 cost model. 58 // 59 //===----------------------------------------------------------------------===// 60 61 TargetTransformInfo::PopcntSupportKind 62 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 63 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 64 // TODO: Currently the __builtin_popcount() implementation using SSE3 65 // instructions is inefficient. Once the problem is fixed, we should 66 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 67 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 68 } 69 70 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 71 TargetTransformInfo::CacheLevel Level) const { 72 switch (Level) { 73 case TargetTransformInfo::CacheLevel::L1D: 74 // - Penryn 75 // - Nehalem 76 // - Westmere 77 // - Sandy Bridge 78 // - Ivy Bridge 79 // - Haswell 80 // - Broadwell 81 // - Skylake 82 // - Kabylake 83 return 32 * 1024; // 32 KByte 84 case TargetTransformInfo::CacheLevel::L2D: 85 // - Penryn 86 // - Nehalem 87 // - Westmere 88 // - Sandy Bridge 89 // - Ivy Bridge 90 // - Haswell 91 // - Broadwell 92 // - Skylake 93 // - Kabylake 94 return 256 * 1024; // 256 KByte 95 } 96 97 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 98 } 99 100 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 101 TargetTransformInfo::CacheLevel Level) const { 102 // - Penryn 103 // - Nehalem 104 // - Westmere 105 // - Sandy Bridge 106 // - Ivy Bridge 107 // - Haswell 108 // - Broadwell 109 // - Skylake 110 // - Kabylake 111 switch (Level) { 112 case TargetTransformInfo::CacheLevel::L1D: 113 LLVM_FALLTHROUGH; 114 case TargetTransformInfo::CacheLevel::L2D: 115 return 8; 116 } 117 118 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 119 } 120 121 unsigned X86TTIImpl::getNumberOfRegisters(bool Vector) { 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const { 134 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 135 if (Vector) { 136 if (ST->hasAVX512() && PreferVectorWidth >= 512) 137 return 512; 138 if (ST->hasAVX() && PreferVectorWidth >= 256) 139 return 256; 140 if (ST->hasSSE1() && PreferVectorWidth >= 128) 141 return 128; 142 return 0; 143 } 144 145 if (ST->is64Bit()) 146 return 64; 147 148 return 32; 149 } 150 151 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 152 return getRegisterBitWidth(true); 153 } 154 155 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 156 // If the loop will not be vectorized, don't interleave the loop. 157 // Let regular unroll to unroll the loop, which saves the overflow 158 // check and memory check cost. 159 if (VF == 1) 160 return 1; 161 162 if (ST->isAtom()) 163 return 1; 164 165 // Sandybridge and Haswell have multiple execution ports and pipelined 166 // vector units. 167 if (ST->hasAVX()) 168 return 4; 169 170 return 2; 171 } 172 173 int X86TTIImpl::getArithmeticInstrCost( 174 unsigned Opcode, Type *Ty, 175 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 176 TTI::OperandValueProperties Opd1PropInfo, 177 TTI::OperandValueProperties Opd2PropInfo, 178 ArrayRef<const Value *> Args) { 179 // Legalize the type. 180 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 181 182 int ISD = TLI->InstructionOpcodeToISD(Opcode); 183 assert(ISD && "Invalid opcode"); 184 185 static const CostTblEntry GLMCostTable[] = { 186 { ISD::FDIV, MVT::f32, 18 }, // divss 187 { ISD::FDIV, MVT::v4f32, 35 }, // divps 188 { ISD::FDIV, MVT::f64, 33 }, // divsd 189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 190 }; 191 192 if (ST->isGLM()) 193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 194 LT.second)) 195 return LT.first * Entry->Cost; 196 197 static const CostTblEntry SLMCostTable[] = { 198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. 201 { ISD::FMUL, MVT::f64, 2 }, // mulsd 202 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 203 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 204 { ISD::FDIV, MVT::f32, 17 }, // divss 205 { ISD::FDIV, MVT::v4f32, 39 }, // divps 206 { ISD::FDIV, MVT::f64, 32 }, // divsd 207 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 208 { ISD::FADD, MVT::v2f64, 2 }, // addpd 209 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 210 // v2i64/v4i64 mul is custom lowered as a series of long: 211 // multiplies(3), shifts(3) and adds(2) 212 // slm muldq version throughput is 2 and addq throughput 4 213 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 214 // 3X4 (addq throughput) = 17 215 { ISD::MUL, MVT::v2i64, 17 }, 216 // slm addq\subq throughput is 4 217 { ISD::ADD, MVT::v2i64, 4 }, 218 { ISD::SUB, MVT::v2i64, 4 }, 219 }; 220 221 if (ST->isSLM()) { 222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 223 // Check if the operands can be shrinked into a smaller datatype. 224 bool Op1Signed = false; 225 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 226 bool Op2Signed = false; 227 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 228 229 bool signedMode = Op1Signed | Op2Signed; 230 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 231 232 if (OpMinSize <= 7) 233 return LT.first * 3; // pmullw/sext 234 if (!signedMode && OpMinSize <= 8) 235 return LT.first * 3; // pmullw/zext 236 if (OpMinSize <= 15) 237 return LT.first * 5; // pmullw/pmulhw/pshuf 238 if (!signedMode && OpMinSize <= 16) 239 return LT.first * 5; // pmullw/pmulhw/pshuf 240 } 241 242 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 243 LT.second)) { 244 return LT.first * Entry->Cost; 245 } 246 } 247 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || 249 ISD == ISD::UREM) && 250 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 251 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 252 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { 254 // On X86, vector signed division by constants power-of-two are 255 // normally expanded to the sequence SRA + SRL + ADD + SRA. 256 // The OperandValue properties may not be the same as that of the previous 257 // operation; conservatively assume OP_None. 258 int Cost = 259 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, 260 TargetTransformInfo::OP_None, 261 TargetTransformInfo::OP_None); 262 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 263 TargetTransformInfo::OP_None, 264 TargetTransformInfo::OP_None); 265 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, 266 TargetTransformInfo::OP_None, 267 TargetTransformInfo::OP_None); 268 269 if (ISD == ISD::SREM) { 270 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 271 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Op1Info, Op2Info); 273 } 274 275 return Cost; 276 } 277 278 // Vector unsigned division/remainder will be simplified to shifts/masks. 279 if (ISD == ISD::UDIV) 280 return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, 281 TargetTransformInfo::OP_None, 282 TargetTransformInfo::OP_None); 283 284 if (ISD == ISD::UREM) 285 return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, 286 TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 } 289 290 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 294 }; 295 296 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 297 ST->hasBWI()) { 298 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 299 LT.second)) 300 return LT.first * Entry->Cost; 301 } 302 303 static const CostTblEntry AVX512UniformConstCostTable[] = { 304 { ISD::SRA, MVT::v2i64, 1 }, 305 { ISD::SRA, MVT::v4i64, 1 }, 306 { ISD::SRA, MVT::v8i64, 1 }, 307 }; 308 309 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 310 ST->hasAVX512()) { 311 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 312 LT.second)) 313 return LT.first * Entry->Cost; 314 } 315 316 static const CostTblEntry AVX2UniformConstCostTable[] = { 317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 320 321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 322 }; 323 324 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 325 ST->hasAVX2()) { 326 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 327 LT.second)) 328 return LT.first * Entry->Cost; 329 } 330 331 static const CostTblEntry SSE2UniformConstCostTable[] = { 332 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 335 336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 339 }; 340 341 // XOP has faster vXi8 shifts. 342 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 343 ST->hasSSE2() && !ST->hasXOP()) { 344 if (const auto *Entry = 345 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 346 return LT.first * Entry->Cost; 347 } 348 349 static const CostTblEntry AVX512BWConstCostTable[] = { 350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 354 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 356 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 357 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 358 }; 359 360 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 361 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 362 ST->hasBWI()) { 363 if (const auto *Entry = 364 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 365 return LT.first * Entry->Cost; 366 } 367 368 static const CostTblEntry AVX512ConstCostTable[] = { 369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 373 }; 374 375 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 376 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 377 ST->hasAVX512()) { 378 if (const auto *Entry = 379 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 380 return LT.first * Entry->Cost; 381 } 382 383 static const CostTblEntry AVX2ConstCostTable[] = { 384 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 386 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 396 }; 397 398 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 399 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 400 ST->hasAVX2()) { 401 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 402 return LT.first * Entry->Cost; 403 } 404 405 static const CostTblEntry SSE2ConstCostTable[] = { 406 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 408 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 409 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 410 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 411 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 412 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 413 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 416 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 417 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 420 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 421 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 430 }; 431 432 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 433 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 434 ST->hasSSE2()) { 435 // pmuldq sequence. 436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 437 return LT.first * 32; 438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 439 return LT.first * 38; 440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 441 return LT.first * 15; 442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 443 return LT.first * 20; 444 445 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 446 return LT.first * Entry->Cost; 447 } 448 449 static const CostTblEntry AVX2UniformCostTable[] = { 450 // Uniform splats are cheaper for the following instructions. 451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 453 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 454 }; 455 456 if (ST->hasAVX2() && 457 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 458 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 459 if (const auto *Entry = 460 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 461 return LT.first * Entry->Cost; 462 } 463 464 static const CostTblEntry SSE2UniformCostTable[] = { 465 // Uniform splats are cheaper for the following instructions. 466 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 467 { ISD::SHL, MVT::v4i32, 1 }, // pslld 468 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 469 470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 473 474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 475 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 476 }; 477 478 if (ST->hasSSE2() && 479 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 480 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 481 if (const auto *Entry = 482 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 483 return LT.first * Entry->Cost; 484 } 485 486 static const CostTblEntry AVX512DQCostTable[] = { 487 { ISD::MUL, MVT::v2i64, 1 }, 488 { ISD::MUL, MVT::v4i64, 1 }, 489 { ISD::MUL, MVT::v8i64, 1 } 490 }; 491 492 // Look for AVX512DQ lowering tricks for custom cases. 493 if (ST->hasDQI()) 494 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 495 return LT.first * Entry->Cost; 496 497 static const CostTblEntry AVX512BWCostTable[] = { 498 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 500 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 501 502 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 504 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 505 506 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 507 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 508 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 509 510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 513 514 { ISD::MUL, MVT::v64i8, 11 }, // extend/pmullw/trunc sequence. 515 { ISD::MUL, MVT::v32i8, 4 }, // extend/pmullw/trunc sequence. 516 { ISD::MUL, MVT::v16i8, 4 }, // extend/pmullw/trunc sequence. 517 }; 518 519 // Look for AVX512BW lowering tricks for custom cases. 520 if (ST->hasBWI()) 521 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 522 return LT.first * Entry->Cost; 523 524 static const CostTblEntry AVX512CostTable[] = { 525 { ISD::SHL, MVT::v16i32, 1 }, 526 { ISD::SRL, MVT::v16i32, 1 }, 527 { ISD::SRA, MVT::v16i32, 1 }, 528 529 { ISD::SHL, MVT::v8i64, 1 }, 530 { ISD::SRL, MVT::v8i64, 1 }, 531 532 { ISD::SRA, MVT::v2i64, 1 }, 533 { ISD::SRA, MVT::v4i64, 1 }, 534 { ISD::SRA, MVT::v8i64, 1 }, 535 536 { ISD::MUL, MVT::v32i8, 13 }, // extend/pmullw/trunc sequence. 537 { ISD::MUL, MVT::v16i8, 5 }, // extend/pmullw/trunc sequence. 538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 539 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 540 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 541 { ISD::MUL, MVT::v8i64, 8 }, // 3*pmuludq/3*shift/2*add 542 543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 544 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 545 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 546 547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 549 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 550 }; 551 552 if (ST->hasAVX512()) 553 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 554 return LT.first * Entry->Cost; 555 556 static const CostTblEntry AVX2ShiftCostTable[] = { 557 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 558 // customize them to detect the cases where shift amount is a scalar one. 559 { ISD::SHL, MVT::v4i32, 1 }, 560 { ISD::SRL, MVT::v4i32, 1 }, 561 { ISD::SRA, MVT::v4i32, 1 }, 562 { ISD::SHL, MVT::v8i32, 1 }, 563 { ISD::SRL, MVT::v8i32, 1 }, 564 { ISD::SRA, MVT::v8i32, 1 }, 565 { ISD::SHL, MVT::v2i64, 1 }, 566 { ISD::SRL, MVT::v2i64, 1 }, 567 { ISD::SHL, MVT::v4i64, 1 }, 568 { ISD::SRL, MVT::v4i64, 1 }, 569 }; 570 571 // Look for AVX2 lowering tricks. 572 if (ST->hasAVX2()) { 573 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 574 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 575 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 576 // On AVX2, a packed v16i16 shift left by a constant build_vector 577 // is lowered into a vector multiply (vpmullw). 578 return getArithmeticInstrCost(Instruction::Mul, Ty, Op1Info, Op2Info, 579 TargetTransformInfo::OP_None, 580 TargetTransformInfo::OP_None); 581 582 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 583 return LT.first * Entry->Cost; 584 } 585 586 static const CostTblEntry XOPShiftCostTable[] = { 587 // 128bit shifts take 1cy, but right shifts require negation beforehand. 588 { ISD::SHL, MVT::v16i8, 1 }, 589 { ISD::SRL, MVT::v16i8, 2 }, 590 { ISD::SRA, MVT::v16i8, 2 }, 591 { ISD::SHL, MVT::v8i16, 1 }, 592 { ISD::SRL, MVT::v8i16, 2 }, 593 { ISD::SRA, MVT::v8i16, 2 }, 594 { ISD::SHL, MVT::v4i32, 1 }, 595 { ISD::SRL, MVT::v4i32, 2 }, 596 { ISD::SRA, MVT::v4i32, 2 }, 597 { ISD::SHL, MVT::v2i64, 1 }, 598 { ISD::SRL, MVT::v2i64, 2 }, 599 { ISD::SRA, MVT::v2i64, 2 }, 600 // 256bit shifts require splitting if AVX2 didn't catch them above. 601 { ISD::SHL, MVT::v32i8, 2+2 }, 602 { ISD::SRL, MVT::v32i8, 4+2 }, 603 { ISD::SRA, MVT::v32i8, 4+2 }, 604 { ISD::SHL, MVT::v16i16, 2+2 }, 605 { ISD::SRL, MVT::v16i16, 4+2 }, 606 { ISD::SRA, MVT::v16i16, 4+2 }, 607 { ISD::SHL, MVT::v8i32, 2+2 }, 608 { ISD::SRL, MVT::v8i32, 4+2 }, 609 { ISD::SRA, MVT::v8i32, 4+2 }, 610 { ISD::SHL, MVT::v4i64, 2+2 }, 611 { ISD::SRL, MVT::v4i64, 4+2 }, 612 { ISD::SRA, MVT::v4i64, 4+2 }, 613 }; 614 615 // Look for XOP lowering tricks. 616 if (ST->hasXOP()) { 617 // If the right shift is constant then we'll fold the negation so 618 // it's as cheap as a left shift. 619 int ShiftISD = ISD; 620 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 621 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 622 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 623 ShiftISD = ISD::SHL; 624 if (const auto *Entry = 625 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 626 return LT.first * Entry->Cost; 627 } 628 629 static const CostTblEntry SSE2UniformShiftCostTable[] = { 630 // Uniform splats are cheaper for the following instructions. 631 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 632 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 634 635 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 636 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 637 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 638 639 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 640 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 641 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 642 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 643 }; 644 645 if (ST->hasSSE2() && 646 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 647 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 648 649 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 650 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 651 return LT.first * 4; // 2*psrad + shuffle. 652 653 if (const auto *Entry = 654 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 655 return LT.first * Entry->Cost; 656 } 657 658 if (ISD == ISD::SHL && 659 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 660 MVT VT = LT.second; 661 // Vector shift left by non uniform constant can be lowered 662 // into vector multiply. 663 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 664 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 665 ISD = ISD::MUL; 666 } 667 668 static const CostTblEntry AVX2CostTable[] = { 669 { ISD::SHL, MVT::v32i8, 11 }, // vpblendvb sequence. 670 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 671 672 { ISD::SRL, MVT::v32i8, 11 }, // vpblendvb sequence. 673 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. 674 675 { ISD::SRA, MVT::v32i8, 24 }, // vpblendvb sequence. 676 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. 677 { ISD::SRA, MVT::v2i64, 4 }, // srl/xor/sub sequence. 678 { ISD::SRA, MVT::v4i64, 4 }, // srl/xor/sub sequence. 679 680 { ISD::SUB, MVT::v32i8, 1 }, // psubb 681 { ISD::ADD, MVT::v32i8, 1 }, // paddb 682 { ISD::SUB, MVT::v16i16, 1 }, // psubw 683 { ISD::ADD, MVT::v16i16, 1 }, // paddw 684 { ISD::SUB, MVT::v8i32, 1 }, // psubd 685 { ISD::ADD, MVT::v8i32, 1 }, // paddd 686 { ISD::SUB, MVT::v4i64, 1 }, // psubq 687 { ISD::ADD, MVT::v4i64, 1 }, // paddq 688 689 { ISD::MUL, MVT::v32i8, 17 }, // extend/pmullw/trunc sequence. 690 { ISD::MUL, MVT::v16i8, 7 }, // extend/pmullw/trunc sequence. 691 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 692 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 693 { ISD::MUL, MVT::v4i64, 8 }, // 3*pmuludq/3*shift/2*add 694 695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 697 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 699 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 700 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 701 702 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 703 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 704 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 705 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 706 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 707 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 708 }; 709 710 // Look for AVX2 lowering tricks for custom cases. 711 if (ST->hasAVX2()) 712 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 713 return LT.first * Entry->Cost; 714 715 static const CostTblEntry AVX1CostTable[] = { 716 // We don't have to scalarize unsupported ops. We can issue two half-sized 717 // operations and we only need to extract the upper YMM half. 718 // Two ops + 1 extract + 1 insert = 4. 719 { ISD::MUL, MVT::v16i16, 4 }, 720 { ISD::MUL, MVT::v8i32, 4 }, 721 { ISD::SUB, MVT::v32i8, 4 }, 722 { ISD::ADD, MVT::v32i8, 4 }, 723 { ISD::SUB, MVT::v16i16, 4 }, 724 { ISD::ADD, MVT::v16i16, 4 }, 725 { ISD::SUB, MVT::v8i32, 4 }, 726 { ISD::ADD, MVT::v8i32, 4 }, 727 { ISD::SUB, MVT::v4i64, 4 }, 728 { ISD::ADD, MVT::v4i64, 4 }, 729 730 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 731 // are lowered as a series of long multiplies(3), shifts(3) and adds(2) 732 // Because we believe v4i64 to be a legal type, we must also include the 733 // extract+insert in the cost table. Therefore, the cost here is 18 734 // instead of 8. 735 { ISD::MUL, MVT::v4i64, 18 }, 736 737 { ISD::MUL, MVT::v32i8, 26 }, // extend/pmullw/trunc sequence. 738 739 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 740 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 741 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 742 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 743 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 744 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 745 }; 746 747 if (ST->hasAVX()) 748 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 749 return LT.first * Entry->Cost; 750 751 static const CostTblEntry SSE42CostTable[] = { 752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 756 757 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 758 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 759 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 760 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 761 762 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 763 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 764 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 765 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 766 767 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 768 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 769 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 770 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 771 }; 772 773 if (ST->hasSSE42()) 774 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 775 return LT.first * Entry->Cost; 776 777 static const CostTblEntry SSE41CostTable[] = { 778 { ISD::SHL, MVT::v16i8, 11 }, // pblendvb sequence. 779 { ISD::SHL, MVT::v32i8, 2*11+2 }, // pblendvb sequence + split. 780 { ISD::SHL, MVT::v8i16, 14 }, // pblendvb sequence. 781 { ISD::SHL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 782 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 783 { ISD::SHL, MVT::v8i32, 2*4+2 }, // pslld/paddd/cvttps2dq/pmulld + split 784 785 { ISD::SRL, MVT::v16i8, 12 }, // pblendvb sequence. 786 { ISD::SRL, MVT::v32i8, 2*12+2 }, // pblendvb sequence + split. 787 { ISD::SRL, MVT::v8i16, 14 }, // pblendvb sequence. 788 { ISD::SRL, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 789 { ISD::SRL, MVT::v4i32, 11 }, // Shift each lane + blend. 790 { ISD::SRL, MVT::v8i32, 2*11+2 }, // Shift each lane + blend + split. 791 792 { ISD::SRA, MVT::v16i8, 24 }, // pblendvb sequence. 793 { ISD::SRA, MVT::v32i8, 2*24+2 }, // pblendvb sequence + split. 794 { ISD::SRA, MVT::v8i16, 14 }, // pblendvb sequence. 795 { ISD::SRA, MVT::v16i16, 2*14+2 }, // pblendvb sequence + split. 796 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 797 { ISD::SRA, MVT::v8i32, 2*12+2 }, // Shift each lane + blend + split. 798 799 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 800 }; 801 802 if (ST->hasSSE41()) 803 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 806 static const CostTblEntry SSE2CostTable[] = { 807 // We don't correctly identify costs of casts because they are marked as 808 // custom. 809 { ISD::SHL, MVT::v16i8, 26 }, // cmpgtb sequence. 810 { ISD::SHL, MVT::v8i16, 32 }, // cmpgtb sequence. 811 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 812 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 813 { ISD::SHL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 814 815 { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence. 816 { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence. 817 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 818 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 819 { ISD::SRL, MVT::v4i64, 2*4+2 }, // splat+shuffle sequence + split. 820 821 { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence. 822 { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence. 823 { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend. 824 { ISD::SRA, MVT::v2i64, 12 }, // srl/xor/sub sequence. 825 { ISD::SRA, MVT::v4i64, 2*12+2 }, // srl/xor/sub sequence+split. 826 827 { ISD::MUL, MVT::v16i8, 12 }, // extend/pmullw/trunc sequence. 828 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 829 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 830 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 831 832 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 833 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 834 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 835 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 836 837 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 838 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 839 840 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 841 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 842 }; 843 844 if (ST->hasSSE2()) 845 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 846 return LT.first * Entry->Cost; 847 848 static const CostTblEntry SSE1CostTable[] = { 849 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 850 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 851 852 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 853 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 854 855 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 856 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 857 858 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 859 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 860 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 861 862 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 863 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 864 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 865 }; 866 867 if (ST->hasSSE1()) 868 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 869 return LT.first * Entry->Cost; 870 871 // It is not a good idea to vectorize division. We have to scalarize it and 872 // in the process we will often end up having to spilling regular 873 // registers. The overhead of division is going to dominate most kernels 874 // anyways so try hard to prevent vectorization of division - it is 875 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 876 // to hide "20 cycles" for each lane. 877 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 878 ISD == ISD::UDIV || ISD == ISD::UREM)) { 879 int ScalarCost = getArithmeticInstrCost( 880 Opcode, Ty->getScalarType(), Op1Info, Op2Info, 881 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 882 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 883 } 884 885 // Fallback to the default implementation. 886 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info); 887 } 888 889 int X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, 890 Type *SubTp) { 891 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 892 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 893 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp); 894 895 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 896 if (Kind == TTI::SK_Transpose) 897 Kind = TTI::SK_PermuteTwoSrc; 898 899 // For Broadcasts we are splatting the first element from the first input 900 // register, so only need to reference that input and all the output 901 // registers are the same. 902 if (Kind == TTI::SK_Broadcast) 903 LT.first = 1; 904 905 // Subvector extractions are free if they start at the beginning of a 906 // vector and cheap if the subvectors are aligned. 907 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 908 int NumElts = LT.second.getVectorNumElements(); 909 if ((Index % NumElts) == 0) 910 return 0; 911 std::pair<int, MVT> SubLT = TLI->getTypeLegalizationCost(DL, SubTp); 912 if (SubLT.second.isVector()) { 913 int NumSubElts = SubLT.second.getVectorNumElements(); 914 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 915 return SubLT.first; 916 // Handle some cases for widening legalization. For now we only handle 917 // cases where the original subvector was naturally aligned and evenly 918 // fit in its legalized subvector type. 919 // FIXME: Remove some of the alignment restrictions. 920 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 921 // vectors. 922 int OrigSubElts = SubTp->getVectorNumElements(); 923 if (ExperimentalVectorWideningLegalization && 924 NumSubElts > OrigSubElts && 925 (Index % OrigSubElts) == 0 && (NumSubElts % OrigSubElts) == 0 && 926 LT.second.getVectorElementType() == 927 SubLT.second.getVectorElementType() && 928 LT.second.getVectorElementType().getSizeInBits() == 929 Tp->getVectorElementType()->getPrimitiveSizeInBits()) { 930 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 931 "Unexpected number of elements!"); 932 Type *VecTy = VectorType::get(Tp->getVectorElementType(), 933 LT.second.getVectorNumElements()); 934 Type *SubTy = VectorType::get(Tp->getVectorElementType(), 935 SubLT.second.getVectorNumElements()); 936 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 937 int ExtractCost = getShuffleCost(TTI::SK_ExtractSubvector, VecTy, 938 ExtractIndex, SubTy); 939 940 // If the original size is 32-bits or more, we can use pshufd. Otherwise 941 // if we have SSSE3 we can use pshufb. 942 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 943 return ExtractCost + 1; // pshufd or pshufb 944 945 assert(SubTp->getPrimitiveSizeInBits() == 16 && 946 "Unexpected vector size"); 947 948 return ExtractCost + 2; // worst case pshufhw + pshufd 949 } 950 } 951 } 952 953 // We are going to permute multiple sources and the result will be in multiple 954 // destinations. Providing an accurate cost only for splits where the element 955 // type remains the same. 956 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 957 MVT LegalVT = LT.second; 958 if (LegalVT.isVector() && 959 LegalVT.getVectorElementType().getSizeInBits() == 960 Tp->getVectorElementType()->getPrimitiveSizeInBits() && 961 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) { 962 963 unsigned VecTySize = DL.getTypeStoreSize(Tp); 964 unsigned LegalVTSize = LegalVT.getStoreSize(); 965 // Number of source vectors after legalization: 966 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 967 // Number of destination vectors after legalization: 968 unsigned NumOfDests = LT.first; 969 970 Type *SingleOpTy = VectorType::get(Tp->getVectorElementType(), 971 LegalVT.getVectorNumElements()); 972 973 unsigned NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 974 return NumOfShuffles * 975 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 0, nullptr); 976 } 977 978 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 979 } 980 981 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 982 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 983 // We assume that source and destination have the same vector type. 984 int NumOfDests = LT.first; 985 int NumOfShufflesPerDest = LT.first * 2 - 1; 986 LT.first = NumOfDests * NumOfShufflesPerDest; 987 } 988 989 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 990 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 991 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 992 993 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 994 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 995 996 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 1}, // vpermt2b 997 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 1}, // vpermt2b 998 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1} // vpermt2b 999 }; 1000 1001 if (ST->hasVBMI()) 1002 if (const auto *Entry = 1003 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1004 return LT.first * Entry->Cost; 1005 1006 static const CostTblEntry AVX512BWShuffleTbl[] = { 1007 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1008 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1009 1010 {TTI::SK_Reverse, MVT::v32i16, 1}, // vpermw 1011 {TTI::SK_Reverse, MVT::v16i16, 1}, // vpermw 1012 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1013 1014 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 1}, // vpermw 1015 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 1}, // vpermw 1016 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // vpermw 1017 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1018 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 3}, // vpermw + zext/trunc 1019 1020 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 1}, // vpermt2w 1021 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 1}, // vpermt2w 1022 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpermt2w 1023 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 3}, // zext + vpermt2w + trunc 1024 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1025 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3} // zext + vpermt2w + trunc 1026 }; 1027 1028 if (ST->hasBWI()) 1029 if (const auto *Entry = 1030 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1031 return LT.first * Entry->Cost; 1032 1033 static const CostTblEntry AVX512ShuffleTbl[] = { 1034 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1035 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1036 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1037 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1038 1039 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1040 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1041 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1042 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1043 1044 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1045 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1046 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1047 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1048 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1049 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1050 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1051 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1052 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1053 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1054 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1055 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1056 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1057 1058 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1059 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1060 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1061 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1062 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1063 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1064 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1065 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1066 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1067 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1068 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1069 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1} // vpermt2d 1070 }; 1071 1072 if (ST->hasAVX512()) 1073 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1074 return LT.first * Entry->Cost; 1075 1076 static const CostTblEntry AVX2ShuffleTbl[] = { 1077 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1078 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1079 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1080 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1081 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1082 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1083 1084 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1085 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1086 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1087 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1088 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1089 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1090 1091 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1092 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1093 1094 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1095 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1096 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1097 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1098 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1099 // + vpblendvb 1100 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1101 // + vpblendvb 1102 1103 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1104 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1105 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1106 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1107 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1108 // + vpblendvb 1109 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1110 // + vpblendvb 1111 }; 1112 1113 if (ST->hasAVX2()) 1114 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1115 return LT.first * Entry->Cost; 1116 1117 static const CostTblEntry XOPShuffleTbl[] = { 1118 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1119 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1120 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1121 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1122 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1123 // + vinsertf128 1124 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1125 // + vinsertf128 1126 1127 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1128 // + vinsertf128 1129 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1130 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1131 // + vinsertf128 1132 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1133 }; 1134 1135 if (ST->hasXOP()) 1136 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1137 return LT.first * Entry->Cost; 1138 1139 static const CostTblEntry AVX1ShuffleTbl[] = { 1140 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1141 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1142 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1143 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1144 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1145 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1146 1147 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1148 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1149 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1150 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1151 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1152 // + vinsertf128 1153 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1154 // + vinsertf128 1155 1156 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1157 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1158 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1159 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1160 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1161 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1162 1163 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1164 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1165 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1166 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1167 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1168 // + 2*por + vinsertf128 1169 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1170 // + 2*por + vinsertf128 1171 1172 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1173 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1174 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1175 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1176 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1177 // + 4*por + vinsertf128 1178 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1179 // + 4*por + vinsertf128 1180 }; 1181 1182 if (ST->hasAVX()) 1183 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1184 return LT.first * Entry->Cost; 1185 1186 static const CostTblEntry SSE41ShuffleTbl[] = { 1187 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1188 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1189 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1190 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1191 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1192 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1193 }; 1194 1195 if (ST->hasSSE41()) 1196 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1197 return LT.first * Entry->Cost; 1198 1199 static const CostTblEntry SSSE3ShuffleTbl[] = { 1200 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1201 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1202 1203 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1204 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1205 1206 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1207 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1208 1209 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1210 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1211 1212 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1213 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1214 }; 1215 1216 if (ST->hasSSSE3()) 1217 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1218 return LT.first * Entry->Cost; 1219 1220 static const CostTblEntry SSE2ShuffleTbl[] = { 1221 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1222 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1223 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1224 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1225 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1226 1227 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1228 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1229 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1230 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1231 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1232 // + 2*pshufd + 2*unpck + packus 1233 1234 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1235 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1236 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1237 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1238 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1239 1240 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1241 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1242 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1243 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1244 // + pshufd/unpck 1245 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1246 // + 2*pshufd + 2*unpck + 2*packus 1247 1248 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1249 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1250 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1251 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1252 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1253 }; 1254 1255 if (ST->hasSSE2()) 1256 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1257 return LT.first * Entry->Cost; 1258 1259 static const CostTblEntry SSE1ShuffleTbl[] = { 1260 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1261 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1262 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1263 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1264 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1265 }; 1266 1267 if (ST->hasSSE1()) 1268 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1269 return LT.first * Entry->Cost; 1270 1271 return BaseT::getShuffleCost(Kind, Tp, Index, SubTp); 1272 } 1273 1274 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 1275 const Instruction *I) { 1276 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1277 assert(ISD && "Invalid opcode"); 1278 1279 // FIXME: Need a better design of the cost table to handle non-simple types of 1280 // potential massive combinations (elem_num x src_type x dst_type). 1281 1282 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1283 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1284 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1285 1286 // Mask sign extend has an instruction. 1287 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1288 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1289 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1290 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1291 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1292 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1293 1294 // Mask zero extend is a load + broadcast. 1295 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1296 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1297 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1298 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1299 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1300 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1301 }; 1302 1303 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1304 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1305 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1306 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1307 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1308 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1309 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1310 1311 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 1312 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 1313 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 1314 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 1315 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1316 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1317 1318 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 1 }, 1319 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 1320 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1321 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 1322 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 1323 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1324 1325 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 1 }, 1326 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 1327 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1328 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 1329 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 1330 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1331 }; 1332 1333 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1334 // 256-bit wide vectors. 1335 1336 // Used with widening legalization 1337 static const TypeConversionCostTblEntry AVX512FConversionTblWide[] = { 1338 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1339 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1340 }; 1341 1342 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1343 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1344 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1345 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1346 1347 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, 1348 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, 1349 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 1 }, 1350 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, 1351 1352 // v16i1 -> v16i32 - load + broadcast 1353 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1354 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1355 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1356 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1357 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1358 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1359 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1360 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1361 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1362 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1363 1364 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1365 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1366 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1367 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1368 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1369 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1370 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1371 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1372 1373 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1374 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1375 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 2 }, 1376 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1377 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 2 }, 1378 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i8, 2 }, 1379 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, 1380 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 5 }, 1381 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1382 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 1383 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1384 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 2 }, 1385 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 1386 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 1387 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1388 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1389 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1390 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1391 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1392 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 1393 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1394 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1395 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 1396 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1397 1398 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 1399 1400 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 1401 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 1402 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 1403 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 1404 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 2 }, 1405 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 2 }, 1406 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1407 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 2 }, 1408 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 2 }, 1409 }; 1410 1411 static const TypeConversionCostTblEntry AVX2ConversionTblWide[] = { 1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 }, 1414 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1415 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 }, 1416 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1417 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, 1418 }; 1419 1420 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 1421 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1422 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 1423 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1424 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 1425 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1426 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 }, 1427 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1428 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, 1429 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1430 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 1431 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1432 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1433 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1434 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 1435 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1436 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 1437 1438 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, 1439 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 1440 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 1441 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, 1442 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 1443 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 }, 1444 1445 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 1446 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 1447 1448 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 1449 }; 1450 1451 static const TypeConversionCostTblEntry AVXConversionTblWide[] = { 1452 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1453 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1454 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, 1455 }; 1456 1457 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 1458 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 1459 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 1460 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 1461 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 1462 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 1463 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1464 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 }, 1465 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 }, 1466 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1467 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1468 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 1469 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1470 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1471 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1472 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1473 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 }, 1474 1475 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 }, 1476 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1477 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1478 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 }, 1479 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 1480 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 }, 1481 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 }, 1482 1483 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 1484 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 1485 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 1486 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 1487 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 1488 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 1489 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 1490 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 1491 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1492 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 1493 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 1494 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 1495 1496 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 1497 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 1498 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 1499 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 1500 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 1501 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 1502 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 1503 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 1504 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 1505 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 }, 1506 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 1507 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 1508 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 1509 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 1510 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 6 }, 1511 // The generic code to compute the scalar overhead is currently broken. 1512 // Workaround this limitation by estimating the scalarization overhead 1513 // here. We have roughly 10 instructions per scalar element. 1514 // Multiply that by the vector width. 1515 // FIXME: remove that when PR19268 is fixed. 1516 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1517 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 13 }, 1518 1519 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 1520 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, 1521 // This node is expanded into scalarized operations but BasicTTI is overly 1522 // optimistic estimating its cost. It computes 3 per element (one 1523 // vector-extract, one scalar conversion and one vector-insert). The 1524 // problem is that the inserts form a read-modify-write chain so latency 1525 // should be factored in too. Inflating the cost per element by 1. 1526 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 }, 1527 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 }, 1528 1529 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 1530 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 1531 }; 1532 1533 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 1534 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1535 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 }, 1536 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1537 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 2 }, 1538 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1539 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 1540 1541 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1542 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 }, 1543 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1544 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 }, 1545 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1546 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1547 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1548 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 2 }, 1549 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1550 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 1551 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1552 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 4 }, 1553 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1554 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1555 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1556 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 1557 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1558 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 }, 1559 1560 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, 1561 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 1 }, 1562 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 }, 1563 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 1564 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 1565 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 3 }, 1566 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 1567 1568 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 1569 }; 1570 1571 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 1572 // These are somewhat magic numbers justified by looking at the output of 1573 // Intel's IACA, running some kernels and making sure when we take 1574 // legalization into account the throughput will be overestimated. 1575 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1576 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1577 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1578 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1579 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 1580 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1581 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1582 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 1583 1584 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 1585 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 1586 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 1587 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 1588 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 1589 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, 1590 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 6 }, 1591 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 1592 1593 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 }, 1594 1595 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 }, 1596 1597 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 }, 1598 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 }, 1599 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 }, 1600 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 }, 1601 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 }, 1602 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 }, 1603 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 }, 1604 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 2 }, 1605 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1606 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 6 }, 1607 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 1608 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 }, 1609 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 }, 1610 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 12 }, 1611 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 }, 1612 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 2 }, 1613 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 1614 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 10 }, 1615 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 1616 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 }, 1617 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 }, 1618 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 }, 1619 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 1620 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 5 }, 1621 1622 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 }, 1623 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, 1624 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 1625 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 }, 1626 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 3 }, 1627 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 }, 1628 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 1629 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 1630 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 10 }, 1631 }; 1632 1633 std::pair<int, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 1634 std::pair<int, MVT> LTDest = TLI->getTypeLegalizationCost(DL, Dst); 1635 1636 if (ST->hasSSE2() && !ST->hasAVX()) { 1637 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1638 LTDest.second, LTSrc.second)) 1639 return LTSrc.first * Entry->Cost; 1640 } 1641 1642 EVT SrcTy = TLI->getValueType(DL, Src); 1643 EVT DstTy = TLI->getValueType(DL, Dst); 1644 1645 // The function getSimpleVT only handles simple value types. 1646 if (!SrcTy.isSimple() || !DstTy.isSimple()) 1647 return BaseT::getCastInstrCost(Opcode, Dst, Src); 1648 1649 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 1650 MVT SimpleDstTy = DstTy.getSimpleVT(); 1651 1652 // Make sure that neither type is going to be split before using the 1653 // AVX512 tables. This handles -mprefer-vector-width=256 1654 // with -min-legal-vector-width<=256 1655 if (TLI->getTypeAction(SimpleSrcTy) != TargetLowering::TypeSplitVector && 1656 TLI->getTypeAction(SimpleDstTy) != TargetLowering::TypeSplitVector) { 1657 if (ST->hasBWI()) 1658 if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, 1659 SimpleDstTy, SimpleSrcTy)) 1660 return Entry->Cost; 1661 1662 if (ST->hasDQI()) 1663 if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, 1664 SimpleDstTy, SimpleSrcTy)) 1665 return Entry->Cost; 1666 1667 if (ST->hasAVX512() && ExperimentalVectorWideningLegalization) 1668 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTblWide, ISD, 1669 SimpleDstTy, SimpleSrcTy)) 1670 return Entry->Cost; 1671 1672 if (ST->hasAVX512()) 1673 if (const auto *Entry = ConvertCostTableLookup(AVX512FConversionTbl, ISD, 1674 SimpleDstTy, SimpleSrcTy)) 1675 return Entry->Cost; 1676 } 1677 1678 if (ST->hasAVX2() && ExperimentalVectorWideningLegalization) { 1679 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTblWide, ISD, 1680 SimpleDstTy, SimpleSrcTy)) 1681 return Entry->Cost; 1682 } 1683 1684 if (ST->hasAVX2()) { 1685 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 1686 SimpleDstTy, SimpleSrcTy)) 1687 return Entry->Cost; 1688 } 1689 1690 if (ST->hasAVX() && ExperimentalVectorWideningLegalization) { 1691 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTblWide, ISD, 1692 SimpleDstTy, SimpleSrcTy)) 1693 return Entry->Cost; 1694 } 1695 1696 if (ST->hasAVX()) { 1697 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 1698 SimpleDstTy, SimpleSrcTy)) 1699 return Entry->Cost; 1700 } 1701 1702 if (ST->hasSSE41()) { 1703 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 1704 SimpleDstTy, SimpleSrcTy)) 1705 return Entry->Cost; 1706 } 1707 1708 if (ST->hasSSE2()) { 1709 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 1710 SimpleDstTy, SimpleSrcTy)) 1711 return Entry->Cost; 1712 } 1713 1714 return BaseT::getCastInstrCost(Opcode, Dst, Src, I); 1715 } 1716 1717 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 1718 const Instruction *I) { 1719 // Legalize the type. 1720 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 1721 1722 MVT MTy = LT.second; 1723 1724 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1725 assert(ISD && "Invalid opcode"); 1726 1727 unsigned ExtraCost = 0; 1728 if (I && (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp)) { 1729 // Some vector comparison predicates cost extra instructions. 1730 if (MTy.isVector() && 1731 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 1732 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 1733 ST->hasBWI())) { 1734 switch (cast<CmpInst>(I)->getPredicate()) { 1735 case CmpInst::Predicate::ICMP_NE: 1736 // xor(cmpeq(x,y),-1) 1737 ExtraCost = 1; 1738 break; 1739 case CmpInst::Predicate::ICMP_SGE: 1740 case CmpInst::Predicate::ICMP_SLE: 1741 // xor(cmpgt(x,y),-1) 1742 ExtraCost = 1; 1743 break; 1744 case CmpInst::Predicate::ICMP_ULT: 1745 case CmpInst::Predicate::ICMP_UGT: 1746 // cmpgt(xor(x,signbit),xor(y,signbit)) 1747 // xor(cmpeq(pmaxu(x,y),x),-1) 1748 ExtraCost = 2; 1749 break; 1750 case CmpInst::Predicate::ICMP_ULE: 1751 case CmpInst::Predicate::ICMP_UGE: 1752 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 1753 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 1754 // cmpeq(psubus(x,y),0) 1755 // cmpeq(pminu(x,y),x) 1756 ExtraCost = 1; 1757 } else { 1758 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 1759 ExtraCost = 3; 1760 } 1761 break; 1762 default: 1763 break; 1764 } 1765 } 1766 } 1767 1768 static const CostTblEntry AVX512BWCostTbl[] = { 1769 { ISD::SETCC, MVT::v32i16, 1 }, 1770 { ISD::SETCC, MVT::v64i8, 1 }, 1771 1772 { ISD::SELECT, MVT::v32i16, 1 }, 1773 { ISD::SELECT, MVT::v64i8, 1 }, 1774 }; 1775 1776 static const CostTblEntry AVX512CostTbl[] = { 1777 { ISD::SETCC, MVT::v8i64, 1 }, 1778 { ISD::SETCC, MVT::v16i32, 1 }, 1779 { ISD::SETCC, MVT::v8f64, 1 }, 1780 { ISD::SETCC, MVT::v16f32, 1 }, 1781 1782 { ISD::SELECT, MVT::v8i64, 1 }, 1783 { ISD::SELECT, MVT::v16i32, 1 }, 1784 { ISD::SELECT, MVT::v8f64, 1 }, 1785 { ISD::SELECT, MVT::v16f32, 1 }, 1786 }; 1787 1788 static const CostTblEntry AVX2CostTbl[] = { 1789 { ISD::SETCC, MVT::v4i64, 1 }, 1790 { ISD::SETCC, MVT::v8i32, 1 }, 1791 { ISD::SETCC, MVT::v16i16, 1 }, 1792 { ISD::SETCC, MVT::v32i8, 1 }, 1793 1794 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 1795 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 1796 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 1797 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 1798 }; 1799 1800 static const CostTblEntry AVX1CostTbl[] = { 1801 { ISD::SETCC, MVT::v4f64, 1 }, 1802 { ISD::SETCC, MVT::v8f32, 1 }, 1803 // AVX1 does not support 8-wide integer compare. 1804 { ISD::SETCC, MVT::v4i64, 4 }, 1805 { ISD::SETCC, MVT::v8i32, 4 }, 1806 { ISD::SETCC, MVT::v16i16, 4 }, 1807 { ISD::SETCC, MVT::v32i8, 4 }, 1808 1809 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 1810 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 1811 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 1812 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 1813 { ISD::SELECT, MVT::v16i16, 3 }, // vandps + vandnps + vorps 1814 { ISD::SELECT, MVT::v32i8, 3 }, // vandps + vandnps + vorps 1815 }; 1816 1817 static const CostTblEntry SSE42CostTbl[] = { 1818 { ISD::SETCC, MVT::v2f64, 1 }, 1819 { ISD::SETCC, MVT::v4f32, 1 }, 1820 { ISD::SETCC, MVT::v2i64, 1 }, 1821 }; 1822 1823 static const CostTblEntry SSE41CostTbl[] = { 1824 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 1825 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 1826 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 1827 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 1828 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 1829 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 1830 }; 1831 1832 static const CostTblEntry SSE2CostTbl[] = { 1833 { ISD::SETCC, MVT::v2f64, 2 }, 1834 { ISD::SETCC, MVT::f64, 1 }, 1835 { ISD::SETCC, MVT::v2i64, 8 }, 1836 { ISD::SETCC, MVT::v4i32, 1 }, 1837 { ISD::SETCC, MVT::v8i16, 1 }, 1838 { ISD::SETCC, MVT::v16i8, 1 }, 1839 1840 { ISD::SELECT, MVT::v2f64, 3 }, // andpd + andnpd + orpd 1841 { ISD::SELECT, MVT::v2i64, 3 }, // pand + pandn + por 1842 { ISD::SELECT, MVT::v4i32, 3 }, // pand + pandn + por 1843 { ISD::SELECT, MVT::v8i16, 3 }, // pand + pandn + por 1844 { ISD::SELECT, MVT::v16i8, 3 }, // pand + pandn + por 1845 }; 1846 1847 static const CostTblEntry SSE1CostTbl[] = { 1848 { ISD::SETCC, MVT::v4f32, 2 }, 1849 { ISD::SETCC, MVT::f32, 1 }, 1850 1851 { ISD::SELECT, MVT::v4f32, 3 }, // andps + andnps + orps 1852 }; 1853 1854 if (ST->hasBWI()) 1855 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 1856 return LT.first * (ExtraCost + Entry->Cost); 1857 1858 if (ST->hasAVX512()) 1859 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 1860 return LT.first * (ExtraCost + Entry->Cost); 1861 1862 if (ST->hasAVX2()) 1863 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 1864 return LT.first * (ExtraCost + Entry->Cost); 1865 1866 if (ST->hasAVX()) 1867 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 1868 return LT.first * (ExtraCost + Entry->Cost); 1869 1870 if (ST->hasSSE42()) 1871 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 1872 return LT.first * (ExtraCost + Entry->Cost); 1873 1874 if (ST->hasSSE41()) 1875 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 1876 return LT.first * (ExtraCost + Entry->Cost); 1877 1878 if (ST->hasSSE2()) 1879 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 1880 return LT.first * (ExtraCost + Entry->Cost); 1881 1882 if (ST->hasSSE1()) 1883 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 1884 return LT.first * (ExtraCost + Entry->Cost); 1885 1886 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I); 1887 } 1888 1889 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 1890 1891 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 1892 ArrayRef<Type *> Tys, FastMathFlags FMF, 1893 unsigned ScalarizationCostPassed) { 1894 // Costs should match the codegen from: 1895 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 1896 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 1897 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 1898 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 1899 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 1900 static const CostTblEntry AVX512CDCostTbl[] = { 1901 { ISD::CTLZ, MVT::v8i64, 1 }, 1902 { ISD::CTLZ, MVT::v16i32, 1 }, 1903 { ISD::CTLZ, MVT::v32i16, 8 }, 1904 { ISD::CTLZ, MVT::v64i8, 20 }, 1905 { ISD::CTLZ, MVT::v4i64, 1 }, 1906 { ISD::CTLZ, MVT::v8i32, 1 }, 1907 { ISD::CTLZ, MVT::v16i16, 4 }, 1908 { ISD::CTLZ, MVT::v32i8, 10 }, 1909 { ISD::CTLZ, MVT::v2i64, 1 }, 1910 { ISD::CTLZ, MVT::v4i32, 1 }, 1911 { ISD::CTLZ, MVT::v8i16, 4 }, 1912 { ISD::CTLZ, MVT::v16i8, 4 }, 1913 }; 1914 static const CostTblEntry AVX512BWCostTbl[] = { 1915 { ISD::BITREVERSE, MVT::v8i64, 5 }, 1916 { ISD::BITREVERSE, MVT::v16i32, 5 }, 1917 { ISD::BITREVERSE, MVT::v32i16, 5 }, 1918 { ISD::BITREVERSE, MVT::v64i8, 5 }, 1919 { ISD::CTLZ, MVT::v8i64, 23 }, 1920 { ISD::CTLZ, MVT::v16i32, 22 }, 1921 { ISD::CTLZ, MVT::v32i16, 18 }, 1922 { ISD::CTLZ, MVT::v64i8, 17 }, 1923 { ISD::CTPOP, MVT::v8i64, 7 }, 1924 { ISD::CTPOP, MVT::v16i32, 11 }, 1925 { ISD::CTPOP, MVT::v32i16, 9 }, 1926 { ISD::CTPOP, MVT::v64i8, 6 }, 1927 { ISD::CTTZ, MVT::v8i64, 10 }, 1928 { ISD::CTTZ, MVT::v16i32, 14 }, 1929 { ISD::CTTZ, MVT::v32i16, 12 }, 1930 { ISD::CTTZ, MVT::v64i8, 9 }, 1931 { ISD::SADDSAT, MVT::v32i16, 1 }, 1932 { ISD::SADDSAT, MVT::v64i8, 1 }, 1933 { ISD::SSUBSAT, MVT::v32i16, 1 }, 1934 { ISD::SSUBSAT, MVT::v64i8, 1 }, 1935 { ISD::UADDSAT, MVT::v32i16, 1 }, 1936 { ISD::UADDSAT, MVT::v64i8, 1 }, 1937 { ISD::USUBSAT, MVT::v32i16, 1 }, 1938 { ISD::USUBSAT, MVT::v64i8, 1 }, 1939 }; 1940 static const CostTblEntry AVX512CostTbl[] = { 1941 { ISD::BITREVERSE, MVT::v8i64, 36 }, 1942 { ISD::BITREVERSE, MVT::v16i32, 24 }, 1943 { ISD::CTLZ, MVT::v8i64, 29 }, 1944 { ISD::CTLZ, MVT::v16i32, 35 }, 1945 { ISD::CTPOP, MVT::v8i64, 16 }, 1946 { ISD::CTPOP, MVT::v16i32, 24 }, 1947 { ISD::CTTZ, MVT::v8i64, 20 }, 1948 { ISD::CTTZ, MVT::v16i32, 28 }, 1949 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 1950 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 1951 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 1952 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 1953 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 1954 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 1955 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 1956 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 1957 }; 1958 static const CostTblEntry XOPCostTbl[] = { 1959 { ISD::BITREVERSE, MVT::v4i64, 4 }, 1960 { ISD::BITREVERSE, MVT::v8i32, 4 }, 1961 { ISD::BITREVERSE, MVT::v16i16, 4 }, 1962 { ISD::BITREVERSE, MVT::v32i8, 4 }, 1963 { ISD::BITREVERSE, MVT::v2i64, 1 }, 1964 { ISD::BITREVERSE, MVT::v4i32, 1 }, 1965 { ISD::BITREVERSE, MVT::v8i16, 1 }, 1966 { ISD::BITREVERSE, MVT::v16i8, 1 }, 1967 { ISD::BITREVERSE, MVT::i64, 3 }, 1968 { ISD::BITREVERSE, MVT::i32, 3 }, 1969 { ISD::BITREVERSE, MVT::i16, 3 }, 1970 { ISD::BITREVERSE, MVT::i8, 3 } 1971 }; 1972 static const CostTblEntry AVX2CostTbl[] = { 1973 { ISD::BITREVERSE, MVT::v4i64, 5 }, 1974 { ISD::BITREVERSE, MVT::v8i32, 5 }, 1975 { ISD::BITREVERSE, MVT::v16i16, 5 }, 1976 { ISD::BITREVERSE, MVT::v32i8, 5 }, 1977 { ISD::BSWAP, MVT::v4i64, 1 }, 1978 { ISD::BSWAP, MVT::v8i32, 1 }, 1979 { ISD::BSWAP, MVT::v16i16, 1 }, 1980 { ISD::CTLZ, MVT::v4i64, 23 }, 1981 { ISD::CTLZ, MVT::v8i32, 18 }, 1982 { ISD::CTLZ, MVT::v16i16, 14 }, 1983 { ISD::CTLZ, MVT::v32i8, 9 }, 1984 { ISD::CTPOP, MVT::v4i64, 7 }, 1985 { ISD::CTPOP, MVT::v8i32, 11 }, 1986 { ISD::CTPOP, MVT::v16i16, 9 }, 1987 { ISD::CTPOP, MVT::v32i8, 6 }, 1988 { ISD::CTTZ, MVT::v4i64, 10 }, 1989 { ISD::CTTZ, MVT::v8i32, 14 }, 1990 { ISD::CTTZ, MVT::v16i16, 12 }, 1991 { ISD::CTTZ, MVT::v32i8, 9 }, 1992 { ISD::SADDSAT, MVT::v16i16, 1 }, 1993 { ISD::SADDSAT, MVT::v32i8, 1 }, 1994 { ISD::SSUBSAT, MVT::v16i16, 1 }, 1995 { ISD::SSUBSAT, MVT::v32i8, 1 }, 1996 { ISD::UADDSAT, MVT::v16i16, 1 }, 1997 { ISD::UADDSAT, MVT::v32i8, 1 }, 1998 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 1999 { ISD::USUBSAT, MVT::v16i16, 1 }, 2000 { ISD::USUBSAT, MVT::v32i8, 1 }, 2001 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 2002 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 2003 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 2004 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 2005 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 2006 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 2007 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 2008 }; 2009 static const CostTblEntry AVX1CostTbl[] = { 2010 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 2011 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 2012 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 2013 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 2014 { ISD::BSWAP, MVT::v4i64, 4 }, 2015 { ISD::BSWAP, MVT::v8i32, 4 }, 2016 { ISD::BSWAP, MVT::v16i16, 4 }, 2017 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 2018 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 2019 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 2020 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2021 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 2022 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 2023 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 2024 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 2025 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 2026 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 2027 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 2028 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 2029 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2030 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2031 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2032 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2033 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2034 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2035 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 2036 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 2037 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 2038 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 2039 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 2040 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 2041 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 2042 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 2043 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 2044 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 2045 }; 2046 static const CostTblEntry GLMCostTbl[] = { 2047 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 2048 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 2049 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 2050 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 2051 }; 2052 static const CostTblEntry SLMCostTbl[] = { 2053 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 2054 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 2055 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 2056 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 2057 }; 2058 static const CostTblEntry SSE42CostTbl[] = { 2059 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 2060 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 2061 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 2062 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 2063 }; 2064 static const CostTblEntry SSSE3CostTbl[] = { 2065 { ISD::BITREVERSE, MVT::v2i64, 5 }, 2066 { ISD::BITREVERSE, MVT::v4i32, 5 }, 2067 { ISD::BITREVERSE, MVT::v8i16, 5 }, 2068 { ISD::BITREVERSE, MVT::v16i8, 5 }, 2069 { ISD::BSWAP, MVT::v2i64, 1 }, 2070 { ISD::BSWAP, MVT::v4i32, 1 }, 2071 { ISD::BSWAP, MVT::v8i16, 1 }, 2072 { ISD::CTLZ, MVT::v2i64, 23 }, 2073 { ISD::CTLZ, MVT::v4i32, 18 }, 2074 { ISD::CTLZ, MVT::v8i16, 14 }, 2075 { ISD::CTLZ, MVT::v16i8, 9 }, 2076 { ISD::CTPOP, MVT::v2i64, 7 }, 2077 { ISD::CTPOP, MVT::v4i32, 11 }, 2078 { ISD::CTPOP, MVT::v8i16, 9 }, 2079 { ISD::CTPOP, MVT::v16i8, 6 }, 2080 { ISD::CTTZ, MVT::v2i64, 10 }, 2081 { ISD::CTTZ, MVT::v4i32, 14 }, 2082 { ISD::CTTZ, MVT::v8i16, 12 }, 2083 { ISD::CTTZ, MVT::v16i8, 9 } 2084 }; 2085 static const CostTblEntry SSE2CostTbl[] = { 2086 { ISD::BITREVERSE, MVT::v2i64, 29 }, 2087 { ISD::BITREVERSE, MVT::v4i32, 27 }, 2088 { ISD::BITREVERSE, MVT::v8i16, 27 }, 2089 { ISD::BITREVERSE, MVT::v16i8, 20 }, 2090 { ISD::BSWAP, MVT::v2i64, 7 }, 2091 { ISD::BSWAP, MVT::v4i32, 7 }, 2092 { ISD::BSWAP, MVT::v8i16, 7 }, 2093 { ISD::CTLZ, MVT::v2i64, 25 }, 2094 { ISD::CTLZ, MVT::v4i32, 26 }, 2095 { ISD::CTLZ, MVT::v8i16, 20 }, 2096 { ISD::CTLZ, MVT::v16i8, 17 }, 2097 { ISD::CTPOP, MVT::v2i64, 12 }, 2098 { ISD::CTPOP, MVT::v4i32, 15 }, 2099 { ISD::CTPOP, MVT::v8i16, 13 }, 2100 { ISD::CTPOP, MVT::v16i8, 10 }, 2101 { ISD::CTTZ, MVT::v2i64, 14 }, 2102 { ISD::CTTZ, MVT::v4i32, 18 }, 2103 { ISD::CTTZ, MVT::v8i16, 16 }, 2104 { ISD::CTTZ, MVT::v16i8, 13 }, 2105 { ISD::SADDSAT, MVT::v8i16, 1 }, 2106 { ISD::SADDSAT, MVT::v16i8, 1 }, 2107 { ISD::SSUBSAT, MVT::v8i16, 1 }, 2108 { ISD::SSUBSAT, MVT::v16i8, 1 }, 2109 { ISD::UADDSAT, MVT::v8i16, 1 }, 2110 { ISD::UADDSAT, MVT::v16i8, 1 }, 2111 { ISD::USUBSAT, MVT::v8i16, 1 }, 2112 { ISD::USUBSAT, MVT::v16i8, 1 }, 2113 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 2114 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 2115 }; 2116 static const CostTblEntry SSE1CostTbl[] = { 2117 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 2118 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 2119 }; 2120 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2121 { ISD::BITREVERSE, MVT::i64, 14 }, 2122 { ISD::SADDO, MVT::i64, 1 }, 2123 { ISD::UADDO, MVT::i64, 1 }, 2124 }; 2125 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2126 { ISD::BITREVERSE, MVT::i32, 14 }, 2127 { ISD::BITREVERSE, MVT::i16, 14 }, 2128 { ISD::BITREVERSE, MVT::i8, 11 }, 2129 { ISD::SADDO, MVT::i32, 1 }, 2130 { ISD::SADDO, MVT::i16, 1 }, 2131 { ISD::SADDO, MVT::i8, 1 }, 2132 { ISD::UADDO, MVT::i32, 1 }, 2133 { ISD::UADDO, MVT::i16, 1 }, 2134 { ISD::UADDO, MVT::i8, 1 }, 2135 }; 2136 2137 Type *OpTy = RetTy; 2138 unsigned ISD = ISD::DELETED_NODE; 2139 switch (IID) { 2140 default: 2141 break; 2142 case Intrinsic::bitreverse: 2143 ISD = ISD::BITREVERSE; 2144 break; 2145 case Intrinsic::bswap: 2146 ISD = ISD::BSWAP; 2147 break; 2148 case Intrinsic::ctlz: 2149 ISD = ISD::CTLZ; 2150 break; 2151 case Intrinsic::ctpop: 2152 ISD = ISD::CTPOP; 2153 break; 2154 case Intrinsic::cttz: 2155 ISD = ISD::CTTZ; 2156 break; 2157 case Intrinsic::sadd_sat: 2158 ISD = ISD::SADDSAT; 2159 break; 2160 case Intrinsic::ssub_sat: 2161 ISD = ISD::SSUBSAT; 2162 break; 2163 case Intrinsic::uadd_sat: 2164 ISD = ISD::UADDSAT; 2165 break; 2166 case Intrinsic::usub_sat: 2167 ISD = ISD::USUBSAT; 2168 break; 2169 case Intrinsic::sqrt: 2170 ISD = ISD::FSQRT; 2171 break; 2172 case Intrinsic::sadd_with_overflow: 2173 case Intrinsic::ssub_with_overflow: 2174 // SSUBO has same costs so don't duplicate. 2175 ISD = ISD::SADDO; 2176 OpTy = RetTy->getContainedType(0); 2177 break; 2178 case Intrinsic::uadd_with_overflow: 2179 case Intrinsic::usub_with_overflow: 2180 // USUBO has same costs so don't duplicate. 2181 ISD = ISD::UADDO; 2182 OpTy = RetTy->getContainedType(0); 2183 break; 2184 } 2185 2186 if (ISD != ISD::DELETED_NODE) { 2187 // Legalize the type. 2188 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 2189 MVT MTy = LT.second; 2190 2191 // Attempt to lookup cost. 2192 if (ST->isGLM()) 2193 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 2194 return LT.first * Entry->Cost; 2195 2196 if (ST->isSLM()) 2197 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2198 return LT.first * Entry->Cost; 2199 2200 if (ST->hasCDI()) 2201 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 2202 return LT.first * Entry->Cost; 2203 2204 if (ST->hasBWI()) 2205 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2206 return LT.first * Entry->Cost; 2207 2208 if (ST->hasAVX512()) 2209 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2210 return LT.first * Entry->Cost; 2211 2212 if (ST->hasXOP()) 2213 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2214 return LT.first * Entry->Cost; 2215 2216 if (ST->hasAVX2()) 2217 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2218 return LT.first * Entry->Cost; 2219 2220 if (ST->hasAVX()) 2221 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2222 return LT.first * Entry->Cost; 2223 2224 if (ST->hasSSE42()) 2225 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2226 return LT.first * Entry->Cost; 2227 2228 if (ST->hasSSSE3()) 2229 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 2230 return LT.first * Entry->Cost; 2231 2232 if (ST->hasSSE2()) 2233 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2234 return LT.first * Entry->Cost; 2235 2236 if (ST->hasSSE1()) 2237 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2238 return LT.first * Entry->Cost; 2239 2240 if (ST->is64Bit()) 2241 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2242 return LT.first * Entry->Cost; 2243 2244 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2245 return LT.first * Entry->Cost; 2246 } 2247 2248 return BaseT::getIntrinsicInstrCost(IID, RetTy, Tys, FMF, ScalarizationCostPassed); 2249 } 2250 2251 int X86TTIImpl::getIntrinsicInstrCost(Intrinsic::ID IID, Type *RetTy, 2252 ArrayRef<Value *> Args, FastMathFlags FMF, 2253 unsigned VF) { 2254 static const CostTblEntry AVX512CostTbl[] = { 2255 { ISD::ROTL, MVT::v8i64, 1 }, 2256 { ISD::ROTL, MVT::v4i64, 1 }, 2257 { ISD::ROTL, MVT::v2i64, 1 }, 2258 { ISD::ROTL, MVT::v16i32, 1 }, 2259 { ISD::ROTL, MVT::v8i32, 1 }, 2260 { ISD::ROTL, MVT::v4i32, 1 }, 2261 { ISD::ROTR, MVT::v8i64, 1 }, 2262 { ISD::ROTR, MVT::v4i64, 1 }, 2263 { ISD::ROTR, MVT::v2i64, 1 }, 2264 { ISD::ROTR, MVT::v16i32, 1 }, 2265 { ISD::ROTR, MVT::v8i32, 1 }, 2266 { ISD::ROTR, MVT::v4i32, 1 } 2267 }; 2268 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 2269 static const CostTblEntry XOPCostTbl[] = { 2270 { ISD::ROTL, MVT::v4i64, 4 }, 2271 { ISD::ROTL, MVT::v8i32, 4 }, 2272 { ISD::ROTL, MVT::v16i16, 4 }, 2273 { ISD::ROTL, MVT::v32i8, 4 }, 2274 { ISD::ROTL, MVT::v2i64, 1 }, 2275 { ISD::ROTL, MVT::v4i32, 1 }, 2276 { ISD::ROTL, MVT::v8i16, 1 }, 2277 { ISD::ROTL, MVT::v16i8, 1 }, 2278 { ISD::ROTR, MVT::v4i64, 6 }, 2279 { ISD::ROTR, MVT::v8i32, 6 }, 2280 { ISD::ROTR, MVT::v16i16, 6 }, 2281 { ISD::ROTR, MVT::v32i8, 6 }, 2282 { ISD::ROTR, MVT::v2i64, 2 }, 2283 { ISD::ROTR, MVT::v4i32, 2 }, 2284 { ISD::ROTR, MVT::v8i16, 2 }, 2285 { ISD::ROTR, MVT::v16i8, 2 } 2286 }; 2287 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 2288 { ISD::ROTL, MVT::i64, 1 }, 2289 { ISD::ROTR, MVT::i64, 1 }, 2290 { ISD::FSHL, MVT::i64, 4 } 2291 }; 2292 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 2293 { ISD::ROTL, MVT::i32, 1 }, 2294 { ISD::ROTL, MVT::i16, 1 }, 2295 { ISD::ROTL, MVT::i8, 1 }, 2296 { ISD::ROTR, MVT::i32, 1 }, 2297 { ISD::ROTR, MVT::i16, 1 }, 2298 { ISD::ROTR, MVT::i8, 1 }, 2299 { ISD::FSHL, MVT::i32, 4 }, 2300 { ISD::FSHL, MVT::i16, 4 }, 2301 { ISD::FSHL, MVT::i8, 4 } 2302 }; 2303 2304 unsigned ISD = ISD::DELETED_NODE; 2305 switch (IID) { 2306 default: 2307 break; 2308 case Intrinsic::fshl: 2309 ISD = ISD::FSHL; 2310 if (Args[0] == Args[1]) 2311 ISD = ISD::ROTL; 2312 break; 2313 case Intrinsic::fshr: 2314 // FSHR has same costs so don't duplicate. 2315 ISD = ISD::FSHL; 2316 if (Args[0] == Args[1]) 2317 ISD = ISD::ROTR; 2318 break; 2319 } 2320 2321 if (ISD != ISD::DELETED_NODE) { 2322 // Legalize the type. 2323 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, RetTy); 2324 MVT MTy = LT.second; 2325 2326 // Attempt to lookup cost. 2327 if (ST->hasAVX512()) 2328 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2329 return LT.first * Entry->Cost; 2330 2331 if (ST->hasXOP()) 2332 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 2333 return LT.first * Entry->Cost; 2334 2335 if (ST->is64Bit()) 2336 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 2337 return LT.first * Entry->Cost; 2338 2339 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 2340 return LT.first * Entry->Cost; 2341 } 2342 2343 return BaseT::getIntrinsicInstrCost(IID, RetTy, Args, FMF, VF); 2344 } 2345 2346 int X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { 2347 assert(Val->isVectorTy() && "This must be a vector type"); 2348 2349 Type *ScalarType = Val->getScalarType(); 2350 2351 if (Index != -1U) { 2352 // Legalize the type. 2353 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 2354 2355 // This type is legalized to a scalar type. 2356 if (!LT.second.isVector()) 2357 return 0; 2358 2359 // The type may be split. Normalize the index to the new type. 2360 unsigned Width = LT.second.getVectorNumElements(); 2361 Index = Index % Width; 2362 2363 // Floating point scalars are already located in index #0. 2364 if (ScalarType->isFloatingPointTy() && Index == 0) 2365 return 0; 2366 } 2367 2368 // Add to the base cost if we know that the extracted element of a vector is 2369 // destined to be moved to and used in the integer register file. 2370 int RegisterFileMoveCost = 0; 2371 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 2372 RegisterFileMoveCost = 1; 2373 2374 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 2375 } 2376 2377 int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 2378 unsigned AddressSpace, const Instruction *I) { 2379 // Handle non-power-of-two vectors such as <3 x float> 2380 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 2381 unsigned NumElem = VTy->getVectorNumElements(); 2382 2383 // Handle a few common cases: 2384 // <3 x float> 2385 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 2386 // Cost = 64 bit store + extract + 32 bit store. 2387 return 3; 2388 2389 // <3 x double> 2390 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 2391 // Cost = 128 bit store + unpack + 64 bit store. 2392 return 3; 2393 2394 // Assume that all other non-power-of-two numbers are scalarized. 2395 if (!isPowerOf2_32(NumElem)) { 2396 int Cost = BaseT::getMemoryOpCost(Opcode, VTy->getScalarType(), Alignment, 2397 AddressSpace); 2398 int SplitCost = getScalarizationOverhead(Src, Opcode == Instruction::Load, 2399 Opcode == Instruction::Store); 2400 return NumElem * Cost + SplitCost; 2401 } 2402 } 2403 2404 // Legalize the type. 2405 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 2406 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 2407 "Invalid Opcode"); 2408 2409 // Each load/store unit costs 1. 2410 int Cost = LT.first * 1; 2411 2412 // This isn't exactly right. We're using slow unaligned 32-byte accesses as a 2413 // proxy for a double-pumped AVX memory interface such as on Sandybridge. 2414 if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow()) 2415 Cost *= 2; 2416 2417 return Cost; 2418 } 2419 2420 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, 2421 unsigned Alignment, 2422 unsigned AddressSpace) { 2423 bool IsLoad = (Instruction::Load == Opcode); 2424 bool IsStore = (Instruction::Store == Opcode); 2425 2426 VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy); 2427 if (!SrcVTy) 2428 // To calculate scalar take the regular cost, without mask 2429 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace); 2430 2431 unsigned NumElem = SrcVTy->getVectorNumElements(); 2432 VectorType *MaskTy = 2433 VectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 2434 if ((IsLoad && !isLegalMaskedLoad(SrcVTy)) || 2435 (IsStore && !isLegalMaskedStore(SrcVTy)) || !isPowerOf2_32(NumElem)) { 2436 // Scalarization 2437 int MaskSplitCost = getScalarizationOverhead(MaskTy, false, true); 2438 int ScalarCompareCost = getCmpSelInstrCost( 2439 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr); 2440 int BranchCost = getCFInstrCost(Instruction::Br); 2441 int MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 2442 2443 int ValueSplitCost = getScalarizationOverhead(SrcVTy, IsLoad, IsStore); 2444 int MemopCost = 2445 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 2446 Alignment, AddressSpace); 2447 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 2448 } 2449 2450 // Legalize the type. 2451 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 2452 auto VT = TLI->getValueType(DL, SrcVTy); 2453 int Cost = 0; 2454 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 2455 LT.second.getVectorNumElements() == NumElem) 2456 // Promotion requires expand/truncate for data and a shuffle for mask. 2457 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, 0, nullptr) + 2458 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, 0, nullptr); 2459 2460 else if (LT.second.getVectorNumElements() > NumElem) { 2461 VectorType *NewMaskTy = VectorType::get(MaskTy->getVectorElementType(), 2462 LT.second.getVectorNumElements()); 2463 // Expanding requires fill mask with zeroes 2464 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, 0, MaskTy); 2465 } 2466 2467 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 2468 if (!ST->hasAVX512()) 2469 return Cost + LT.first * (IsLoad ? 2 : 8); 2470 2471 // AVX-512 masked load/store is cheapper 2472 return Cost + LT.first; 2473 } 2474 2475 int X86TTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, 2476 const SCEV *Ptr) { 2477 // Address computations in vectorized code with non-consecutive addresses will 2478 // likely result in more instructions compared to scalar code where the 2479 // computation can more often be merged into the index mode. The resulting 2480 // extra micro-ops can significantly decrease throughput. 2481 const unsigned NumVectorInstToHideOverhead = 10; 2482 2483 // Cost modeling of Strided Access Computation is hidden by the indexing 2484 // modes of X86 regardless of the stride value. We dont believe that there 2485 // is a difference between constant strided access in gerenal and constant 2486 // strided value which is less than or equal to 64. 2487 // Even in the case of (loop invariant) stride whose value is not known at 2488 // compile time, the address computation will not incur more than one extra 2489 // ADD instruction. 2490 if (Ty->isVectorTy() && SE) { 2491 if (!BaseT::isStridedAccess(Ptr)) 2492 return NumVectorInstToHideOverhead; 2493 if (!BaseT::getConstantStrideStep(SE, Ptr)) 2494 return 1; 2495 } 2496 2497 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 2498 } 2499 2500 int X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, Type *ValTy, 2501 bool IsPairwise) { 2502 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2503 // and make it as the cost. 2504 2505 static const CostTblEntry SSE42CostTblPairWise[] = { 2506 { ISD::FADD, MVT::v2f64, 2 }, 2507 { ISD::FADD, MVT::v4f32, 4 }, 2508 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2509 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32. 2510 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2511 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16 2512 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16 2513 { ISD::ADD, MVT::v8i16, 5 }, 2514 }; 2515 2516 static const CostTblEntry AVX1CostTblPairWise[] = { 2517 { ISD::FADD, MVT::v4f32, 4 }, 2518 { ISD::FADD, MVT::v4f64, 5 }, 2519 { ISD::FADD, MVT::v8f32, 7 }, 2520 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2521 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2522 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5". 2523 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8". 2524 { ISD::ADD, MVT::v2i16, 3 }, // FIXME: chosen to be less than v4i16 2525 { ISD::ADD, MVT::v4i16, 4 }, // FIXME: chosen to be less than v8i16 2526 { ISD::ADD, MVT::v8i16, 5 }, 2527 { ISD::ADD, MVT::v8i32, 5 }, 2528 }; 2529 2530 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2531 { ISD::FADD, MVT::v2f64, 2 }, 2532 { ISD::FADD, MVT::v4f32, 4 }, 2533 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 2534 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2535 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 2536 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2537 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2538 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 2539 }; 2540 2541 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2542 { ISD::FADD, MVT::v4f32, 3 }, 2543 { ISD::FADD, MVT::v4f64, 3 }, 2544 { ISD::FADD, MVT::v8f32, 4 }, 2545 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 2546 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 2547 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8". 2548 { ISD::ADD, MVT::v4i64, 3 }, 2549 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 2550 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 2551 { ISD::ADD, MVT::v8i16, 4 }, 2552 { ISD::ADD, MVT::v8i32, 5 }, 2553 }; 2554 2555 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2556 assert(ISD && "Invalid opcode"); 2557 2558 // Before legalizing the type, give a chance to look up illegal narrow types 2559 // in the table. 2560 // FIXME: Is there a better way to do this? 2561 EVT VT = TLI->getValueType(DL, ValTy); 2562 if (VT.isSimple() && ExperimentalVectorWideningLegalization) { 2563 MVT MTy = VT.getSimpleVT(); 2564 if (IsPairwise) { 2565 if (ST->hasAVX()) 2566 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2567 return Entry->Cost; 2568 2569 if (ST->hasSSE42()) 2570 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2571 return Entry->Cost; 2572 } else { 2573 if (ST->hasAVX()) 2574 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2575 return Entry->Cost; 2576 2577 if (ST->hasSSE42()) 2578 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2579 return Entry->Cost; 2580 } 2581 } 2582 2583 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2584 2585 MVT MTy = LT.second; 2586 2587 if (IsPairwise) { 2588 if (ST->hasAVX()) 2589 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2590 return LT.first * Entry->Cost; 2591 2592 if (ST->hasSSE42()) 2593 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2594 return LT.first * Entry->Cost; 2595 } else { 2596 if (ST->hasAVX()) 2597 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2598 return LT.first * Entry->Cost; 2599 2600 if (ST->hasSSE42()) 2601 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2602 return LT.first * Entry->Cost; 2603 } 2604 2605 static const CostTblEntry AVX2BoolReduction[] = { 2606 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 2607 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 2608 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 2609 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 2610 }; 2611 2612 static const CostTblEntry AVX1BoolReduction[] = { 2613 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 2614 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 2615 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2616 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 2617 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 2618 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 2619 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2620 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 2621 }; 2622 2623 static const CostTblEntry SSE2BoolReduction[] = { 2624 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 2625 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 2626 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 2627 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 2628 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 2629 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 2630 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 2631 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 2632 }; 2633 2634 // Handle bool allof/anyof patterns. 2635 if (ValTy->getVectorElementType()->isIntegerTy(1)) { 2636 if (ST->hasAVX2()) 2637 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 2638 return LT.first * Entry->Cost; 2639 if (ST->hasAVX()) 2640 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 2641 return LT.first * Entry->Cost; 2642 if (ST->hasSSE2()) 2643 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 2644 return LT.first * Entry->Cost; 2645 } 2646 2647 return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwise); 2648 } 2649 2650 int X86TTIImpl::getMinMaxReductionCost(Type *ValTy, Type *CondTy, 2651 bool IsPairwise, bool IsUnsigned) { 2652 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2653 2654 MVT MTy = LT.second; 2655 2656 int ISD; 2657 if (ValTy->isIntOrIntVectorTy()) { 2658 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 2659 } else { 2660 assert(ValTy->isFPOrFPVectorTy() && 2661 "Expected float point or integer vector type."); 2662 ISD = ISD::FMINNUM; 2663 } 2664 2665 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 2666 // and make it as the cost. 2667 2668 static const CostTblEntry SSE1CostTblPairWise[] = { 2669 {ISD::FMINNUM, MVT::v4f32, 4}, 2670 }; 2671 2672 static const CostTblEntry SSE2CostTblPairWise[] = { 2673 {ISD::FMINNUM, MVT::v2f64, 3}, 2674 {ISD::SMIN, MVT::v2i64, 6}, 2675 {ISD::UMIN, MVT::v2i64, 8}, 2676 {ISD::SMIN, MVT::v4i32, 6}, 2677 {ISD::UMIN, MVT::v4i32, 8}, 2678 {ISD::SMIN, MVT::v8i16, 4}, 2679 {ISD::UMIN, MVT::v8i16, 6}, 2680 {ISD::SMIN, MVT::v16i8, 8}, 2681 {ISD::UMIN, MVT::v16i8, 6}, 2682 }; 2683 2684 static const CostTblEntry SSE41CostTblPairWise[] = { 2685 {ISD::FMINNUM, MVT::v4f32, 2}, 2686 {ISD::SMIN, MVT::v2i64, 9}, 2687 {ISD::UMIN, MVT::v2i64,10}, 2688 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2689 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2690 {ISD::SMIN, MVT::v8i16, 2}, 2691 {ISD::UMIN, MVT::v8i16, 2}, 2692 {ISD::SMIN, MVT::v16i8, 3}, 2693 {ISD::UMIN, MVT::v16i8, 3}, 2694 }; 2695 2696 static const CostTblEntry SSE42CostTblPairWise[] = { 2697 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2698 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" 2699 }; 2700 2701 static const CostTblEntry AVX1CostTblPairWise[] = { 2702 {ISD::FMINNUM, MVT::v4f32, 1}, 2703 {ISD::FMINNUM, MVT::v4f64, 1}, 2704 {ISD::FMINNUM, MVT::v8f32, 2}, 2705 {ISD::SMIN, MVT::v2i64, 3}, 2706 {ISD::UMIN, MVT::v2i64, 3}, 2707 {ISD::SMIN, MVT::v4i32, 1}, 2708 {ISD::UMIN, MVT::v4i32, 1}, 2709 {ISD::SMIN, MVT::v8i16, 1}, 2710 {ISD::UMIN, MVT::v8i16, 1}, 2711 {ISD::SMIN, MVT::v16i8, 2}, 2712 {ISD::UMIN, MVT::v16i8, 2}, 2713 {ISD::SMIN, MVT::v4i64, 7}, 2714 {ISD::UMIN, MVT::v4i64, 7}, 2715 {ISD::SMIN, MVT::v8i32, 3}, 2716 {ISD::UMIN, MVT::v8i32, 3}, 2717 {ISD::SMIN, MVT::v16i16, 3}, 2718 {ISD::UMIN, MVT::v16i16, 3}, 2719 {ISD::SMIN, MVT::v32i8, 3}, 2720 {ISD::UMIN, MVT::v32i8, 3}, 2721 }; 2722 2723 static const CostTblEntry AVX2CostTblPairWise[] = { 2724 {ISD::SMIN, MVT::v4i64, 2}, 2725 {ISD::UMIN, MVT::v4i64, 2}, 2726 {ISD::SMIN, MVT::v8i32, 1}, 2727 {ISD::UMIN, MVT::v8i32, 1}, 2728 {ISD::SMIN, MVT::v16i16, 1}, 2729 {ISD::UMIN, MVT::v16i16, 1}, 2730 {ISD::SMIN, MVT::v32i8, 2}, 2731 {ISD::UMIN, MVT::v32i8, 2}, 2732 }; 2733 2734 static const CostTblEntry AVX512CostTblPairWise[] = { 2735 {ISD::FMINNUM, MVT::v8f64, 1}, 2736 {ISD::FMINNUM, MVT::v16f32, 2}, 2737 {ISD::SMIN, MVT::v8i64, 2}, 2738 {ISD::UMIN, MVT::v8i64, 2}, 2739 {ISD::SMIN, MVT::v16i32, 1}, 2740 {ISD::UMIN, MVT::v16i32, 1}, 2741 }; 2742 2743 static const CostTblEntry SSE1CostTblNoPairWise[] = { 2744 {ISD::FMINNUM, MVT::v4f32, 4}, 2745 }; 2746 2747 static const CostTblEntry SSE2CostTblNoPairWise[] = { 2748 {ISD::FMINNUM, MVT::v2f64, 3}, 2749 {ISD::SMIN, MVT::v2i64, 6}, 2750 {ISD::UMIN, MVT::v2i64, 8}, 2751 {ISD::SMIN, MVT::v4i32, 6}, 2752 {ISD::UMIN, MVT::v4i32, 8}, 2753 {ISD::SMIN, MVT::v8i16, 4}, 2754 {ISD::UMIN, MVT::v8i16, 6}, 2755 {ISD::SMIN, MVT::v16i8, 8}, 2756 {ISD::UMIN, MVT::v16i8, 6}, 2757 }; 2758 2759 static const CostTblEntry SSE41CostTblNoPairWise[] = { 2760 {ISD::FMINNUM, MVT::v4f32, 3}, 2761 {ISD::SMIN, MVT::v2i64, 9}, 2762 {ISD::UMIN, MVT::v2i64,11}, 2763 {ISD::SMIN, MVT::v4i32, 1}, // The data reported by the IACA is "1.5" 2764 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" 2765 {ISD::SMIN, MVT::v8i16, 1}, // The data reported by the IACA is "1.5" 2766 {ISD::UMIN, MVT::v8i16, 2}, // The data reported by the IACA is "1.8" 2767 {ISD::SMIN, MVT::v16i8, 3}, 2768 {ISD::UMIN, MVT::v16i8, 3}, 2769 }; 2770 2771 static const CostTblEntry SSE42CostTblNoPairWise[] = { 2772 {ISD::SMIN, MVT::v2i64, 7}, // The data reported by the IACA is "6.8" 2773 {ISD::UMIN, MVT::v2i64, 9}, // The data reported by the IACA is "8.6" 2774 }; 2775 2776 static const CostTblEntry AVX1CostTblNoPairWise[] = { 2777 {ISD::FMINNUM, MVT::v4f32, 1}, 2778 {ISD::FMINNUM, MVT::v4f64, 1}, 2779 {ISD::FMINNUM, MVT::v8f32, 1}, 2780 {ISD::SMIN, MVT::v2i64, 3}, 2781 {ISD::UMIN, MVT::v2i64, 3}, 2782 {ISD::SMIN, MVT::v4i32, 1}, 2783 {ISD::UMIN, MVT::v4i32, 1}, 2784 {ISD::SMIN, MVT::v8i16, 1}, 2785 {ISD::UMIN, MVT::v8i16, 1}, 2786 {ISD::SMIN, MVT::v16i8, 2}, 2787 {ISD::UMIN, MVT::v16i8, 2}, 2788 {ISD::SMIN, MVT::v4i64, 7}, 2789 {ISD::UMIN, MVT::v4i64, 7}, 2790 {ISD::SMIN, MVT::v8i32, 2}, 2791 {ISD::UMIN, MVT::v8i32, 2}, 2792 {ISD::SMIN, MVT::v16i16, 2}, 2793 {ISD::UMIN, MVT::v16i16, 2}, 2794 {ISD::SMIN, MVT::v32i8, 2}, 2795 {ISD::UMIN, MVT::v32i8, 2}, 2796 }; 2797 2798 static const CostTblEntry AVX2CostTblNoPairWise[] = { 2799 {ISD::SMIN, MVT::v4i64, 1}, 2800 {ISD::UMIN, MVT::v4i64, 1}, 2801 {ISD::SMIN, MVT::v8i32, 1}, 2802 {ISD::UMIN, MVT::v8i32, 1}, 2803 {ISD::SMIN, MVT::v16i16, 1}, 2804 {ISD::UMIN, MVT::v16i16, 1}, 2805 {ISD::SMIN, MVT::v32i8, 1}, 2806 {ISD::UMIN, MVT::v32i8, 1}, 2807 }; 2808 2809 static const CostTblEntry AVX512CostTblNoPairWise[] = { 2810 {ISD::FMINNUM, MVT::v8f64, 1}, 2811 {ISD::FMINNUM, MVT::v16f32, 2}, 2812 {ISD::SMIN, MVT::v8i64, 1}, 2813 {ISD::UMIN, MVT::v8i64, 1}, 2814 {ISD::SMIN, MVT::v16i32, 1}, 2815 {ISD::UMIN, MVT::v16i32, 1}, 2816 }; 2817 2818 if (IsPairwise) { 2819 if (ST->hasAVX512()) 2820 if (const auto *Entry = CostTableLookup(AVX512CostTblPairWise, ISD, MTy)) 2821 return LT.first * Entry->Cost; 2822 2823 if (ST->hasAVX2()) 2824 if (const auto *Entry = CostTableLookup(AVX2CostTblPairWise, ISD, MTy)) 2825 return LT.first * Entry->Cost; 2826 2827 if (ST->hasAVX()) 2828 if (const auto *Entry = CostTableLookup(AVX1CostTblPairWise, ISD, MTy)) 2829 return LT.first * Entry->Cost; 2830 2831 if (ST->hasSSE42()) 2832 if (const auto *Entry = CostTableLookup(SSE42CostTblPairWise, ISD, MTy)) 2833 return LT.first * Entry->Cost; 2834 2835 if (ST->hasSSE41()) 2836 if (const auto *Entry = CostTableLookup(SSE41CostTblPairWise, ISD, MTy)) 2837 return LT.first * Entry->Cost; 2838 2839 if (ST->hasSSE2()) 2840 if (const auto *Entry = CostTableLookup(SSE2CostTblPairWise, ISD, MTy)) 2841 return LT.first * Entry->Cost; 2842 2843 if (ST->hasSSE1()) 2844 if (const auto *Entry = CostTableLookup(SSE1CostTblPairWise, ISD, MTy)) 2845 return LT.first * Entry->Cost; 2846 } else { 2847 if (ST->hasAVX512()) 2848 if (const auto *Entry = 2849 CostTableLookup(AVX512CostTblNoPairWise, ISD, MTy)) 2850 return LT.first * Entry->Cost; 2851 2852 if (ST->hasAVX2()) 2853 if (const auto *Entry = CostTableLookup(AVX2CostTblNoPairWise, ISD, MTy)) 2854 return LT.first * Entry->Cost; 2855 2856 if (ST->hasAVX()) 2857 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 2858 return LT.first * Entry->Cost; 2859 2860 if (ST->hasSSE42()) 2861 if (const auto *Entry = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy)) 2862 return LT.first * Entry->Cost; 2863 2864 if (ST->hasSSE41()) 2865 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 2866 return LT.first * Entry->Cost; 2867 2868 if (ST->hasSSE2()) 2869 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 2870 return LT.first * Entry->Cost; 2871 2872 if (ST->hasSSE1()) 2873 if (const auto *Entry = CostTableLookup(SSE1CostTblNoPairWise, ISD, MTy)) 2874 return LT.first * Entry->Cost; 2875 } 2876 2877 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsPairwise, IsUnsigned); 2878 } 2879 2880 /// Calculate the cost of materializing a 64-bit value. This helper 2881 /// method might only calculate a fraction of a larger immediate. Therefore it 2882 /// is valid to return a cost of ZERO. 2883 int X86TTIImpl::getIntImmCost(int64_t Val) { 2884 if (Val == 0) 2885 return TTI::TCC_Free; 2886 2887 if (isInt<32>(Val)) 2888 return TTI::TCC_Basic; 2889 2890 return 2 * TTI::TCC_Basic; 2891 } 2892 2893 int X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { 2894 assert(Ty->isIntegerTy()); 2895 2896 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2897 if (BitSize == 0) 2898 return ~0U; 2899 2900 // Never hoist constants larger than 128bit, because this might lead to 2901 // incorrect code generation or assertions in codegen. 2902 // Fixme: Create a cost model for types larger than i128 once the codegen 2903 // issues have been fixed. 2904 if (BitSize > 128) 2905 return TTI::TCC_Free; 2906 2907 if (Imm == 0) 2908 return TTI::TCC_Free; 2909 2910 // Sign-extend all constants to a multiple of 64-bit. 2911 APInt ImmVal = Imm; 2912 if (BitSize % 64 != 0) 2913 ImmVal = Imm.sext(alignTo(BitSize, 64)); 2914 2915 // Split the constant into 64-bit chunks and calculate the cost for each 2916 // chunk. 2917 int Cost = 0; 2918 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 2919 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 2920 int64_t Val = Tmp.getSExtValue(); 2921 Cost += getIntImmCost(Val); 2922 } 2923 // We need at least one instruction to materialize the constant. 2924 return std::max(1, Cost); 2925 } 2926 2927 int X86TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, 2928 Type *Ty) { 2929 assert(Ty->isIntegerTy()); 2930 2931 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 2932 // There is no cost model for constants with a bit size of 0. Return TCC_Free 2933 // here, so that constant hoisting will ignore this constant. 2934 if (BitSize == 0) 2935 return TTI::TCC_Free; 2936 2937 unsigned ImmIdx = ~0U; 2938 switch (Opcode) { 2939 default: 2940 return TTI::TCC_Free; 2941 case Instruction::GetElementPtr: 2942 // Always hoist the base address of a GetElementPtr. This prevents the 2943 // creation of new constants for every base constant that gets constant 2944 // folded with the offset. 2945 if (Idx == 0) 2946 return 2 * TTI::TCC_Basic; 2947 return TTI::TCC_Free; 2948 case Instruction::Store: 2949 ImmIdx = 0; 2950 break; 2951 case Instruction::ICmp: 2952 // This is an imperfect hack to prevent constant hoisting of 2953 // compares that might be trying to check if a 64-bit value fits in 2954 // 32-bits. The backend can optimize these cases using a right shift by 32. 2955 // Ideally we would check the compare predicate here. There also other 2956 // similar immediates the backend can use shifts for. 2957 if (Idx == 1 && Imm.getBitWidth() == 64) { 2958 uint64_t ImmVal = Imm.getZExtValue(); 2959 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 2960 return TTI::TCC_Free; 2961 } 2962 ImmIdx = 1; 2963 break; 2964 case Instruction::And: 2965 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 2966 // by using a 32-bit operation with implicit zero extension. Detect such 2967 // immediates here as the normal path expects bit 31 to be sign extended. 2968 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 2969 return TTI::TCC_Free; 2970 ImmIdx = 1; 2971 break; 2972 case Instruction::Add: 2973 case Instruction::Sub: 2974 // For add/sub, we can use the opposite instruction for INT32_MIN. 2975 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 2976 return TTI::TCC_Free; 2977 ImmIdx = 1; 2978 break; 2979 case Instruction::UDiv: 2980 case Instruction::SDiv: 2981 case Instruction::URem: 2982 case Instruction::SRem: 2983 // Division by constant is typically expanded later into a different 2984 // instruction sequence. This completely changes the constants. 2985 // Report them as "free" to stop ConstantHoist from marking them as opaque. 2986 return TTI::TCC_Free; 2987 case Instruction::Mul: 2988 case Instruction::Or: 2989 case Instruction::Xor: 2990 ImmIdx = 1; 2991 break; 2992 // Always return TCC_Free for the shift value of a shift instruction. 2993 case Instruction::Shl: 2994 case Instruction::LShr: 2995 case Instruction::AShr: 2996 if (Idx == 1) 2997 return TTI::TCC_Free; 2998 break; 2999 case Instruction::Trunc: 3000 case Instruction::ZExt: 3001 case Instruction::SExt: 3002 case Instruction::IntToPtr: 3003 case Instruction::PtrToInt: 3004 case Instruction::BitCast: 3005 case Instruction::PHI: 3006 case Instruction::Call: 3007 case Instruction::Select: 3008 case Instruction::Ret: 3009 case Instruction::Load: 3010 break; 3011 } 3012 3013 if (Idx == ImmIdx) { 3014 int NumConstants = divideCeil(BitSize, 64); 3015 int Cost = X86TTIImpl::getIntImmCost(Imm, Ty); 3016 return (Cost <= NumConstants * TTI::TCC_Basic) 3017 ? static_cast<int>(TTI::TCC_Free) 3018 : Cost; 3019 } 3020 3021 return X86TTIImpl::getIntImmCost(Imm, Ty); 3022 } 3023 3024 int X86TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 3025 Type *Ty) { 3026 assert(Ty->isIntegerTy()); 3027 3028 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 3029 // There is no cost model for constants with a bit size of 0. Return TCC_Free 3030 // here, so that constant hoisting will ignore this constant. 3031 if (BitSize == 0) 3032 return TTI::TCC_Free; 3033 3034 switch (IID) { 3035 default: 3036 return TTI::TCC_Free; 3037 case Intrinsic::sadd_with_overflow: 3038 case Intrinsic::uadd_with_overflow: 3039 case Intrinsic::ssub_with_overflow: 3040 case Intrinsic::usub_with_overflow: 3041 case Intrinsic::smul_with_overflow: 3042 case Intrinsic::umul_with_overflow: 3043 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 3044 return TTI::TCC_Free; 3045 break; 3046 case Intrinsic::experimental_stackmap: 3047 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3048 return TTI::TCC_Free; 3049 break; 3050 case Intrinsic::experimental_patchpoint_void: 3051 case Intrinsic::experimental_patchpoint_i64: 3052 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 3053 return TTI::TCC_Free; 3054 break; 3055 } 3056 return X86TTIImpl::getIntImmCost(Imm, Ty); 3057 } 3058 3059 unsigned X86TTIImpl::getUserCost(const User *U, 3060 ArrayRef<const Value *> Operands) { 3061 if (isa<StoreInst>(U)) { 3062 Value *Ptr = U->getOperand(1); 3063 // Store instruction with index and scale costs 2 Uops. 3064 // Check the preceding GEP to identify non-const indices. 3065 if (auto GEP = dyn_cast<GetElementPtrInst>(Ptr)) { 3066 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3067 return TTI::TCC_Basic * 2; 3068 } 3069 return TTI::TCC_Basic; 3070 } 3071 return BaseT::getUserCost(U, Operands); 3072 } 3073 3074 // Return an average cost of Gather / Scatter instruction, maybe improved later 3075 int X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, 3076 unsigned Alignment, unsigned AddressSpace) { 3077 3078 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 3079 unsigned VF = SrcVTy->getVectorNumElements(); 3080 3081 // Try to reduce index size from 64 bit (default for GEP) 3082 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 3083 // operation will use 16 x 64 indices which do not fit in a zmm and needs 3084 // to split. Also check that the base pointer is the same for all lanes, 3085 // and that there's at most one variable index. 3086 auto getIndexSizeInBits = [](Value *Ptr, const DataLayout& DL) { 3087 unsigned IndexSize = DL.getPointerSizeInBits(); 3088 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 3089 if (IndexSize < 64 || !GEP) 3090 return IndexSize; 3091 3092 unsigned NumOfVarIndices = 0; 3093 Value *Ptrs = GEP->getPointerOperand(); 3094 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 3095 return IndexSize; 3096 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 3097 if (isa<Constant>(GEP->getOperand(i))) 3098 continue; 3099 Type *IndxTy = GEP->getOperand(i)->getType(); 3100 if (IndxTy->isVectorTy()) 3101 IndxTy = IndxTy->getVectorElementType(); 3102 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 3103 !isa<SExtInst>(GEP->getOperand(i))) || 3104 ++NumOfVarIndices > 1) 3105 return IndexSize; // 64 3106 } 3107 return (unsigned)32; 3108 }; 3109 3110 3111 // Trying to reduce IndexSize to 32 bits for vector 16. 3112 // By default the IndexSize is equal to pointer size. 3113 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 3114 ? getIndexSizeInBits(Ptr, DL) 3115 : DL.getPointerSizeInBits(); 3116 3117 Type *IndexVTy = VectorType::get(IntegerType::get(SrcVTy->getContext(), 3118 IndexSize), VF); 3119 std::pair<int, MVT> IdxsLT = TLI->getTypeLegalizationCost(DL, IndexVTy); 3120 std::pair<int, MVT> SrcLT = TLI->getTypeLegalizationCost(DL, SrcVTy); 3121 int SplitFactor = std::max(IdxsLT.first, SrcLT.first); 3122 if (SplitFactor > 1) { 3123 // Handle splitting of vector of pointers 3124 Type *SplitSrcTy = VectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 3125 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 3126 AddressSpace); 3127 } 3128 3129 // The gather / scatter cost is given by Intel architects. It is a rough 3130 // number since we are looking at one instruction in a time. 3131 const int GSOverhead = (Opcode == Instruction::Load) 3132 ? ST->getGatherOverhead() 3133 : ST->getScatterOverhead(); 3134 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3135 Alignment, AddressSpace); 3136 } 3137 3138 /// Return the cost of full scalarization of gather / scatter operation. 3139 /// 3140 /// Opcode - Load or Store instruction. 3141 /// SrcVTy - The type of the data vector that should be gathered or scattered. 3142 /// VariableMask - The mask is non-constant at compile time. 3143 /// Alignment - Alignment for one element. 3144 /// AddressSpace - pointer[s] address space. 3145 /// 3146 int X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 3147 bool VariableMask, unsigned Alignment, 3148 unsigned AddressSpace) { 3149 unsigned VF = SrcVTy->getVectorNumElements(); 3150 3151 int MaskUnpackCost = 0; 3152 if (VariableMask) { 3153 VectorType *MaskTy = 3154 VectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 3155 MaskUnpackCost = getScalarizationOverhead(MaskTy, false, true); 3156 int ScalarCompareCost = 3157 getCmpSelInstrCost(Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), 3158 nullptr); 3159 int BranchCost = getCFInstrCost(Instruction::Br); 3160 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 3161 } 3162 3163 // The cost of the scalar loads/stores. 3164 int MemoryOpCost = VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 3165 Alignment, AddressSpace); 3166 3167 int InsertExtractCost = 0; 3168 if (Opcode == Instruction::Load) 3169 for (unsigned i = 0; i < VF; ++i) 3170 // Add the cost of inserting each scalar load into the vector 3171 InsertExtractCost += 3172 getVectorInstrCost(Instruction::InsertElement, SrcVTy, i); 3173 else 3174 for (unsigned i = 0; i < VF; ++i) 3175 // Add the cost of extracting each element out of the data vector 3176 InsertExtractCost += 3177 getVectorInstrCost(Instruction::ExtractElement, SrcVTy, i); 3178 3179 return MemoryOpCost + MaskUnpackCost + InsertExtractCost; 3180 } 3181 3182 /// Calculate the cost of Gather / Scatter operation 3183 int X86TTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, 3184 Value *Ptr, bool VariableMask, 3185 unsigned Alignment) { 3186 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 3187 unsigned VF = SrcVTy->getVectorNumElements(); 3188 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 3189 if (!PtrTy && Ptr->getType()->isVectorTy()) 3190 PtrTy = dyn_cast<PointerType>(Ptr->getType()->getVectorElementType()); 3191 assert(PtrTy && "Unexpected type for Ptr argument"); 3192 unsigned AddressSpace = PtrTy->getAddressSpace(); 3193 3194 bool Scalarize = false; 3195 if ((Opcode == Instruction::Load && !isLegalMaskedGather(SrcVTy)) || 3196 (Opcode == Instruction::Store && !isLegalMaskedScatter(SrcVTy))) 3197 Scalarize = true; 3198 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 3199 // Vector-4 of gather/scatter instruction does not exist on KNL. 3200 // We can extend it to 8 elements, but zeroing upper bits of 3201 // the mask vector will add more instructions. Right now we give the scalar 3202 // cost of vector-4 for KNL. TODO: Check, maybe the gather/scatter instruction 3203 // is better in the VariableMask case. 3204 if (ST->hasAVX512() && (VF == 2 || (VF == 4 && !ST->hasVLX()))) 3205 Scalarize = true; 3206 3207 if (Scalarize) 3208 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 3209 AddressSpace); 3210 3211 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 3212 } 3213 3214 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 3215 TargetTransformInfo::LSRCost &C2) { 3216 // X86 specific here are "instruction number 1st priority". 3217 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 3218 C1.NumIVMuls, C1.NumBaseAdds, 3219 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 3220 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 3221 C2.NumIVMuls, C2.NumBaseAdds, 3222 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 3223 } 3224 3225 bool X86TTIImpl::canMacroFuseCmp() { 3226 return ST->hasMacroFusion() || ST->hasBranchFusion(); 3227 } 3228 3229 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy) { 3230 if (!ST->hasAVX()) 3231 return false; 3232 3233 // The backend can't handle a single element vector. 3234 if (isa<VectorType>(DataTy) && DataTy->getVectorNumElements() == 1) 3235 return false; 3236 Type *ScalarTy = DataTy->getScalarType(); 3237 3238 if (ScalarTy->isPointerTy()) 3239 return true; 3240 3241 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3242 return true; 3243 3244 if (!ScalarTy->isIntegerTy()) 3245 return false; 3246 3247 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3248 return IntWidth == 32 || IntWidth == 64 || 3249 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 3250 } 3251 3252 bool X86TTIImpl::isLegalMaskedStore(Type *DataType) { 3253 return isLegalMaskedLoad(DataType); 3254 } 3255 3256 bool X86TTIImpl::isLegalNTLoad(Type *DataType, unsigned Alignment) { 3257 unsigned DataSize = DL.getTypeStoreSize(DataType); 3258 // The only supported nontemporal loads are for aligned vectors of 16 or 32 3259 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 3260 // (the equivalent stores only require AVX). 3261 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 3262 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 3263 3264 return false; 3265 } 3266 3267 bool X86TTIImpl::isLegalNTStore(Type *DataType, unsigned Alignment) { 3268 unsigned DataSize = DL.getTypeStoreSize(DataType); 3269 3270 // SSE4A supports nontemporal stores of float and double at arbitrary 3271 // alignment. 3272 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 3273 return true; 3274 3275 // Besides the SSE4A subtarget exception above, only aligned stores are 3276 // available nontemporaly on any other subtarget. And only stores with a size 3277 // of 4..32 bytes (powers of 2, only) are permitted. 3278 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 3279 !isPowerOf2_32(DataSize)) 3280 return false; 3281 3282 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 3283 // loads require AVX2). 3284 if (DataSize == 32) 3285 return ST->hasAVX(); 3286 else if (DataSize == 16) 3287 return ST->hasSSE1(); 3288 return true; 3289 } 3290 3291 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 3292 if (!isa<VectorType>(DataTy)) 3293 return false; 3294 3295 if (!ST->hasAVX512()) 3296 return false; 3297 3298 // The backend can't handle a single element vector. 3299 if (DataTy->getVectorNumElements() == 1) 3300 return false; 3301 3302 Type *ScalarTy = DataTy->getVectorElementType(); 3303 3304 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3305 return true; 3306 3307 if (!ScalarTy->isIntegerTy()) 3308 return false; 3309 3310 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3311 return IntWidth == 32 || IntWidth == 64 || 3312 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 3313 } 3314 3315 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 3316 return isLegalMaskedExpandLoad(DataTy); 3317 } 3318 3319 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy) { 3320 // Some CPUs have better gather performance than others. 3321 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 3322 // enable gather with a -march. 3323 if (!(ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()))) 3324 return false; 3325 3326 // This function is called now in two cases: from the Loop Vectorizer 3327 // and from the Scalarizer. 3328 // When the Loop Vectorizer asks about legality of the feature, 3329 // the vectorization factor is not calculated yet. The Loop Vectorizer 3330 // sends a scalar type and the decision is based on the width of the 3331 // scalar element. 3332 // Later on, the cost model will estimate usage this intrinsic based on 3333 // the vector type. 3334 // The Scalarizer asks again about legality. It sends a vector type. 3335 // In this case we can reject non-power-of-2 vectors. 3336 // We also reject single element vectors as the type legalizer can't 3337 // scalarize it. 3338 if (isa<VectorType>(DataTy)) { 3339 unsigned NumElts = DataTy->getVectorNumElements(); 3340 if (NumElts == 1 || !isPowerOf2_32(NumElts)) 3341 return false; 3342 } 3343 Type *ScalarTy = DataTy->getScalarType(); 3344 if (ScalarTy->isPointerTy()) 3345 return true; 3346 3347 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 3348 return true; 3349 3350 if (!ScalarTy->isIntegerTy()) 3351 return false; 3352 3353 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 3354 return IntWidth == 32 || IntWidth == 64; 3355 } 3356 3357 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType) { 3358 // AVX2 doesn't support scatter 3359 if (!ST->hasAVX512()) 3360 return false; 3361 return isLegalMaskedGather(DataType); 3362 } 3363 3364 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 3365 EVT VT = TLI->getValueType(DL, DataType); 3366 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 3367 } 3368 3369 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 3370 return false; 3371 } 3372 3373 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 3374 const Function *Callee) const { 3375 const TargetMachine &TM = getTLI()->getTargetMachine(); 3376 3377 // Work this as a subsetting of subtarget features. 3378 const FeatureBitset &CallerBits = 3379 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 3380 const FeatureBitset &CalleeBits = 3381 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 3382 3383 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 3384 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 3385 return (RealCallerBits & RealCalleeBits) == RealCalleeBits; 3386 } 3387 3388 bool X86TTIImpl::areFunctionArgsABICompatible( 3389 const Function *Caller, const Function *Callee, 3390 SmallPtrSetImpl<Argument *> &Args) const { 3391 if (!BaseT::areFunctionArgsABICompatible(Caller, Callee, Args)) 3392 return false; 3393 3394 // If we get here, we know the target features match. If one function 3395 // considers 512-bit vectors legal and the other does not, consider them 3396 // incompatible. 3397 // FIXME Look at the arguments and only consider 512 bit or larger vectors? 3398 const TargetMachine &TM = getTLI()->getTargetMachine(); 3399 3400 return TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 3401 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs(); 3402 } 3403 3404 X86TTIImpl::TTI::MemCmpExpansionOptions 3405 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 3406 TTI::MemCmpExpansionOptions Options; 3407 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 3408 Options.NumLoadsPerBlock = 2; 3409 if (IsZeroCmp) { 3410 // Only enable vector loads for equality comparison. Right now the vector 3411 // version is not as fast for three way compare (see #33329). 3412 // TODO: enable AVX512 when the DAG is ready. 3413 // if (ST->hasAVX512()) Options.LoadSizes.push_back(64); 3414 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 3415 if (PreferredWidth >= 256 && ST->hasAVX2()) Options.LoadSizes.push_back(32); 3416 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 3417 // All GPR and vector loads can be unaligned. SIMD compare requires integer 3418 // vectors (SSE2/AVX2). 3419 Options.AllowOverlappingLoads = true; 3420 } 3421 if (ST->is64Bit()) { 3422 Options.LoadSizes.push_back(8); 3423 } 3424 Options.LoadSizes.push_back(4); 3425 Options.LoadSizes.push_back(2); 3426 Options.LoadSizes.push_back(1); 3427 return Options; 3428 } 3429 3430 bool X86TTIImpl::enableInterleavedAccessVectorization() { 3431 // TODO: We expect this to be beneficial regardless of arch, 3432 // but there are currently some unexplained performance artifacts on Atom. 3433 // As a temporary solution, disable on Atom. 3434 return !(ST->isAtom()); 3435 } 3436 3437 // Get estimation for interleaved load/store operations for AVX2. 3438 // \p Factor is the interleaved-access factor (stride) - number of 3439 // (interleaved) elements in the group. 3440 // \p Indices contains the indices for a strided load: when the 3441 // interleaved load has gaps they indicate which elements are used. 3442 // If Indices is empty (or if the number of indices is equal to the size 3443 // of the interleaved-access as given in \p Factor) the access has no gaps. 3444 // 3445 // As opposed to AVX-512, AVX2 does not have generic shuffles that allow 3446 // computing the cost using a generic formula as a function of generic 3447 // shuffles. We therefore use a lookup table instead, filled according to 3448 // the instruction sequences that codegen currently generates. 3449 int X86TTIImpl::getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, 3450 unsigned Factor, 3451 ArrayRef<unsigned> Indices, 3452 unsigned Alignment, 3453 unsigned AddressSpace, 3454 bool UseMaskForCond, 3455 bool UseMaskForGaps) { 3456 3457 if (UseMaskForCond || UseMaskForGaps) 3458 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3459 Alignment, AddressSpace, 3460 UseMaskForCond, UseMaskForGaps); 3461 3462 // We currently Support only fully-interleaved groups, with no gaps. 3463 // TODO: Support also strided loads (interleaved-groups with gaps). 3464 if (Indices.size() && Indices.size() != Factor) 3465 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3466 Alignment, AddressSpace); 3467 3468 // VecTy for interleave memop is <VF*Factor x Elt>. 3469 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3470 // VecTy = <12 x i32>. 3471 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3472 3473 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 3474 // the VF=2, while v2i128 is an unsupported MVT vector type 3475 // (see MachineValueType.h::getVectorVT()). 3476 if (!LegalVT.isVector()) 3477 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3478 Alignment, AddressSpace); 3479 3480 unsigned VF = VecTy->getVectorNumElements() / Factor; 3481 Type *ScalarTy = VecTy->getVectorElementType(); 3482 3483 // Calculate the number of memory operations (NumOfMemOps), required 3484 // for load/store the VecTy. 3485 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3486 unsigned LegalVTSize = LegalVT.getStoreSize(); 3487 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3488 3489 // Get the cost of one memory operation. 3490 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3491 LegalVT.getVectorNumElements()); 3492 unsigned MemOpCost = 3493 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3494 3495 VectorType *VT = VectorType::get(ScalarTy, VF); 3496 EVT ETy = TLI->getValueType(DL, VT); 3497 if (!ETy.isSimple()) 3498 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3499 Alignment, AddressSpace); 3500 3501 // TODO: Complete for other data-types and strides. 3502 // Each combination of Stride, ElementTy and VF results in a different 3503 // sequence; The cost tables are therefore accessed with: 3504 // Factor (stride) and VectorType=VFxElemType. 3505 // The Cost accounts only for the shuffle sequence; 3506 // The cost of the loads/stores is accounted for separately. 3507 // 3508 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 3509 { 2, MVT::v4i64, 6 }, //(load 8i64 and) deinterleave into 2 x 4i64 3510 { 2, MVT::v4f64, 6 }, //(load 8f64 and) deinterleave into 2 x 4f64 3511 3512 { 3, MVT::v2i8, 10 }, //(load 6i8 and) deinterleave into 3 x 2i8 3513 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8 3514 { 3, MVT::v8i8, 9 }, //(load 24i8 and) deinterleave into 3 x 8i8 3515 { 3, MVT::v16i8, 11}, //(load 48i8 and) deinterleave into 3 x 16i8 3516 { 3, MVT::v32i8, 13}, //(load 96i8 and) deinterleave into 3 x 32i8 3517 { 3, MVT::v8f32, 17 }, //(load 24f32 and)deinterleave into 3 x 8f32 3518 3519 { 4, MVT::v2i8, 12 }, //(load 8i8 and) deinterleave into 4 x 2i8 3520 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8 3521 { 4, MVT::v8i8, 20 }, //(load 32i8 and) deinterleave into 4 x 8i8 3522 { 4, MVT::v16i8, 39 }, //(load 64i8 and) deinterleave into 4 x 16i8 3523 { 4, MVT::v32i8, 80 }, //(load 128i8 and) deinterleave into 4 x 32i8 3524 3525 { 8, MVT::v8f32, 40 } //(load 64f32 and)deinterleave into 8 x 8f32 3526 }; 3527 3528 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 3529 { 2, MVT::v4i64, 6 }, //interleave into 2 x 4i64 into 8i64 (and store) 3530 { 2, MVT::v4f64, 6 }, //interleave into 2 x 4f64 into 8f64 (and store) 3531 3532 { 3, MVT::v2i8, 7 }, //interleave 3 x 2i8 into 6i8 (and store) 3533 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store) 3534 { 3, MVT::v8i8, 11 }, //interleave 3 x 8i8 into 24i8 (and store) 3535 { 3, MVT::v16i8, 11 }, //interleave 3 x 16i8 into 48i8 (and store) 3536 { 3, MVT::v32i8, 13 }, //interleave 3 x 32i8 into 96i8 (and store) 3537 3538 { 4, MVT::v2i8, 12 }, //interleave 4 x 2i8 into 8i8 (and store) 3539 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store) 3540 { 4, MVT::v8i8, 10 }, //interleave 4 x 8i8 into 32i8 (and store) 3541 { 4, MVT::v16i8, 10 }, //interleave 4 x 16i8 into 64i8 (and store) 3542 { 4, MVT::v32i8, 12 } //interleave 4 x 32i8 into 128i8 (and store) 3543 }; 3544 3545 if (Opcode == Instruction::Load) { 3546 if (const auto *Entry = 3547 CostTableLookup(AVX2InterleavedLoadTbl, Factor, ETy.getSimpleVT())) 3548 return NumOfMemOps * MemOpCost + Entry->Cost; 3549 } else { 3550 assert(Opcode == Instruction::Store && 3551 "Expected Store Instruction at this point"); 3552 if (const auto *Entry = 3553 CostTableLookup(AVX2InterleavedStoreTbl, Factor, ETy.getSimpleVT())) 3554 return NumOfMemOps * MemOpCost + Entry->Cost; 3555 } 3556 3557 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3558 Alignment, AddressSpace); 3559 } 3560 3561 // Get estimation for interleaved load/store operations and strided load. 3562 // \p Indices contains indices for strided load. 3563 // \p Factor - the factor of interleaving. 3564 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 3565 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, 3566 unsigned Factor, 3567 ArrayRef<unsigned> Indices, 3568 unsigned Alignment, 3569 unsigned AddressSpace, 3570 bool UseMaskForCond, 3571 bool UseMaskForGaps) { 3572 3573 if (UseMaskForCond || UseMaskForGaps) 3574 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3575 Alignment, AddressSpace, 3576 UseMaskForCond, UseMaskForGaps); 3577 3578 // VecTy for interleave memop is <VF*Factor x Elt>. 3579 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 3580 // VecTy = <12 x i32>. 3581 3582 // Calculate the number of memory operations (NumOfMemOps), required 3583 // for load/store the VecTy. 3584 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 3585 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 3586 unsigned LegalVTSize = LegalVT.getStoreSize(); 3587 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 3588 3589 // Get the cost of one memory operation. 3590 Type *SingleMemOpTy = VectorType::get(VecTy->getVectorElementType(), 3591 LegalVT.getVectorNumElements()); 3592 unsigned MemOpCost = 3593 getMemoryOpCost(Opcode, SingleMemOpTy, Alignment, AddressSpace); 3594 3595 unsigned VF = VecTy->getVectorNumElements() / Factor; 3596 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 3597 3598 if (Opcode == Instruction::Load) { 3599 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 3600 // contain the cost of the optimized shuffle sequence that the 3601 // X86InterleavedAccess pass will generate. 3602 // The cost of loads and stores are computed separately from the table. 3603 3604 // X86InterleavedAccess support only the following interleaved-access group. 3605 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 3606 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 3607 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 3608 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 3609 }; 3610 3611 if (const auto *Entry = 3612 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 3613 return NumOfMemOps * MemOpCost + Entry->Cost; 3614 //If an entry does not exist, fallback to the default implementation. 3615 3616 // Kind of shuffle depends on number of loaded values. 3617 // If we load the entire data in one register, we can use a 1-src shuffle. 3618 // Otherwise, we'll merge 2 sources in each operation. 3619 TTI::ShuffleKind ShuffleKind = 3620 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 3621 3622 unsigned ShuffleCost = 3623 getShuffleCost(ShuffleKind, SingleMemOpTy, 0, nullptr); 3624 3625 unsigned NumOfLoadsInInterleaveGrp = 3626 Indices.size() ? Indices.size() : Factor; 3627 Type *ResultTy = VectorType::get(VecTy->getVectorElementType(), 3628 VecTy->getVectorNumElements() / Factor); 3629 unsigned NumOfResults = 3630 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 3631 NumOfLoadsInInterleaveGrp; 3632 3633 // About a half of the loads may be folded in shuffles when we have only 3634 // one result. If we have more than one result, we do not fold loads at all. 3635 unsigned NumOfUnfoldedLoads = 3636 NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 3637 3638 // Get a number of shuffle operations per result. 3639 unsigned NumOfShufflesPerResult = 3640 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 3641 3642 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3643 // When we have more than one destination, we need additional instructions 3644 // to keep sources. 3645 unsigned NumOfMoves = 0; 3646 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 3647 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 3648 3649 int Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 3650 NumOfUnfoldedLoads * MemOpCost + NumOfMoves; 3651 3652 return Cost; 3653 } 3654 3655 // Store. 3656 assert(Opcode == Instruction::Store && 3657 "Expected Store Instruction at this point"); 3658 // X86InterleavedAccess support only the following interleaved-access group. 3659 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 3660 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 3661 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 3662 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 3663 3664 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 3665 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 3666 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 3667 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 3668 }; 3669 3670 if (const auto *Entry = 3671 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 3672 return NumOfMemOps * MemOpCost + Entry->Cost; 3673 //If an entry does not exist, fallback to the default implementation. 3674 3675 // There is no strided stores meanwhile. And store can't be folded in 3676 // shuffle. 3677 unsigned NumOfSources = Factor; // The number of values to be merged. 3678 unsigned ShuffleCost = 3679 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, 0, nullptr); 3680 unsigned NumOfShufflesPerStore = NumOfSources - 1; 3681 3682 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 3683 // We need additional instructions to keep sources. 3684 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 3685 int Cost = NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 3686 NumOfMoves; 3687 return Cost; 3688 } 3689 3690 int X86TTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, 3691 unsigned Factor, 3692 ArrayRef<unsigned> Indices, 3693 unsigned Alignment, 3694 unsigned AddressSpace, 3695 bool UseMaskForCond, 3696 bool UseMaskForGaps) { 3697 auto isSupportedOnAVX512 = [](Type *VecTy, bool HasBW) { 3698 Type *EltTy = VecTy->getVectorElementType(); 3699 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 3700 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 3701 return true; 3702 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8)) 3703 return HasBW; 3704 return false; 3705 }; 3706 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 3707 return getInterleavedMemoryOpCostAVX512(Opcode, VecTy, Factor, Indices, 3708 Alignment, AddressSpace, 3709 UseMaskForCond, UseMaskForGaps); 3710 if (ST->hasAVX2()) 3711 return getInterleavedMemoryOpCostAVX2(Opcode, VecTy, Factor, Indices, 3712 Alignment, AddressSpace, 3713 UseMaskForCond, UseMaskForGaps); 3714 3715 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 3716 Alignment, AddressSpace, 3717 UseMaskForCond, UseMaskForGaps); 3718 } 3719