1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file implements a TargetTransformInfo analysis pass specific to the 10 /// X86 target machine. It uses the target's detailed information to provide 11 /// more precise answers to certain TTI queries, while letting the target 12 /// independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 /// About Cost Model numbers used below it's necessary to say the following: 16 /// the numbers correspond to some "generic" X86 CPU instead of usage of 17 /// concrete CPU model. Usually the numbers correspond to CPU where the feature 18 /// apeared at the first time. For example, if we do Subtarget.hasSSE42() in 19 /// the lookups below the cost is based on Nehalem as that was the first CPU 20 /// to support that feature level and thus has most likely the worst case cost. 21 /// Some examples of other technologies/CPUs: 22 /// SSE 3 - Pentium4 / Athlon64 23 /// SSE 4.1 - Penryn 24 /// SSE 4.2 - Nehalem 25 /// AVX - Sandy Bridge 26 /// AVX2 - Haswell 27 /// AVX-512 - Xeon Phi / Skylake 28 /// And some examples of instruction target dependent costs (latency) 29 /// divss sqrtss rsqrtss 30 /// AMD K7 11-16 19 3 31 /// Piledriver 9-24 13-15 5 32 /// Jaguar 14 16 2 33 /// Pentium II,III 18 30 2 34 /// Nehalem 7-14 7-18 3 35 /// Haswell 10-13 11 5 36 /// TODO: Develop and implement the target dependent cost model and 37 /// specialize cost numbers for different Cost Model Targets such as throughput, 38 /// code size, latency and uop count. 39 //===----------------------------------------------------------------------===// 40 41 #include "X86TargetTransformInfo.h" 42 #include "llvm/Analysis/TargetTransformInfo.h" 43 #include "llvm/CodeGen/BasicTTIImpl.h" 44 #include "llvm/CodeGen/CostTable.h" 45 #include "llvm/CodeGen/TargetLowering.h" 46 #include "llvm/IR/InstIterator.h" 47 #include "llvm/IR/IntrinsicInst.h" 48 #include "llvm/Support/Debug.h" 49 50 using namespace llvm; 51 52 #define DEBUG_TYPE "x86tti" 53 54 //===----------------------------------------------------------------------===// 55 // 56 // X86 cost model. 57 // 58 //===----------------------------------------------------------------------===// 59 60 TargetTransformInfo::PopcntSupportKind 61 X86TTIImpl::getPopcntSupport(unsigned TyWidth) { 62 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 63 // TODO: Currently the __builtin_popcount() implementation using SSE3 64 // instructions is inefficient. Once the problem is fixed, we should 65 // call ST->hasSSE3() instead of ST->hasPOPCNT(). 66 return ST->hasPOPCNT() ? TTI::PSK_FastHardware : TTI::PSK_Software; 67 } 68 69 llvm::Optional<unsigned> X86TTIImpl::getCacheSize( 70 TargetTransformInfo::CacheLevel Level) const { 71 switch (Level) { 72 case TargetTransformInfo::CacheLevel::L1D: 73 // - Penryn 74 // - Nehalem 75 // - Westmere 76 // - Sandy Bridge 77 // - Ivy Bridge 78 // - Haswell 79 // - Broadwell 80 // - Skylake 81 // - Kabylake 82 return 32 * 1024; // 32 KByte 83 case TargetTransformInfo::CacheLevel::L2D: 84 // - Penryn 85 // - Nehalem 86 // - Westmere 87 // - Sandy Bridge 88 // - Ivy Bridge 89 // - Haswell 90 // - Broadwell 91 // - Skylake 92 // - Kabylake 93 return 256 * 1024; // 256 KByte 94 } 95 96 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 97 } 98 99 llvm::Optional<unsigned> X86TTIImpl::getCacheAssociativity( 100 TargetTransformInfo::CacheLevel Level) const { 101 // - Penryn 102 // - Nehalem 103 // - Westmere 104 // - Sandy Bridge 105 // - Ivy Bridge 106 // - Haswell 107 // - Broadwell 108 // - Skylake 109 // - Kabylake 110 switch (Level) { 111 case TargetTransformInfo::CacheLevel::L1D: 112 LLVM_FALLTHROUGH; 113 case TargetTransformInfo::CacheLevel::L2D: 114 return 8; 115 } 116 117 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel"); 118 } 119 120 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const { 121 bool Vector = (ClassID == 1); 122 if (Vector && !ST->hasSSE1()) 123 return 0; 124 125 if (ST->is64Bit()) { 126 if (Vector && ST->hasAVX512()) 127 return 32; 128 return 16; 129 } 130 return 8; 131 } 132 133 TypeSize 134 X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 135 unsigned PreferVectorWidth = ST->getPreferVectorWidth(); 136 switch (K) { 137 case TargetTransformInfo::RGK_Scalar: 138 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); 139 case TargetTransformInfo::RGK_FixedWidthVector: 140 if (ST->hasAVX512() && PreferVectorWidth >= 512) 141 return TypeSize::getFixed(512); 142 if (ST->hasAVX() && PreferVectorWidth >= 256) 143 return TypeSize::getFixed(256); 144 if (ST->hasSSE1() && PreferVectorWidth >= 128) 145 return TypeSize::getFixed(128); 146 return TypeSize::getFixed(0); 147 case TargetTransformInfo::RGK_ScalableVector: 148 return TypeSize::getScalable(0); 149 } 150 151 llvm_unreachable("Unsupported register kind"); 152 } 153 154 unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const { 155 return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector) 156 .getFixedSize(); 157 } 158 159 unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) { 160 // If the loop will not be vectorized, don't interleave the loop. 161 // Let regular unroll to unroll the loop, which saves the overflow 162 // check and memory check cost. 163 if (VF == 1) 164 return 1; 165 166 if (ST->isAtom()) 167 return 1; 168 169 // Sandybridge and Haswell have multiple execution ports and pipelined 170 // vector units. 171 if (ST->hasAVX()) 172 return 4; 173 174 return 2; 175 } 176 177 InstructionCost X86TTIImpl::getArithmeticInstrCost( 178 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 179 TTI::OperandValueKind Op1Info, TTI::OperandValueKind Op2Info, 180 TTI::OperandValueProperties Opd1PropInfo, 181 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, 182 const Instruction *CxtI) { 183 // TODO: Handle more cost kinds. 184 if (CostKind != TTI::TCK_RecipThroughput) 185 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, 186 Op2Info, Opd1PropInfo, 187 Opd2PropInfo, Args, CxtI); 188 189 // vXi8 multiplications are always promoted to vXi16. 190 if (Opcode == Instruction::Mul && Ty->isVectorTy() && 191 Ty->getScalarSizeInBits() == 8) { 192 Type *WideVecTy = 193 VectorType::getExtendedElementVectorType(cast<VectorType>(Ty)); 194 return getCastInstrCost(Instruction::ZExt, WideVecTy, Ty, 195 TargetTransformInfo::CastContextHint::None, 196 CostKind) + 197 getCastInstrCost(Instruction::Trunc, Ty, WideVecTy, 198 TargetTransformInfo::CastContextHint::None, 199 CostKind) + 200 getArithmeticInstrCost(Opcode, WideVecTy, CostKind, Op1Info, Op2Info, 201 Opd1PropInfo, Opd2PropInfo); 202 } 203 204 // Legalize the type. 205 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 206 207 int ISD = TLI->InstructionOpcodeToISD(Opcode); 208 assert(ISD && "Invalid opcode"); 209 210 if (ISD == ISD::MUL && Args.size() == 2 && LT.second.isVector() && 211 LT.second.getScalarType() == MVT::i32) { 212 // Check if the operands can be represented as a smaller datatype. 213 bool Op1Signed = false, Op2Signed = false; 214 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 215 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 216 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 217 218 // If both are representable as i15 and at least one is constant, 219 // zero-extended, or sign-extended from vXi16 (or less pre-SSE41) then we 220 // can treat this as PMADDWD which has the same costs as a vXi16 multiply. 221 if (OpMinSize <= 15 && !ST->isPMADDWDSlow()) { 222 bool Op1Constant = 223 isa<ConstantDataVector>(Args[0]) || isa<ConstantVector>(Args[0]); 224 bool Op2Constant = 225 isa<ConstantDataVector>(Args[1]) || isa<ConstantVector>(Args[1]); 226 bool Op1Sext = isa<SExtInst>(Args[0]) && 227 (Op1MinSize == 15 || (Op1MinSize < 15 && !ST->hasSSE41())); 228 bool Op2Sext = isa<SExtInst>(Args[1]) && 229 (Op2MinSize == 15 || (Op2MinSize < 15 && !ST->hasSSE41())); 230 231 bool IsZeroExtended = !Op1Signed || !Op2Signed; 232 bool IsConstant = Op1Constant || Op2Constant; 233 bool IsSext = Op1Sext || Op2Sext; 234 if (IsConstant || IsZeroExtended || IsSext) 235 LT.second = 236 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); 237 } 238 } 239 240 // Vector multiply by pow2 will be simplified to shifts. 241 if (ISD == ISD::MUL && 242 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 243 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 244 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) 245 return getArithmeticInstrCost(Instruction::Shl, Ty, CostKind, Op1Info, 246 Op2Info, TargetTransformInfo::OP_None, 247 TargetTransformInfo::OP_None); 248 249 // On X86, vector signed division by constants power-of-two are 250 // normally expanded to the sequence SRA + SRL + ADD + SRA. 251 // The OperandValue properties may not be the same as that of the previous 252 // operation; conservatively assume OP_None. 253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && 254 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 255 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 256 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 257 InstructionCost Cost = 258 2 * getArithmeticInstrCost(Instruction::AShr, Ty, CostKind, Op1Info, 259 Op2Info, TargetTransformInfo::OP_None, 260 TargetTransformInfo::OP_None); 261 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 262 Op2Info, TargetTransformInfo::OP_None, 263 TargetTransformInfo::OP_None); 264 Cost += getArithmeticInstrCost(Instruction::Add, Ty, CostKind, Op1Info, 265 Op2Info, TargetTransformInfo::OP_None, 266 TargetTransformInfo::OP_None); 267 268 if (ISD == ISD::SREM) { 269 // For SREM: (X % C) is the equivalent of (X - (X/C)*C) 270 Cost += getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, Op1Info, 271 Op2Info); 272 Cost += getArithmeticInstrCost(Instruction::Sub, Ty, CostKind, Op1Info, 273 Op2Info); 274 } 275 276 return Cost; 277 } 278 279 // Vector unsigned division/remainder will be simplified to shifts/masks. 280 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && 281 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 282 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 283 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { 284 if (ISD == ISD::UDIV) 285 return getArithmeticInstrCost(Instruction::LShr, Ty, CostKind, Op1Info, 286 Op2Info, TargetTransformInfo::OP_None, 287 TargetTransformInfo::OP_None); 288 // UREM 289 return getArithmeticInstrCost(Instruction::And, Ty, CostKind, Op1Info, 290 Op2Info, TargetTransformInfo::OP_None, 291 TargetTransformInfo::OP_None); 292 } 293 294 static const CostTblEntry GLMCostTable[] = { 295 { ISD::FDIV, MVT::f32, 18 }, // divss 296 { ISD::FDIV, MVT::v4f32, 35 }, // divps 297 { ISD::FDIV, MVT::f64, 33 }, // divsd 298 { ISD::FDIV, MVT::v2f64, 65 }, // divpd 299 }; 300 301 if (ST->useGLMDivSqrtCosts()) 302 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, 303 LT.second)) 304 return LT.first * Entry->Cost; 305 306 static const CostTblEntry SLMCostTable[] = { 307 { ISD::MUL, MVT::v4i32, 11 }, // pmulld 308 { ISD::MUL, MVT::v8i16, 2 }, // pmullw 309 { ISD::FMUL, MVT::f64, 2 }, // mulsd 310 { ISD::FMUL, MVT::v2f64, 4 }, // mulpd 311 { ISD::FMUL, MVT::v4f32, 2 }, // mulps 312 { ISD::FDIV, MVT::f32, 17 }, // divss 313 { ISD::FDIV, MVT::v4f32, 39 }, // divps 314 { ISD::FDIV, MVT::f64, 32 }, // divsd 315 { ISD::FDIV, MVT::v2f64, 69 }, // divpd 316 { ISD::FADD, MVT::v2f64, 2 }, // addpd 317 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 318 // v2i64/v4i64 mul is custom lowered as a series of long: 319 // multiplies(3), shifts(3) and adds(2) 320 // slm muldq version throughput is 2 and addq throughput 4 321 // thus: 3X2 (muldq throughput) + 3X1 (shift throughput) + 322 // 3X4 (addq throughput) = 17 323 { ISD::MUL, MVT::v2i64, 17 }, 324 // slm addq\subq throughput is 4 325 { ISD::ADD, MVT::v2i64, 4 }, 326 { ISD::SUB, MVT::v2i64, 4 }, 327 }; 328 329 if (ST->useSLMArithCosts()) { 330 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { 331 // Check if the operands can be shrinked into a smaller datatype. 332 // TODO: Merge this into generiic vXi32 MUL patterns above. 333 bool Op1Signed = false; 334 unsigned Op1MinSize = BaseT::minRequiredElementSize(Args[0], Op1Signed); 335 bool Op2Signed = false; 336 unsigned Op2MinSize = BaseT::minRequiredElementSize(Args[1], Op2Signed); 337 338 bool SignedMode = Op1Signed || Op2Signed; 339 unsigned OpMinSize = std::max(Op1MinSize, Op2MinSize); 340 341 if (OpMinSize <= 7) 342 return LT.first * 3; // pmullw/sext 343 if (!SignedMode && OpMinSize <= 8) 344 return LT.first * 3; // pmullw/zext 345 if (OpMinSize <= 15) 346 return LT.first * 5; // pmullw/pmulhw/pshuf 347 if (!SignedMode && OpMinSize <= 16) 348 return LT.first * 5; // pmullw/pmulhw/pshuf 349 } 350 351 if (const auto *Entry = CostTableLookup(SLMCostTable, ISD, 352 LT.second)) { 353 return LT.first * Entry->Cost; 354 } 355 } 356 357 static const CostTblEntry AVX512BWUniformConstCostTable[] = { 358 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. 359 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. 360 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. 361 }; 362 363 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 364 ST->hasBWI()) { 365 if (const auto *Entry = CostTableLookup(AVX512BWUniformConstCostTable, ISD, 366 LT.second)) 367 return LT.first * Entry->Cost; 368 } 369 370 static const CostTblEntry AVX512UniformConstCostTable[] = { 371 { ISD::SRA, MVT::v2i64, 1 }, 372 { ISD::SRA, MVT::v4i64, 1 }, 373 { ISD::SRA, MVT::v8i64, 1 }, 374 375 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. 376 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. 377 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. 378 379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence 380 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence 381 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence 382 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence 383 }; 384 385 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 386 ST->hasAVX512()) { 387 if (const auto *Entry = CostTableLookup(AVX512UniformConstCostTable, ISD, 388 LT.second)) 389 return LT.first * Entry->Cost; 390 } 391 392 static const CostTblEntry AVX2UniformConstCostTable[] = { 393 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. 394 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. 395 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. 396 397 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 398 399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence 400 { ISD::SREM, MVT::v8i32, 8 }, // pmuludq+mul+sub sequence 401 { ISD::UDIV, MVT::v8i32, 5 }, // pmuludq sequence 402 { ISD::UREM, MVT::v8i32, 7 }, // pmuludq+mul+sub sequence 403 }; 404 405 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 406 ST->hasAVX2()) { 407 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, 408 LT.second)) 409 return LT.first * Entry->Cost; 410 } 411 412 static const CostTblEntry SSE2UniformConstCostTable[] = { 413 { ISD::SHL, MVT::v16i8, 2 }, // psllw + pand. 414 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. 415 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 416 417 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. 418 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. 419 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. 420 421 { ISD::SDIV, MVT::v8i32, 12+2 }, // 2*pmuludq sequence + split. 422 { ISD::SREM, MVT::v8i32, 16+2 }, // 2*pmuludq+mul+sub sequence + split. 423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence 424 { ISD::SREM, MVT::v4i32, 8 }, // pmuludq+mul+sub sequence 425 { ISD::UDIV, MVT::v8i32, 10+2 }, // 2*pmuludq sequence + split. 426 { ISD::UREM, MVT::v8i32, 14+2 }, // 2*pmuludq+mul+sub sequence + split. 427 { ISD::UDIV, MVT::v4i32, 5 }, // pmuludq sequence 428 { ISD::UREM, MVT::v4i32, 7 }, // pmuludq+mul+sub sequence 429 }; 430 431 // XOP has faster vXi8 shifts. 432 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 433 ST->hasSSE2() && !ST->hasXOP()) { 434 if (const auto *Entry = 435 CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second)) 436 return LT.first * Entry->Cost; 437 } 438 439 static const CostTblEntry AVX512BWConstCostTable[] = { 440 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 441 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 442 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence 443 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence 445 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence 446 { ISD::UDIV, MVT::v32i16, 6 }, // vpmulhuw sequence 447 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence 448 }; 449 450 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 451 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 452 ST->hasBWI()) { 453 if (const auto *Entry = 454 CostTableLookup(AVX512BWConstCostTable, ISD, LT.second)) 455 return LT.first * Entry->Cost; 456 } 457 458 static const CostTblEntry AVX512ConstCostTable[] = { 459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence 460 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence 461 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence 462 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence 463 { ISD::SDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 464 { ISD::SREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 465 { ISD::UDIV, MVT::v64i8, 28 }, // 4*ext+4*pmulhw sequence 466 { ISD::UREM, MVT::v64i8, 32 }, // 4*ext+4*pmulhw+mul+sub sequence 467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence 468 { ISD::SREM, MVT::v32i16, 16 }, // 2*vpmulhw+mul+sub sequence 469 { ISD::UDIV, MVT::v32i16, 12 }, // 2*vpmulhuw sequence 470 { ISD::UREM, MVT::v32i16, 16 }, // 2*vpmulhuw+mul+sub sequence 471 }; 472 473 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 474 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 475 ST->hasAVX512()) { 476 if (const auto *Entry = 477 CostTableLookup(AVX512ConstCostTable, ISD, LT.second)) 478 return LT.first * Entry->Cost; 479 } 480 481 static const CostTblEntry AVX2ConstCostTable[] = { 482 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 483 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 484 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence 485 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 487 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence 488 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 489 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence 490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 491 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence 492 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 493 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence 494 }; 495 496 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 497 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 498 ST->hasAVX2()) { 499 if (const auto *Entry = CostTableLookup(AVX2ConstCostTable, ISD, LT.second)) 500 return LT.first * Entry->Cost; 501 } 502 503 static const CostTblEntry SSE2ConstCostTable[] = { 504 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 505 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 506 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 507 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 508 { ISD::UDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split. 509 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. 510 { ISD::UDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence 511 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence 512 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. 513 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. 514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence 515 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence 516 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. 517 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. 518 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence 519 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence 520 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. 521 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. 522 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence 523 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence 524 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. 525 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. 526 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence 527 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence 528 }; 529 530 if ((Op2Info == TargetTransformInfo::OK_UniformConstantValue || 531 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && 532 ST->hasSSE2()) { 533 // pmuldq sequence. 534 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) 535 return LT.first * 32; 536 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) 537 return LT.first * 38; 538 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) 539 return LT.first * 15; 540 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) 541 return LT.first * 20; 542 543 if (const auto *Entry = CostTableLookup(SSE2ConstCostTable, ISD, LT.second)) 544 return LT.first * Entry->Cost; 545 } 546 547 static const CostTblEntry AVX512BWShiftCostTable[] = { 548 { ISD::SHL, MVT::v16i8, 4 }, // extend/vpsllvw/pack sequence. 549 { ISD::SRL, MVT::v16i8, 4 }, // extend/vpsrlvw/pack sequence. 550 { ISD::SRA, MVT::v16i8, 4 }, // extend/vpsravw/pack sequence. 551 { ISD::SHL, MVT::v32i8, 4 }, // extend/vpsllvw/pack sequence. 552 { ISD::SRL, MVT::v32i8, 4 }, // extend/vpsrlvw/pack sequence. 553 { ISD::SRA, MVT::v32i8, 6 }, // extend/vpsravw/pack sequence. 554 { ISD::SHL, MVT::v64i8, 6 }, // extend/vpsllvw/pack sequence. 555 { ISD::SRL, MVT::v64i8, 7 }, // extend/vpsrlvw/pack sequence. 556 { ISD::SRA, MVT::v64i8, 15 }, // extend/vpsravw/pack sequence. 557 558 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw 559 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw 560 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw 561 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw 562 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw 563 { ISD::SRA, MVT::v16i16, 1 }, // vpsravw 564 { ISD::SHL, MVT::v32i16, 1 }, // vpsllvw 565 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw 566 { ISD::SRA, MVT::v32i16, 1 }, // vpsravw 567 }; 568 569 if (ST->hasBWI()) 570 if (const auto *Entry = CostTableLookup(AVX512BWShiftCostTable, ISD, LT.second)) 571 return LT.first * Entry->Cost; 572 573 static const CostTblEntry AVX2UniformCostTable[] = { 574 // Uniform splats are cheaper for the following instructions. 575 { ISD::SHL, MVT::v16i16, 1 }, // psllw. 576 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. 577 { ISD::SRA, MVT::v16i16, 1 }, // psraw. 578 { ISD::SHL, MVT::v32i16, 2 }, // 2*psllw. 579 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. 580 { ISD::SRA, MVT::v32i16, 2 }, // 2*psraw. 581 582 { ISD::SHL, MVT::v8i32, 1 }, // pslld 583 { ISD::SRL, MVT::v8i32, 1 }, // psrld 584 { ISD::SRA, MVT::v8i32, 1 }, // psrad 585 { ISD::SHL, MVT::v4i64, 1 }, // psllq 586 { ISD::SRL, MVT::v4i64, 1 }, // psrlq 587 }; 588 589 if (ST->hasAVX2() && 590 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 591 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 592 if (const auto *Entry = 593 CostTableLookup(AVX2UniformCostTable, ISD, LT.second)) 594 return LT.first * Entry->Cost; 595 } 596 597 static const CostTblEntry SSE2UniformCostTable[] = { 598 // Uniform splats are cheaper for the following instructions. 599 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 600 { ISD::SHL, MVT::v4i32, 1 }, // pslld 601 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 602 603 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 604 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 605 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 606 607 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 608 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 609 }; 610 611 if (ST->hasSSE2() && 612 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 613 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 614 if (const auto *Entry = 615 CostTableLookup(SSE2UniformCostTable, ISD, LT.second)) 616 return LT.first * Entry->Cost; 617 } 618 619 static const CostTblEntry AVX512DQCostTable[] = { 620 { ISD::MUL, MVT::v2i64, 2 }, // pmullq 621 { ISD::MUL, MVT::v4i64, 2 }, // pmullq 622 { ISD::MUL, MVT::v8i64, 2 } // pmullq 623 }; 624 625 // Look for AVX512DQ lowering tricks for custom cases. 626 if (ST->hasDQI()) 627 if (const auto *Entry = CostTableLookup(AVX512DQCostTable, ISD, LT.second)) 628 return LT.first * Entry->Cost; 629 630 static const CostTblEntry AVX512BWCostTable[] = { 631 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. 632 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. 633 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. 634 }; 635 636 // Look for AVX512BW lowering tricks for custom cases. 637 if (ST->hasBWI()) 638 if (const auto *Entry = CostTableLookup(AVX512BWCostTable, ISD, LT.second)) 639 return LT.first * Entry->Cost; 640 641 static const CostTblEntry AVX512CostTable[] = { 642 { ISD::SHL, MVT::v4i32, 1 }, 643 { ISD::SRL, MVT::v4i32, 1 }, 644 { ISD::SRA, MVT::v4i32, 1 }, 645 { ISD::SHL, MVT::v8i32, 1 }, 646 { ISD::SRL, MVT::v8i32, 1 }, 647 { ISD::SRA, MVT::v8i32, 1 }, 648 { ISD::SHL, MVT::v16i32, 1 }, 649 { ISD::SRL, MVT::v16i32, 1 }, 650 { ISD::SRA, MVT::v16i32, 1 }, 651 652 { ISD::SHL, MVT::v2i64, 1 }, 653 { ISD::SRL, MVT::v2i64, 1 }, 654 { ISD::SHL, MVT::v4i64, 1 }, 655 { ISD::SRL, MVT::v4i64, 1 }, 656 { ISD::SHL, MVT::v8i64, 1 }, 657 { ISD::SRL, MVT::v8i64, 1 }, 658 659 { ISD::SRA, MVT::v2i64, 1 }, 660 { ISD::SRA, MVT::v4i64, 1 }, 661 { ISD::SRA, MVT::v8i64, 1 }, 662 663 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) 664 { ISD::MUL, MVT::v8i32, 1 }, // pmulld (Skylake from agner.org) 665 { ISD::MUL, MVT::v4i32, 1 }, // pmulld (Skylake from agner.org) 666 { ISD::MUL, MVT::v8i64, 6 }, // 3*pmuludq/3*shift/2*add 667 { ISD::MUL, MVT::i64, 1 }, // Skylake from http://www.agner.org/ 668 669 { ISD::FNEG, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 670 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 671 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 672 { ISD::FMUL, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 673 { ISD::FDIV, MVT::f64, 4 }, // Skylake from http://www.agner.org/ 674 { ISD::FDIV, MVT::v2f64, 4 }, // Skylake from http://www.agner.org/ 675 { ISD::FDIV, MVT::v4f64, 8 }, // Skylake from http://www.agner.org/ 676 { ISD::FDIV, MVT::v8f64, 16 }, // Skylake from http://www.agner.org/ 677 678 { ISD::FNEG, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 679 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 680 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 681 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 682 { ISD::FDIV, MVT::f32, 3 }, // Skylake from http://www.agner.org/ 683 { ISD::FDIV, MVT::v4f32, 3 }, // Skylake from http://www.agner.org/ 684 { ISD::FDIV, MVT::v8f32, 5 }, // Skylake from http://www.agner.org/ 685 { ISD::FDIV, MVT::v16f32, 10 }, // Skylake from http://www.agner.org/ 686 }; 687 688 if (ST->hasAVX512()) 689 if (const auto *Entry = CostTableLookup(AVX512CostTable, ISD, LT.second)) 690 return LT.first * Entry->Cost; 691 692 static const CostTblEntry AVX2ShiftCostTable[] = { 693 // Shifts on vXi64/vXi32 on AVX2 is legal even though we declare to 694 // customize them to detect the cases where shift amount is a scalar one. 695 { ISD::SHL, MVT::v4i32, 2 }, // vpsllvd (Haswell from agner.org) 696 { ISD::SRL, MVT::v4i32, 2 }, // vpsrlvd (Haswell from agner.org) 697 { ISD::SRA, MVT::v4i32, 2 }, // vpsravd (Haswell from agner.org) 698 { ISD::SHL, MVT::v8i32, 2 }, // vpsllvd (Haswell from agner.org) 699 { ISD::SRL, MVT::v8i32, 2 }, // vpsrlvd (Haswell from agner.org) 700 { ISD::SRA, MVT::v8i32, 2 }, // vpsravd (Haswell from agner.org) 701 { ISD::SHL, MVT::v2i64, 1 }, // vpsllvq (Haswell from agner.org) 702 { ISD::SRL, MVT::v2i64, 1 }, // vpsrlvq (Haswell from agner.org) 703 { ISD::SHL, MVT::v4i64, 1 }, // vpsllvq (Haswell from agner.org) 704 { ISD::SRL, MVT::v4i64, 1 }, // vpsrlvq (Haswell from agner.org) 705 }; 706 707 if (ST->hasAVX512()) { 708 if (ISD == ISD::SHL && LT.second == MVT::v32i16 && 709 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 710 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 711 // On AVX512, a packed v32i16 shift left by a constant build_vector 712 // is lowered into a vector multiply (vpmullw). 713 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 714 Op1Info, Op2Info, 715 TargetTransformInfo::OP_None, 716 TargetTransformInfo::OP_None); 717 } 718 719 // Look for AVX2 lowering tricks (XOP is always better at v4i32 shifts). 720 if (ST->hasAVX2() && !(ST->hasXOP() && LT.second == MVT::v4i32)) { 721 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 722 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 723 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 724 // On AVX2, a packed v16i16 shift left by a constant build_vector 725 // is lowered into a vector multiply (vpmullw). 726 return getArithmeticInstrCost(Instruction::Mul, Ty, CostKind, 727 Op1Info, Op2Info, 728 TargetTransformInfo::OP_None, 729 TargetTransformInfo::OP_None); 730 731 if (const auto *Entry = CostTableLookup(AVX2ShiftCostTable, ISD, LT.second)) 732 return LT.first * Entry->Cost; 733 } 734 735 static const CostTblEntry XOPShiftCostTable[] = { 736 // 128bit shifts take 1cy, but right shifts require negation beforehand. 737 { ISD::SHL, MVT::v16i8, 1 }, 738 { ISD::SRL, MVT::v16i8, 2 }, 739 { ISD::SRA, MVT::v16i8, 2 }, 740 { ISD::SHL, MVT::v8i16, 1 }, 741 { ISD::SRL, MVT::v8i16, 2 }, 742 { ISD::SRA, MVT::v8i16, 2 }, 743 { ISD::SHL, MVT::v4i32, 1 }, 744 { ISD::SRL, MVT::v4i32, 2 }, 745 { ISD::SRA, MVT::v4i32, 2 }, 746 { ISD::SHL, MVT::v2i64, 1 }, 747 { ISD::SRL, MVT::v2i64, 2 }, 748 { ISD::SRA, MVT::v2i64, 2 }, 749 // 256bit shifts require splitting if AVX2 didn't catch them above. 750 { ISD::SHL, MVT::v32i8, 2+2 }, 751 { ISD::SRL, MVT::v32i8, 4+2 }, 752 { ISD::SRA, MVT::v32i8, 4+2 }, 753 { ISD::SHL, MVT::v16i16, 2+2 }, 754 { ISD::SRL, MVT::v16i16, 4+2 }, 755 { ISD::SRA, MVT::v16i16, 4+2 }, 756 { ISD::SHL, MVT::v8i32, 2+2 }, 757 { ISD::SRL, MVT::v8i32, 4+2 }, 758 { ISD::SRA, MVT::v8i32, 4+2 }, 759 { ISD::SHL, MVT::v4i64, 2+2 }, 760 { ISD::SRL, MVT::v4i64, 4+2 }, 761 { ISD::SRA, MVT::v4i64, 4+2 }, 762 }; 763 764 // Look for XOP lowering tricks. 765 if (ST->hasXOP()) { 766 // If the right shift is constant then we'll fold the negation so 767 // it's as cheap as a left shift. 768 int ShiftISD = ISD; 769 if ((ShiftISD == ISD::SRL || ShiftISD == ISD::SRA) && 770 (Op2Info == TargetTransformInfo::OK_UniformConstantValue || 771 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)) 772 ShiftISD = ISD::SHL; 773 if (const auto *Entry = 774 CostTableLookup(XOPShiftCostTable, ShiftISD, LT.second)) 775 return LT.first * Entry->Cost; 776 } 777 778 static const CostTblEntry SSE2UniformShiftCostTable[] = { 779 // Uniform splats are cheaper for the following instructions. 780 { ISD::SHL, MVT::v16i16, 2+2 }, // 2*psllw + split. 781 { ISD::SHL, MVT::v8i32, 2+2 }, // 2*pslld + split. 782 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. 783 784 { ISD::SRL, MVT::v16i16, 2+2 }, // 2*psrlw + split. 785 { ISD::SRL, MVT::v8i32, 2+2 }, // 2*psrld + split. 786 { ISD::SRL, MVT::v4i64, 2+2 }, // 2*psrlq + split. 787 788 { ISD::SRA, MVT::v16i16, 2+2 }, // 2*psraw + split. 789 { ISD::SRA, MVT::v8i32, 2+2 }, // 2*psrad + split. 790 { ISD::SRA, MVT::v2i64, 4 }, // 2*psrad + shuffle. 791 { ISD::SRA, MVT::v4i64, 8+2 }, // 2*(2*psrad + shuffle) + split. 792 }; 793 794 if (ST->hasSSE2() && 795 ((Op2Info == TargetTransformInfo::OK_UniformConstantValue) || 796 (Op2Info == TargetTransformInfo::OK_UniformValue))) { 797 798 // Handle AVX2 uniform v4i64 ISD::SRA, it's not worth a table. 799 if (ISD == ISD::SRA && LT.second == MVT::v4i64 && ST->hasAVX2()) 800 return LT.first * 4; // 2*psrad + shuffle. 801 802 if (const auto *Entry = 803 CostTableLookup(SSE2UniformShiftCostTable, ISD, LT.second)) 804 return LT.first * Entry->Cost; 805 } 806 807 if (ISD == ISD::SHL && 808 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) { 809 MVT VT = LT.second; 810 // Vector shift left by non uniform constant can be lowered 811 // into vector multiply. 812 if (((VT == MVT::v8i16 || VT == MVT::v4i32) && ST->hasSSE2()) || 813 ((VT == MVT::v16i16 || VT == MVT::v8i32) && ST->hasAVX())) 814 ISD = ISD::MUL; 815 } 816 817 static const CostTblEntry AVX2CostTable[] = { 818 { ISD::SHL, MVT::v16i8, 6 }, // vpblendvb sequence. 819 { ISD::SHL, MVT::v32i8, 6 }, // vpblendvb sequence. 820 { ISD::SHL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 821 { ISD::SHL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 822 { ISD::SHL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 823 { ISD::SHL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 824 825 { ISD::SRL, MVT::v16i8, 6 }, // vpblendvb sequence. 826 { ISD::SRL, MVT::v32i8, 6 }, // vpblendvb sequence. 827 { ISD::SRL, MVT::v64i8, 12 }, // 2*vpblendvb sequence. 828 { ISD::SRL, MVT::v8i16, 5 }, // extend/vpsrlvd/pack sequence. 829 { ISD::SRL, MVT::v16i16, 7 }, // extend/vpsrlvd/pack sequence. 830 { ISD::SRL, MVT::v32i16, 14 }, // 2*extend/vpsrlvd/pack sequence. 831 832 { ISD::SRA, MVT::v16i8, 17 }, // vpblendvb sequence. 833 { ISD::SRA, MVT::v32i8, 17 }, // vpblendvb sequence. 834 { ISD::SRA, MVT::v64i8, 34 }, // 2*vpblendvb sequence. 835 { ISD::SRA, MVT::v8i16, 5 }, // extend/vpsravd/pack sequence. 836 { ISD::SRA, MVT::v16i16, 7 }, // extend/vpsravd/pack sequence. 837 { ISD::SRA, MVT::v32i16, 14 }, // 2*extend/vpsravd/pack sequence. 838 { ISD::SRA, MVT::v2i64, 2 }, // srl/xor/sub sequence. 839 { ISD::SRA, MVT::v4i64, 2 }, // srl/xor/sub sequence. 840 841 { ISD::SUB, MVT::v32i8, 1 }, // psubb 842 { ISD::ADD, MVT::v32i8, 1 }, // paddb 843 { ISD::SUB, MVT::v16i16, 1 }, // psubw 844 { ISD::ADD, MVT::v16i16, 1 }, // paddw 845 { ISD::SUB, MVT::v8i32, 1 }, // psubd 846 { ISD::ADD, MVT::v8i32, 1 }, // paddd 847 { ISD::SUB, MVT::v4i64, 1 }, // psubq 848 { ISD::ADD, MVT::v4i64, 1 }, // paddq 849 850 { ISD::MUL, MVT::v16i16, 1 }, // pmullw 851 { ISD::MUL, MVT::v8i32, 2 }, // pmulld (Haswell from agner.org) 852 { ISD::MUL, MVT::v4i64, 6 }, // 3*pmuludq/3*shift/2*add 853 854 { ISD::FNEG, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 855 { ISD::FNEG, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 856 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 857 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 858 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 859 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 860 { ISD::FMUL, MVT::f64, 1 }, // Haswell from http://www.agner.org/ 861 { ISD::FMUL, MVT::v2f64, 1 }, // Haswell from http://www.agner.org/ 862 { ISD::FMUL, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 863 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 864 865 { ISD::FDIV, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 866 { ISD::FDIV, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 867 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 868 { ISD::FDIV, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 869 { ISD::FDIV, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 870 { ISD::FDIV, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 871 }; 872 873 // Look for AVX2 lowering tricks for custom cases. 874 if (ST->hasAVX2()) 875 if (const auto *Entry = CostTableLookup(AVX2CostTable, ISD, LT.second)) 876 return LT.first * Entry->Cost; 877 878 static const CostTblEntry AVX1CostTable[] = { 879 // We don't have to scalarize unsupported ops. We can issue two half-sized 880 // operations and we only need to extract the upper YMM half. 881 // Two ops + 1 extract + 1 insert = 4. 882 { ISD::MUL, MVT::v16i16, 4 }, 883 { ISD::MUL, MVT::v8i32, 5 }, // BTVER2 from http://www.agner.org/ 884 { ISD::MUL, MVT::v4i64, 12 }, 885 886 { ISD::SUB, MVT::v32i8, 4 }, 887 { ISD::ADD, MVT::v32i8, 4 }, 888 { ISD::SUB, MVT::v16i16, 4 }, 889 { ISD::ADD, MVT::v16i16, 4 }, 890 { ISD::SUB, MVT::v8i32, 4 }, 891 { ISD::ADD, MVT::v8i32, 4 }, 892 { ISD::SUB, MVT::v4i64, 4 }, 893 { ISD::ADD, MVT::v4i64, 4 }, 894 895 { ISD::SHL, MVT::v32i8, 22 }, // pblendvb sequence + split. 896 { ISD::SHL, MVT::v8i16, 6 }, // pblendvb sequence. 897 { ISD::SHL, MVT::v16i16, 13 }, // pblendvb sequence + split. 898 { ISD::SHL, MVT::v4i32, 3 }, // pslld/paddd/cvttps2dq/pmulld 899 { ISD::SHL, MVT::v8i32, 9 }, // pslld/paddd/cvttps2dq/pmulld + split 900 { ISD::SHL, MVT::v2i64, 2 }, // Shift each lane + blend. 901 { ISD::SHL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 902 903 { ISD::SRL, MVT::v32i8, 23 }, // pblendvb sequence + split. 904 { ISD::SRL, MVT::v16i16, 28 }, // pblendvb sequence + split. 905 { ISD::SRL, MVT::v4i32, 6 }, // Shift each lane + blend. 906 { ISD::SRL, MVT::v8i32, 14 }, // Shift each lane + blend + split. 907 { ISD::SRL, MVT::v2i64, 2 }, // Shift each lane + blend. 908 { ISD::SRL, MVT::v4i64, 6 }, // Shift each lane + blend + split. 909 910 { ISD::SRA, MVT::v32i8, 44 }, // pblendvb sequence + split. 911 { ISD::SRA, MVT::v16i16, 28 }, // pblendvb sequence + split. 912 { ISD::SRA, MVT::v4i32, 6 }, // Shift each lane + blend. 913 { ISD::SRA, MVT::v8i32, 14 }, // Shift each lane + blend + split. 914 { ISD::SRA, MVT::v2i64, 5 }, // Shift each lane + blend. 915 { ISD::SRA, MVT::v4i64, 12 }, // Shift each lane + blend + split. 916 917 { ISD::FNEG, MVT::v4f64, 2 }, // BTVER2 from http://www.agner.org/ 918 { ISD::FNEG, MVT::v8f32, 2 }, // BTVER2 from http://www.agner.org/ 919 920 { ISD::FMUL, MVT::f64, 2 }, // BTVER2 from http://www.agner.org/ 921 { ISD::FMUL, MVT::v2f64, 2 }, // BTVER2 from http://www.agner.org/ 922 { ISD::FMUL, MVT::v4f64, 4 }, // BTVER2 from http://www.agner.org/ 923 924 { ISD::FDIV, MVT::f32, 14 }, // SNB from http://www.agner.org/ 925 { ISD::FDIV, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 926 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 927 { ISD::FDIV, MVT::f64, 22 }, // SNB from http://www.agner.org/ 928 { ISD::FDIV, MVT::v2f64, 22 }, // SNB from http://www.agner.org/ 929 { ISD::FDIV, MVT::v4f64, 44 }, // SNB from http://www.agner.org/ 930 }; 931 932 if (ST->hasAVX()) 933 if (const auto *Entry = CostTableLookup(AVX1CostTable, ISD, LT.second)) 934 return LT.first * Entry->Cost; 935 936 static const CostTblEntry SSE42CostTable[] = { 937 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 938 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 939 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 940 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 941 942 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 943 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 944 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 945 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 946 947 { ISD::FMUL, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 948 { ISD::FMUL, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ 949 { ISD::FMUL, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 950 { ISD::FMUL, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 951 952 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ 953 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ 954 { ISD::FDIV, MVT::f64, 22 }, // Nehalem from http://www.agner.org/ 955 { ISD::FDIV, MVT::v2f64, 22 }, // Nehalem from http://www.agner.org/ 956 957 { ISD::MUL, MVT::v2i64, 6 } // 3*pmuludq/3*shift/2*add 958 }; 959 960 if (ST->hasSSE42()) 961 if (const auto *Entry = CostTableLookup(SSE42CostTable, ISD, LT.second)) 962 return LT.first * Entry->Cost; 963 964 static const CostTblEntry SSE41CostTable[] = { 965 { ISD::SHL, MVT::v16i8, 10 }, // pblendvb sequence. 966 { ISD::SHL, MVT::v8i16, 11 }, // pblendvb sequence. 967 { ISD::SHL, MVT::v4i32, 4 }, // pslld/paddd/cvttps2dq/pmulld 968 969 { ISD::SRL, MVT::v16i8, 11 }, // pblendvb sequence. 970 { ISD::SRL, MVT::v8i16, 13 }, // pblendvb sequence. 971 { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend. 972 973 { ISD::SRA, MVT::v16i8, 21 }, // pblendvb sequence. 974 { ISD::SRA, MVT::v8i16, 13 }, // pblendvb sequence. 975 976 { ISD::MUL, MVT::v4i32, 2 } // pmulld (Nehalem from agner.org) 977 }; 978 979 if (ST->hasSSE41()) 980 if (const auto *Entry = CostTableLookup(SSE41CostTable, ISD, LT.second)) 981 return LT.first * Entry->Cost; 982 983 static const CostTblEntry SSE2CostTable[] = { 984 // We don't correctly identify costs of casts because they are marked as 985 // custom. 986 { ISD::SHL, MVT::v16i8, 13 }, // cmpgtb sequence. 987 { ISD::SHL, MVT::v8i16, 25 }, // cmpgtw sequence. 988 { ISD::SHL, MVT::v4i32, 16 }, // pslld/paddd/cvttps2dq/pmuludq. 989 { ISD::SHL, MVT::v2i64, 4 }, // splat+shuffle sequence. 990 991 { ISD::SRL, MVT::v16i8, 14 }, // cmpgtb sequence. 992 { ISD::SRL, MVT::v8i16, 16 }, // cmpgtw sequence. 993 { ISD::SRL, MVT::v4i32, 12 }, // Shift each lane + blend. 994 { ISD::SRL, MVT::v2i64, 4 }, // splat+shuffle sequence. 995 996 { ISD::SRA, MVT::v16i8, 27 }, // unpacked cmpgtb sequence. 997 { ISD::SRA, MVT::v8i16, 16 }, // cmpgtw sequence. 998 { ISD::SRA, MVT::v4i32, 12 }, // Shift each lane + blend. 999 { ISD::SRA, MVT::v2i64, 8 }, // srl/xor/sub splat+shuffle sequence. 1000 1001 { ISD::MUL, MVT::v8i16, 1 }, // pmullw 1002 { ISD::MUL, MVT::v4i32, 6 }, // 3*pmuludq/4*shuffle 1003 { ISD::MUL, MVT::v2i64, 8 }, // 3*pmuludq/3*shift/2*add 1004 1005 { ISD::FDIV, MVT::f32, 23 }, // Pentium IV from http://www.agner.org/ 1006 { ISD::FDIV, MVT::v4f32, 39 }, // Pentium IV from http://www.agner.org/ 1007 { ISD::FDIV, MVT::f64, 38 }, // Pentium IV from http://www.agner.org/ 1008 { ISD::FDIV, MVT::v2f64, 69 }, // Pentium IV from http://www.agner.org/ 1009 1010 { ISD::FNEG, MVT::f32, 1 }, // Pentium IV from http://www.agner.org/ 1011 { ISD::FNEG, MVT::f64, 1 }, // Pentium IV from http://www.agner.org/ 1012 { ISD::FNEG, MVT::v4f32, 1 }, // Pentium IV from http://www.agner.org/ 1013 { ISD::FNEG, MVT::v2f64, 1 }, // Pentium IV from http://www.agner.org/ 1014 1015 { ISD::FADD, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1016 { ISD::FADD, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1017 1018 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/ 1019 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/ 1020 }; 1021 1022 if (ST->hasSSE2()) 1023 if (const auto *Entry = CostTableLookup(SSE2CostTable, ISD, LT.second)) 1024 return LT.first * Entry->Cost; 1025 1026 static const CostTblEntry SSE1CostTable[] = { 1027 { ISD::FDIV, MVT::f32, 17 }, // Pentium III from http://www.agner.org/ 1028 { ISD::FDIV, MVT::v4f32, 34 }, // Pentium III from http://www.agner.org/ 1029 1030 { ISD::FNEG, MVT::f32, 2 }, // Pentium III from http://www.agner.org/ 1031 { ISD::FNEG, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1032 1033 { ISD::FADD, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1034 { ISD::FADD, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1035 1036 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/ 1037 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/ 1038 }; 1039 1040 if (ST->hasSSE1()) 1041 if (const auto *Entry = CostTableLookup(SSE1CostTable, ISD, LT.second)) 1042 return LT.first * Entry->Cost; 1043 1044 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 1045 { ISD::ADD, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1046 { ISD::SUB, MVT::i64, 1 }, // Core (Merom) from http://www.agner.org/ 1047 { ISD::MUL, MVT::i64, 2 }, // Nehalem from http://www.agner.org/ 1048 }; 1049 1050 if (ST->is64Bit()) 1051 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, LT.second)) 1052 return LT.first * Entry->Cost; 1053 1054 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 1055 { ISD::ADD, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1056 { ISD::ADD, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1057 { ISD::ADD, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1058 1059 { ISD::SUB, MVT::i8, 1 }, // Pentium III from http://www.agner.org/ 1060 { ISD::SUB, MVT::i16, 1 }, // Pentium III from http://www.agner.org/ 1061 { ISD::SUB, MVT::i32, 1 }, // Pentium III from http://www.agner.org/ 1062 }; 1063 1064 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, LT.second)) 1065 return LT.first * Entry->Cost; 1066 1067 // It is not a good idea to vectorize division. We have to scalarize it and 1068 // in the process we will often end up having to spilling regular 1069 // registers. The overhead of division is going to dominate most kernels 1070 // anyways so try hard to prevent vectorization of division - it is 1071 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 1072 // to hide "20 cycles" for each lane. 1073 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM || 1074 ISD == ISD::UDIV || ISD == ISD::UREM)) { 1075 InstructionCost ScalarCost = getArithmeticInstrCost( 1076 Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info, 1077 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 1078 return 20 * LT.first * LT.second.getVectorNumElements() * ScalarCost; 1079 } 1080 1081 // Fallback to the default implementation. 1082 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, Op2Info); 1083 } 1084 1085 InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, 1086 VectorType *BaseTp, 1087 ArrayRef<int> Mask, int Index, 1088 VectorType *SubTp, 1089 ArrayRef<const Value *> Args) { 1090 // 64-bit packed float vectors (v2f32) are widened to type v4f32. 1091 // 64-bit packed integer vectors (v2i32) are widened to type v4i32. 1092 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, BaseTp); 1093 1094 Kind = improveShuffleKindFromMask(Kind, Mask); 1095 // Treat Transpose as 2-op shuffles - there's no difference in lowering. 1096 if (Kind == TTI::SK_Transpose) 1097 Kind = TTI::SK_PermuteTwoSrc; 1098 1099 // For Broadcasts we are splatting the first element from the first input 1100 // register, so only need to reference that input and all the output 1101 // registers are the same. 1102 if (Kind == TTI::SK_Broadcast) 1103 LT.first = 1; 1104 1105 // Subvector extractions are free if they start at the beginning of a 1106 // vector and cheap if the subvectors are aligned. 1107 if (Kind == TTI::SK_ExtractSubvector && LT.second.isVector()) { 1108 int NumElts = LT.second.getVectorNumElements(); 1109 if ((Index % NumElts) == 0) 1110 return 0; 1111 std::pair<InstructionCost, MVT> SubLT = 1112 TLI->getTypeLegalizationCost(DL, SubTp); 1113 if (SubLT.second.isVector()) { 1114 int NumSubElts = SubLT.second.getVectorNumElements(); 1115 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1116 return SubLT.first; 1117 // Handle some cases for widening legalization. For now we only handle 1118 // cases where the original subvector was naturally aligned and evenly 1119 // fit in its legalized subvector type. 1120 // FIXME: Remove some of the alignment restrictions. 1121 // FIXME: We can use permq for 64-bit or larger extracts from 256-bit 1122 // vectors. 1123 int OrigSubElts = cast<FixedVectorType>(SubTp)->getNumElements(); 1124 if (NumSubElts > OrigSubElts && (Index % OrigSubElts) == 0 && 1125 (NumSubElts % OrigSubElts) == 0 && 1126 LT.second.getVectorElementType() == 1127 SubLT.second.getVectorElementType() && 1128 LT.second.getVectorElementType().getSizeInBits() == 1129 BaseTp->getElementType()->getPrimitiveSizeInBits()) { 1130 assert(NumElts >= NumSubElts && NumElts > OrigSubElts && 1131 "Unexpected number of elements!"); 1132 auto *VecTy = FixedVectorType::get(BaseTp->getElementType(), 1133 LT.second.getVectorNumElements()); 1134 auto *SubTy = FixedVectorType::get(BaseTp->getElementType(), 1135 SubLT.second.getVectorNumElements()); 1136 int ExtractIndex = alignDown((Index % NumElts), NumSubElts); 1137 InstructionCost ExtractCost = getShuffleCost( 1138 TTI::SK_ExtractSubvector, VecTy, None, ExtractIndex, SubTy); 1139 1140 // If the original size is 32-bits or more, we can use pshufd. Otherwise 1141 // if we have SSSE3 we can use pshufb. 1142 if (SubTp->getPrimitiveSizeInBits() >= 32 || ST->hasSSSE3()) 1143 return ExtractCost + 1; // pshufd or pshufb 1144 1145 assert(SubTp->getPrimitiveSizeInBits() == 16 && 1146 "Unexpected vector size"); 1147 1148 return ExtractCost + 2; // worst case pshufhw + pshufd 1149 } 1150 } 1151 } 1152 1153 // Subvector insertions are cheap if the subvectors are aligned. 1154 // Note that in general, the insertion starting at the beginning of a vector 1155 // isn't free, because we need to preserve the rest of the wide vector. 1156 if (Kind == TTI::SK_InsertSubvector && LT.second.isVector()) { 1157 int NumElts = LT.second.getVectorNumElements(); 1158 std::pair<InstructionCost, MVT> SubLT = 1159 TLI->getTypeLegalizationCost(DL, SubTp); 1160 if (SubLT.second.isVector()) { 1161 int NumSubElts = SubLT.second.getVectorNumElements(); 1162 if ((Index % NumSubElts) == 0 && (NumElts % NumSubElts) == 0) 1163 return SubLT.first; 1164 } 1165 1166 // If the insertion isn't aligned, treat it like a 2-op shuffle. 1167 Kind = TTI::SK_PermuteTwoSrc; 1168 } 1169 1170 // Handle some common (illegal) sub-vector types as they are often very cheap 1171 // to shuffle even on targets without PSHUFB. 1172 EVT VT = TLI->getValueType(DL, BaseTp); 1173 if (VT.isSimple() && VT.isVector() && VT.getSizeInBits() < 128 && 1174 !ST->hasSSSE3()) { 1175 static const CostTblEntry SSE2SubVectorShuffleTbl[] = { 1176 {TTI::SK_Broadcast, MVT::v4i16, 1}, // pshuflw 1177 {TTI::SK_Broadcast, MVT::v2i16, 1}, // pshuflw 1178 {TTI::SK_Broadcast, MVT::v8i8, 2}, // punpck/pshuflw 1179 {TTI::SK_Broadcast, MVT::v4i8, 2}, // punpck/pshuflw 1180 {TTI::SK_Broadcast, MVT::v2i8, 1}, // punpck 1181 1182 {TTI::SK_Reverse, MVT::v4i16, 1}, // pshuflw 1183 {TTI::SK_Reverse, MVT::v2i16, 1}, // pshuflw 1184 {TTI::SK_Reverse, MVT::v4i8, 3}, // punpck/pshuflw/packus 1185 {TTI::SK_Reverse, MVT::v2i8, 1}, // punpck 1186 1187 {TTI::SK_PermuteTwoSrc, MVT::v4i16, 2}, // punpck/pshuflw 1188 {TTI::SK_PermuteTwoSrc, MVT::v2i16, 2}, // punpck/pshuflw 1189 {TTI::SK_PermuteTwoSrc, MVT::v8i8, 7}, // punpck/pshuflw 1190 {TTI::SK_PermuteTwoSrc, MVT::v4i8, 4}, // punpck/pshuflw 1191 {TTI::SK_PermuteTwoSrc, MVT::v2i8, 2}, // punpck 1192 1193 {TTI::SK_PermuteSingleSrc, MVT::v4i16, 1}, // pshuflw 1194 {TTI::SK_PermuteSingleSrc, MVT::v2i16, 1}, // pshuflw 1195 {TTI::SK_PermuteSingleSrc, MVT::v8i8, 5}, // punpck/pshuflw 1196 {TTI::SK_PermuteSingleSrc, MVT::v4i8, 3}, // punpck/pshuflw 1197 {TTI::SK_PermuteSingleSrc, MVT::v2i8, 1}, // punpck 1198 }; 1199 1200 if (ST->hasSSE2()) 1201 if (const auto *Entry = 1202 CostTableLookup(SSE2SubVectorShuffleTbl, Kind, VT.getSimpleVT())) 1203 return Entry->Cost; 1204 } 1205 1206 // We are going to permute multiple sources and the result will be in multiple 1207 // destinations. Providing an accurate cost only for splits where the element 1208 // type remains the same. 1209 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) { 1210 MVT LegalVT = LT.second; 1211 if (LegalVT.isVector() && 1212 LegalVT.getVectorElementType().getSizeInBits() == 1213 BaseTp->getElementType()->getPrimitiveSizeInBits() && 1214 LegalVT.getVectorNumElements() < 1215 cast<FixedVectorType>(BaseTp)->getNumElements()) { 1216 1217 unsigned VecTySize = DL.getTypeStoreSize(BaseTp); 1218 unsigned LegalVTSize = LegalVT.getStoreSize(); 1219 // Number of source vectors after legalization: 1220 unsigned NumOfSrcs = (VecTySize + LegalVTSize - 1) / LegalVTSize; 1221 // Number of destination vectors after legalization: 1222 InstructionCost NumOfDests = LT.first; 1223 1224 auto *SingleOpTy = FixedVectorType::get(BaseTp->getElementType(), 1225 LegalVT.getVectorNumElements()); 1226 1227 if (!Mask.empty() && NumOfDests.isValid()) { 1228 // Try to perform better estimation of the permutation. 1229 // 1. Split the source/destination vectors into real registers. 1230 // 2. Do the mask analysis to identify which real registers are 1231 // permuted. If more than 1 source registers are used for the 1232 // destination register building, the cost for this destination register 1233 // is (Number_of_source_register - 1) * Cost_PermuteTwoSrc. If only one 1234 // source register is used, build mask and calculate the cost as a cost 1235 // of PermuteSingleSrc. 1236 // Also, for the single register permute we try to identify if the 1237 // destination register is just a copy of the source register or the 1238 // copy of the previous destination register (the cost is 1239 // TTI::TCC_Basic). If the source register is just reused, the cost for 1240 // this operation is 0. 1241 unsigned E = *NumOfDests.getValue(); 1242 unsigned NormalizedVF = 1243 LegalVT.getVectorNumElements() * std::max(NumOfSrcs, E); 1244 unsigned NumOfSrcRegs = NormalizedVF / LegalVT.getVectorNumElements(); 1245 unsigned NumOfDestRegs = NormalizedVF / LegalVT.getVectorNumElements(); 1246 SmallVector<int> NormalizedMask(NormalizedVF, UndefMaskElem); 1247 copy(Mask, NormalizedMask.begin()); 1248 unsigned PrevSrcReg = 0; 1249 ArrayRef<int> PrevRegMask; 1250 InstructionCost Cost = 0; 1251 processShuffleMasks( 1252 NormalizedMask, NumOfSrcRegs, NumOfDestRegs, NumOfDestRegs, []() {}, 1253 [this, SingleOpTy, &PrevSrcReg, &PrevRegMask, 1254 &Cost](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) { 1255 if (!ShuffleVectorInst::isIdentityMask(RegMask)) { 1256 // Check if the previous register can be just copied to the next 1257 // one. 1258 if (PrevRegMask.empty() || PrevSrcReg != SrcReg || 1259 PrevRegMask != RegMask) 1260 Cost += getShuffleCost(TTI::SK_PermuteSingleSrc, SingleOpTy, 1261 RegMask, 0, nullptr); 1262 else 1263 // Just a copy of previous destination register. 1264 Cost += TTI::TCC_Basic; 1265 return; 1266 } 1267 if (SrcReg != DestReg && 1268 any_of(RegMask, [](int I) { return I != UndefMaskElem; })) { 1269 // Just a copy of the source register. 1270 Cost += TTI::TCC_Basic; 1271 } 1272 PrevSrcReg = SrcReg; 1273 PrevRegMask = RegMask; 1274 }, 1275 [this, SingleOpTy, &Cost](ArrayRef<int> RegMask, 1276 unsigned /*Unused*/, 1277 unsigned /*Unused*/) { 1278 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, RegMask, 1279 0, nullptr); 1280 }); 1281 return Cost; 1282 } 1283 1284 InstructionCost NumOfShuffles = (NumOfSrcs - 1) * NumOfDests; 1285 return NumOfShuffles * getShuffleCost(TTI::SK_PermuteTwoSrc, SingleOpTy, 1286 None, 0, nullptr); 1287 } 1288 1289 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1290 } 1291 1292 // For 2-input shuffles, we must account for splitting the 2 inputs into many. 1293 if (Kind == TTI::SK_PermuteTwoSrc && LT.first != 1) { 1294 // We assume that source and destination have the same vector type. 1295 InstructionCost NumOfDests = LT.first; 1296 InstructionCost NumOfShufflesPerDest = LT.first * 2 - 1; 1297 LT.first = NumOfDests * NumOfShufflesPerDest; 1298 } 1299 1300 static const CostTblEntry AVX512FP16ShuffleTbl[] = { 1301 {TTI::SK_Broadcast, MVT::v32f16, 1}, // vpbroadcastw 1302 {TTI::SK_Broadcast, MVT::v16f16, 1}, // vpbroadcastw 1303 {TTI::SK_Broadcast, MVT::v8f16, 1}, // vpbroadcastw 1304 1305 {TTI::SK_Reverse, MVT::v32f16, 2}, // vpermw 1306 {TTI::SK_Reverse, MVT::v16f16, 2}, // vpermw 1307 {TTI::SK_Reverse, MVT::v8f16, 1}, // vpshufb 1308 1309 {TTI::SK_PermuteSingleSrc, MVT::v32f16, 2}, // vpermw 1310 {TTI::SK_PermuteSingleSrc, MVT::v16f16, 2}, // vpermw 1311 {TTI::SK_PermuteSingleSrc, MVT::v8f16, 1}, // vpshufb 1312 1313 {TTI::SK_PermuteTwoSrc, MVT::v32f16, 2}, // vpermt2w 1314 {TTI::SK_PermuteTwoSrc, MVT::v16f16, 2}, // vpermt2w 1315 {TTI::SK_PermuteTwoSrc, MVT::v8f16, 2} // vpermt2w 1316 }; 1317 1318 if (!ST->useSoftFloat() && ST->hasFP16()) 1319 if (const auto *Entry = 1320 CostTableLookup(AVX512FP16ShuffleTbl, Kind, LT.second)) 1321 return LT.first * Entry->Cost; 1322 1323 static const CostTblEntry AVX512VBMIShuffleTbl[] = { 1324 {TTI::SK_Reverse, MVT::v64i8, 1}, // vpermb 1325 {TTI::SK_Reverse, MVT::v32i8, 1}, // vpermb 1326 1327 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 1}, // vpermb 1328 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 1}, // vpermb 1329 1330 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 2}, // vpermt2b 1331 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 2}, // vpermt2b 1332 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 2} // vpermt2b 1333 }; 1334 1335 if (ST->hasVBMI()) 1336 if (const auto *Entry = 1337 CostTableLookup(AVX512VBMIShuffleTbl, Kind, LT.second)) 1338 return LT.first * Entry->Cost; 1339 1340 static const CostTblEntry AVX512BWShuffleTbl[] = { 1341 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1342 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1343 1344 {TTI::SK_Reverse, MVT::v32i16, 2}, // vpermw 1345 {TTI::SK_Reverse, MVT::v16i16, 2}, // vpermw 1346 {TTI::SK_Reverse, MVT::v64i8, 2}, // pshufb + vshufi64x2 1347 1348 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 2}, // vpermw 1349 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 2}, // vpermw 1350 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 8}, // extend to v32i16 1351 1352 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 2}, // vpermt2w 1353 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 2}, // vpermt2w 1354 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 2}, // vpermt2w 1355 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 19}, // 6 * v32i8 + 1 1356 1357 {TTI::SK_Select, MVT::v32i16, 1}, // vblendmw 1358 {TTI::SK_Select, MVT::v64i8, 1}, // vblendmb 1359 }; 1360 1361 if (ST->hasBWI()) 1362 if (const auto *Entry = 1363 CostTableLookup(AVX512BWShuffleTbl, Kind, LT.second)) 1364 return LT.first * Entry->Cost; 1365 1366 static const CostTblEntry AVX512ShuffleTbl[] = { 1367 {TTI::SK_Broadcast, MVT::v8f64, 1}, // vbroadcastpd 1368 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps 1369 {TTI::SK_Broadcast, MVT::v8i64, 1}, // vpbroadcastq 1370 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd 1371 {TTI::SK_Broadcast, MVT::v32i16, 1}, // vpbroadcastw 1372 {TTI::SK_Broadcast, MVT::v64i8, 1}, // vpbroadcastb 1373 1374 {TTI::SK_Reverse, MVT::v8f64, 1}, // vpermpd 1375 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps 1376 {TTI::SK_Reverse, MVT::v8i64, 1}, // vpermq 1377 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd 1378 {TTI::SK_Reverse, MVT::v32i16, 7}, // per mca 1379 {TTI::SK_Reverse, MVT::v64i8, 7}, // per mca 1380 1381 {TTI::SK_PermuteSingleSrc, MVT::v8f64, 1}, // vpermpd 1382 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1383 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // vpermpd 1384 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps 1385 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1386 {TTI::SK_PermuteSingleSrc, MVT::v4f32, 1}, // vpermps 1387 {TTI::SK_PermuteSingleSrc, MVT::v8i64, 1}, // vpermq 1388 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1389 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // vpermq 1390 {TTI::SK_PermuteSingleSrc, MVT::v16i32, 1}, // vpermd 1391 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1392 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // vpermd 1393 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1394 1395 {TTI::SK_PermuteTwoSrc, MVT::v8f64, 1}, // vpermt2pd 1396 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps 1397 {TTI::SK_PermuteTwoSrc, MVT::v8i64, 1}, // vpermt2q 1398 {TTI::SK_PermuteTwoSrc, MVT::v16i32, 1}, // vpermt2d 1399 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 1}, // vpermt2pd 1400 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps 1401 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 1}, // vpermt2q 1402 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 1}, // vpermt2d 1403 {TTI::SK_PermuteTwoSrc, MVT::v2f64, 1}, // vpermt2pd 1404 {TTI::SK_PermuteTwoSrc, MVT::v4f32, 1}, // vpermt2ps 1405 {TTI::SK_PermuteTwoSrc, MVT::v2i64, 1}, // vpermt2q 1406 {TTI::SK_PermuteTwoSrc, MVT::v4i32, 1}, // vpermt2d 1407 1408 // FIXME: This just applies the type legalization cost rules above 1409 // assuming these completely split. 1410 {TTI::SK_PermuteSingleSrc, MVT::v32i16, 14}, 1411 {TTI::SK_PermuteSingleSrc, MVT::v64i8, 14}, 1412 {TTI::SK_PermuteTwoSrc, MVT::v32i16, 42}, 1413 {TTI::SK_PermuteTwoSrc, MVT::v64i8, 42}, 1414 1415 {TTI::SK_Select, MVT::v32i16, 1}, // vpternlogq 1416 {TTI::SK_Select, MVT::v64i8, 1}, // vpternlogq 1417 {TTI::SK_Select, MVT::v8f64, 1}, // vblendmpd 1418 {TTI::SK_Select, MVT::v16f32, 1}, // vblendmps 1419 {TTI::SK_Select, MVT::v8i64, 1}, // vblendmq 1420 {TTI::SK_Select, MVT::v16i32, 1}, // vblendmd 1421 }; 1422 1423 if (ST->hasAVX512()) 1424 if (const auto *Entry = CostTableLookup(AVX512ShuffleTbl, Kind, LT.second)) 1425 return LT.first * Entry->Cost; 1426 1427 static const CostTblEntry AVX2ShuffleTbl[] = { 1428 {TTI::SK_Broadcast, MVT::v4f64, 1}, // vbroadcastpd 1429 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps 1430 {TTI::SK_Broadcast, MVT::v4i64, 1}, // vpbroadcastq 1431 {TTI::SK_Broadcast, MVT::v8i32, 1}, // vpbroadcastd 1432 {TTI::SK_Broadcast, MVT::v16i16, 1}, // vpbroadcastw 1433 {TTI::SK_Broadcast, MVT::v32i8, 1}, // vpbroadcastb 1434 1435 {TTI::SK_Reverse, MVT::v4f64, 1}, // vpermpd 1436 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps 1437 {TTI::SK_Reverse, MVT::v4i64, 1}, // vpermq 1438 {TTI::SK_Reverse, MVT::v8i32, 1}, // vpermd 1439 {TTI::SK_Reverse, MVT::v16i16, 2}, // vperm2i128 + pshufb 1440 {TTI::SK_Reverse, MVT::v32i8, 2}, // vperm2i128 + pshufb 1441 1442 {TTI::SK_Select, MVT::v16i16, 1}, // vpblendvb 1443 {TTI::SK_Select, MVT::v32i8, 1}, // vpblendvb 1444 1445 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 1}, // vpermpd 1446 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps 1447 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 1}, // vpermq 1448 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 1}, // vpermd 1449 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vperm2i128 + 2*vpshufb 1450 // + vpblendvb 1451 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vperm2i128 + 2*vpshufb 1452 // + vpblendvb 1453 1454 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vpermpd + vblendpd 1455 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 3}, // 2*vpermps + vblendps 1456 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vpermq + vpblendd 1457 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 3}, // 2*vpermd + vpblendd 1458 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 7}, // 2*vperm2i128 + 4*vpshufb 1459 // + vpblendvb 1460 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 7}, // 2*vperm2i128 + 4*vpshufb 1461 // + vpblendvb 1462 }; 1463 1464 if (ST->hasAVX2()) 1465 if (const auto *Entry = CostTableLookup(AVX2ShuffleTbl, Kind, LT.second)) 1466 return LT.first * Entry->Cost; 1467 1468 static const CostTblEntry XOPShuffleTbl[] = { 1469 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vpermil2pd 1470 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 2}, // vperm2f128 + vpermil2ps 1471 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vpermil2pd 1472 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 2}, // vperm2f128 + vpermil2ps 1473 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 4}, // vextractf128 + 2*vpperm 1474 // + vinsertf128 1475 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 4}, // vextractf128 + 2*vpperm 1476 // + vinsertf128 1477 1478 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 9}, // 2*vextractf128 + 6*vpperm 1479 // + vinsertf128 1480 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 1}, // vpperm 1481 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 9}, // 2*vextractf128 + 6*vpperm 1482 // + vinsertf128 1483 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 1}, // vpperm 1484 }; 1485 1486 if (ST->hasXOP()) 1487 if (const auto *Entry = CostTableLookup(XOPShuffleTbl, Kind, LT.second)) 1488 return LT.first * Entry->Cost; 1489 1490 static const CostTblEntry AVX1ShuffleTbl[] = { 1491 {TTI::SK_Broadcast, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1492 {TTI::SK_Broadcast, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1493 {TTI::SK_Broadcast, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1494 {TTI::SK_Broadcast, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1495 {TTI::SK_Broadcast, MVT::v16i16, 3}, // vpshuflw + vpshufd + vinsertf128 1496 {TTI::SK_Broadcast, MVT::v32i8, 2}, // vpshufb + vinsertf128 1497 1498 {TTI::SK_Reverse, MVT::v4f64, 2}, // vperm2f128 + vpermilpd 1499 {TTI::SK_Reverse, MVT::v8f32, 2}, // vperm2f128 + vpermilps 1500 {TTI::SK_Reverse, MVT::v4i64, 2}, // vperm2f128 + vpermilpd 1501 {TTI::SK_Reverse, MVT::v8i32, 2}, // vperm2f128 + vpermilps 1502 {TTI::SK_Reverse, MVT::v16i16, 4}, // vextractf128 + 2*pshufb 1503 // + vinsertf128 1504 {TTI::SK_Reverse, MVT::v32i8, 4}, // vextractf128 + 2*pshufb 1505 // + vinsertf128 1506 1507 {TTI::SK_Select, MVT::v4i64, 1}, // vblendpd 1508 {TTI::SK_Select, MVT::v4f64, 1}, // vblendpd 1509 {TTI::SK_Select, MVT::v8i32, 1}, // vblendps 1510 {TTI::SK_Select, MVT::v8f32, 1}, // vblendps 1511 {TTI::SK_Select, MVT::v16i16, 3}, // vpand + vpandn + vpor 1512 {TTI::SK_Select, MVT::v32i8, 3}, // vpand + vpandn + vpor 1513 1514 {TTI::SK_PermuteSingleSrc, MVT::v4f64, 2}, // vperm2f128 + vshufpd 1515 {TTI::SK_PermuteSingleSrc, MVT::v4i64, 2}, // vperm2f128 + vshufpd 1516 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1517 {TTI::SK_PermuteSingleSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1518 {TTI::SK_PermuteSingleSrc, MVT::v16i16, 8}, // vextractf128 + 4*pshufb 1519 // + 2*por + vinsertf128 1520 {TTI::SK_PermuteSingleSrc, MVT::v32i8, 8}, // vextractf128 + 4*pshufb 1521 // + 2*por + vinsertf128 1522 1523 {TTI::SK_PermuteTwoSrc, MVT::v4f64, 3}, // 2*vperm2f128 + vshufpd 1524 {TTI::SK_PermuteTwoSrc, MVT::v4i64, 3}, // 2*vperm2f128 + vshufpd 1525 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 4}, // 2*vperm2f128 + 2*vshufps 1526 {TTI::SK_PermuteTwoSrc, MVT::v8i32, 4}, // 2*vperm2f128 + 2*vshufps 1527 {TTI::SK_PermuteTwoSrc, MVT::v16i16, 15}, // 2*vextractf128 + 8*pshufb 1528 // + 4*por + vinsertf128 1529 {TTI::SK_PermuteTwoSrc, MVT::v32i8, 15}, // 2*vextractf128 + 8*pshufb 1530 // + 4*por + vinsertf128 1531 }; 1532 1533 if (ST->hasAVX()) 1534 if (const auto *Entry = CostTableLookup(AVX1ShuffleTbl, Kind, LT.second)) 1535 return LT.first * Entry->Cost; 1536 1537 static const CostTblEntry SSE41ShuffleTbl[] = { 1538 {TTI::SK_Select, MVT::v2i64, 1}, // pblendw 1539 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1540 {TTI::SK_Select, MVT::v4i32, 1}, // pblendw 1541 {TTI::SK_Select, MVT::v4f32, 1}, // blendps 1542 {TTI::SK_Select, MVT::v8i16, 1}, // pblendw 1543 {TTI::SK_Select, MVT::v16i8, 1} // pblendvb 1544 }; 1545 1546 if (ST->hasSSE41()) 1547 if (const auto *Entry = CostTableLookup(SSE41ShuffleTbl, Kind, LT.second)) 1548 return LT.first * Entry->Cost; 1549 1550 static const CostTblEntry SSSE3ShuffleTbl[] = { 1551 {TTI::SK_Broadcast, MVT::v8i16, 1}, // pshufb 1552 {TTI::SK_Broadcast, MVT::v16i8, 1}, // pshufb 1553 1554 {TTI::SK_Reverse, MVT::v8i16, 1}, // pshufb 1555 {TTI::SK_Reverse, MVT::v16i8, 1}, // pshufb 1556 1557 {TTI::SK_Select, MVT::v8i16, 3}, // 2*pshufb + por 1558 {TTI::SK_Select, MVT::v16i8, 3}, // 2*pshufb + por 1559 1560 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 1}, // pshufb 1561 {TTI::SK_PermuteSingleSrc, MVT::v16i8, 1}, // pshufb 1562 1563 {TTI::SK_PermuteTwoSrc, MVT::v8i16, 3}, // 2*pshufb + por 1564 {TTI::SK_PermuteTwoSrc, MVT::v16i8, 3}, // 2*pshufb + por 1565 }; 1566 1567 if (ST->hasSSSE3()) 1568 if (const auto *Entry = CostTableLookup(SSSE3ShuffleTbl, Kind, LT.second)) 1569 return LT.first * Entry->Cost; 1570 1571 static const CostTblEntry SSE2ShuffleTbl[] = { 1572 {TTI::SK_Broadcast, MVT::v2f64, 1}, // shufpd 1573 {TTI::SK_Broadcast, MVT::v2i64, 1}, // pshufd 1574 {TTI::SK_Broadcast, MVT::v4i32, 1}, // pshufd 1575 {TTI::SK_Broadcast, MVT::v8i16, 2}, // pshuflw + pshufd 1576 {TTI::SK_Broadcast, MVT::v16i8, 3}, // unpck + pshuflw + pshufd 1577 1578 {TTI::SK_Reverse, MVT::v2f64, 1}, // shufpd 1579 {TTI::SK_Reverse, MVT::v2i64, 1}, // pshufd 1580 {TTI::SK_Reverse, MVT::v4i32, 1}, // pshufd 1581 {TTI::SK_Reverse, MVT::v8i16, 3}, // pshuflw + pshufhw + pshufd 1582 {TTI::SK_Reverse, MVT::v16i8, 9}, // 2*pshuflw + 2*pshufhw 1583 // + 2*pshufd + 2*unpck + packus 1584 1585 {TTI::SK_Select, MVT::v2i64, 1}, // movsd 1586 {TTI::SK_Select, MVT::v2f64, 1}, // movsd 1587 {TTI::SK_Select, MVT::v4i32, 2}, // 2*shufps 1588 {TTI::SK_Select, MVT::v8i16, 3}, // pand + pandn + por 1589 {TTI::SK_Select, MVT::v16i8, 3}, // pand + pandn + por 1590 1591 {TTI::SK_PermuteSingleSrc, MVT::v2f64, 1}, // shufpd 1592 {TTI::SK_PermuteSingleSrc, MVT::v2i64, 1}, // pshufd 1593 {TTI::SK_PermuteSingleSrc, MVT::v4i32, 1}, // pshufd 1594 {TTI::SK_PermuteSingleSrc, MVT::v8i16, 5}, // 2*pshuflw + 2*pshufhw 1595 // + pshufd/unpck 1596 { TTI::SK_PermuteSingleSrc, MVT::v16i8, 10 }, // 2*pshuflw + 2*pshufhw 1597 // + 2*pshufd + 2*unpck + 2*packus 1598 1599 { TTI::SK_PermuteTwoSrc, MVT::v2f64, 1 }, // shufpd 1600 { TTI::SK_PermuteTwoSrc, MVT::v2i64, 1 }, // shufpd 1601 { TTI::SK_PermuteTwoSrc, MVT::v4i32, 2 }, // 2*{unpck,movsd,pshufd} 1602 { TTI::SK_PermuteTwoSrc, MVT::v8i16, 8 }, // blend+permute 1603 { TTI::SK_PermuteTwoSrc, MVT::v16i8, 13 }, // blend+permute 1604 }; 1605 1606 static const CostTblEntry SSE3BroadcastLoadTbl[] = { 1607 {TTI::SK_Broadcast, MVT::v2f64, 0}, // broadcast handled by movddup 1608 }; 1609 1610 if (ST->hasSSE2()) { 1611 bool IsLoad = 1612 llvm::any_of(Args, [](const auto &V) { return isa<LoadInst>(V); }); 1613 if (ST->hasSSE3() && IsLoad) 1614 if (const auto *Entry = 1615 CostTableLookup(SSE3BroadcastLoadTbl, Kind, LT.second)) { 1616 assert(isLegalBroadcastLoad(BaseTp->getElementType(), 1617 LT.second.getVectorElementCount()) && 1618 "Table entry missing from isLegalBroadcastLoad()"); 1619 return LT.first * Entry->Cost; 1620 } 1621 1622 if (const auto *Entry = CostTableLookup(SSE2ShuffleTbl, Kind, LT.second)) 1623 return LT.first * Entry->Cost; 1624 } 1625 1626 static const CostTblEntry SSE1ShuffleTbl[] = { 1627 { TTI::SK_Broadcast, MVT::v4f32, 1 }, // shufps 1628 { TTI::SK_Reverse, MVT::v4f32, 1 }, // shufps 1629 { TTI::SK_Select, MVT::v4f32, 2 }, // 2*shufps 1630 { TTI::SK_PermuteSingleSrc, MVT::v4f32, 1 }, // shufps 1631 { TTI::SK_PermuteTwoSrc, MVT::v4f32, 2 }, // 2*shufps 1632 }; 1633 1634 if (ST->hasSSE1()) 1635 if (const auto *Entry = CostTableLookup(SSE1ShuffleTbl, Kind, LT.second)) 1636 return LT.first * Entry->Cost; 1637 1638 return BaseT::getShuffleCost(Kind, BaseTp, Mask, Index, SubTp); 1639 } 1640 1641 InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, 1642 Type *Src, 1643 TTI::CastContextHint CCH, 1644 TTI::TargetCostKind CostKind, 1645 const Instruction *I) { 1646 int ISD = TLI->InstructionOpcodeToISD(Opcode); 1647 assert(ISD && "Invalid opcode"); 1648 1649 // TODO: Allow non-throughput costs that aren't binary. 1650 auto AdjustCost = [&CostKind](InstructionCost Cost) -> InstructionCost { 1651 if (CostKind != TTI::TCK_RecipThroughput) 1652 return Cost == 0 ? 0 : 1; 1653 return Cost; 1654 }; 1655 1656 // The cost tables include both specific, custom (non-legal) src/dst type 1657 // conversions and generic, legalized types. We test for customs first, before 1658 // falling back to legalization. 1659 // FIXME: Need a better design of the cost table to handle non-simple types of 1660 // potential massive combinations (elem_num x src_type x dst_type). 1661 static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { 1662 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1663 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, 1664 1665 // Mask sign extend has an instruction. 1666 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1667 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1668 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1669 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1670 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1671 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1672 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1673 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1674 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1675 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1676 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1677 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1678 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1679 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1680 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, 1681 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, 1682 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v64i1, 1 }, 1683 1684 // Mask zero extend is a sext + shift. 1685 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1686 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1687 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1688 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1689 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1690 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1691 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1692 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1693 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1694 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1695 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1696 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1697 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1698 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1699 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, 1700 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, 1701 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v64i1, 2 }, 1702 1703 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1704 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1705 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1706 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1707 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1708 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1709 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1710 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1711 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1712 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1713 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1714 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1715 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1716 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1717 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, 1718 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, 1719 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i16, 2 }, 1720 1721 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 2 }, 1722 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // widen to zmm 1723 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i16, 2 }, // vpmovwb 1724 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 }, // vpmovwb 1725 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i16, 2 }, // vpmovwb 1726 }; 1727 1728 static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { 1729 // Mask sign extend has an instruction. 1730 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1731 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1732 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1733 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1734 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1735 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v16i1, 1 }, 1736 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, 1737 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, 1738 1739 // Mask zero extend is a sext + shift. 1740 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1741 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1742 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1743 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1744 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1745 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v16i1, 2 }, 1746 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, 1747 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, 1748 1749 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1750 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1751 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1752 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1753 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1754 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, 1755 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, 1756 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i64, 2 }, 1757 1758 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1759 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1760 1761 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, 1762 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, 1763 1764 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f32, 1 }, 1765 { ISD::FP_TO_SINT, MVT::v8i64, MVT::v8f64, 1 }, 1766 1767 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f32, 1 }, 1768 { ISD::FP_TO_UINT, MVT::v8i64, MVT::v8f64, 1 }, 1769 }; 1770 1771 // TODO: For AVX512DQ + AVX512VL, we also have cheap casts for 128-bit and 1772 // 256-bit wide vectors. 1773 1774 static const TypeConversionCostTblEntry AVX512FConversionTbl[] = { 1775 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, 1776 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, 1777 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 1778 1779 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 1780 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 1781 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 1782 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd 1783 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 1784 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 1785 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 1786 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd 1787 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd 1788 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd 1789 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd 1790 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd 1791 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq 1792 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq 1793 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq 1794 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb 1795 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb 1796 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb 1797 { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb 1798 { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb 1799 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw 1800 { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw 1801 { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb 1802 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb 1803 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb 1804 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb 1805 { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb 1806 { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb 1807 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw 1808 { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw 1809 { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw 1810 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd 1811 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd 1812 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb 1813 1814 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32 1815 { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 }, 1816 { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 }, 1817 1818 // Sign extend is zmm vpternlogd+vptruncdb. 1819 // Zero extend is zmm broadcast load+vptruncdw. 1820 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 }, 1821 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 }, 1822 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 }, 1823 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 }, 1824 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 }, 1825 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 }, 1826 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 }, 1827 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 }, 1828 1829 // Sign extend is zmm vpternlogd+vptruncdw. 1830 // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw. 1831 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 }, 1832 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 1833 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 }, 1834 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 1835 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 }, 1836 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 1837 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 }, 1838 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 1839 1840 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd 1841 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld 1842 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd 1843 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld 1844 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd 1845 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld 1846 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq 1847 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq 1848 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq 1849 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq 1850 1851 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd 1852 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld 1853 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq 1854 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq 1855 1856 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1857 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, 1858 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1859 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, 1860 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1861 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 }, 1862 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1863 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 }, 1864 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1865 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 }, 1866 1867 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1868 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right 1869 1870 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1871 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1872 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1873 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1874 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1875 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1876 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1877 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1878 1879 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, 1880 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, 1881 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, 1882 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, 1883 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, 1884 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, 1885 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, 1886 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, 1887 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 }, 1888 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 }, 1889 1890 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 1891 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 }, 1892 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 }, 1893 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 }, 1894 { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 }, 1895 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 }, 1896 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 }, 1897 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 }, 1898 { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 }, 1899 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 }, 1900 { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 }, 1901 1902 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 1903 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 }, 1904 { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 }, 1905 { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 }, 1906 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 }, 1907 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 }, 1908 }; 1909 1910 static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] { 1911 // Mask sign extend has an instruction. 1912 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 1 }, 1913 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, 1 }, 1914 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 1 }, 1915 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, 1 }, 1916 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 1 }, 1917 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, 1 }, 1918 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 1 }, 1919 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, 1 }, 1920 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, 1921 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v8i1, 1 }, 1922 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, 1923 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, 1924 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 1925 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, 1926 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v32i1, 1 }, 1927 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v64i1, 1 }, 1928 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v64i1, 1 }, 1929 1930 // Mask zero extend is a sext + shift. 1931 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 2 }, 1932 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v2i1, 2 }, 1933 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 2 }, 1934 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v2i1, 2 }, 1935 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 2 }, 1936 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v4i1, 2 }, 1937 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 2 }, 1938 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v4i1, 2 }, 1939 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, 1940 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v8i1, 2 }, 1941 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, 1942 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, 1943 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, 1944 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, 1945 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v32i1, 2 }, 1946 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v64i1, 2 }, 1947 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v64i1, 2 }, 1948 1949 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 2 }, 1950 { ISD::TRUNCATE, MVT::v2i1, MVT::v16i8, 2 }, 1951 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, 1952 { ISD::TRUNCATE, MVT::v2i1, MVT::v8i16, 2 }, 1953 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, 1954 { ISD::TRUNCATE, MVT::v4i1, MVT::v16i8, 2 }, 1955 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 2 }, 1956 { ISD::TRUNCATE, MVT::v4i1, MVT::v8i16, 2 }, 1957 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, 1958 { ISD::TRUNCATE, MVT::v8i1, MVT::v16i8, 2 }, 1959 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, 1960 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 2 }, 1961 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 2 }, 1962 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, 1963 { ISD::TRUNCATE, MVT::v32i1, MVT::v16i16, 2 }, 1964 { ISD::TRUNCATE, MVT::v64i1, MVT::v32i8, 2 }, 1965 { ISD::TRUNCATE, MVT::v64i1, MVT::v16i16, 2 }, 1966 1967 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, 1968 }; 1969 1970 static const TypeConversionCostTblEntry AVX512DQVLConversionTbl[] = { 1971 // Mask sign extend has an instruction. 1972 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, 1973 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v2i1, 1 }, 1974 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, 1975 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i1, 1 }, 1976 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, 1977 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i1, 1 }, 1978 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i1, 1 }, 1979 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, 1980 1981 // Mask zero extend is a sext + shift. 1982 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, 1983 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v2i1, 2 }, 1984 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, 1985 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i1, 2 }, 1986 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, 1987 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i1, 2 }, 1988 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i1, 2 }, 1989 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, 1990 1991 { ISD::TRUNCATE, MVT::v16i1, MVT::v4i64, 2 }, 1992 { ISD::TRUNCATE, MVT::v16i1, MVT::v8i32, 2 }, 1993 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, 1994 { ISD::TRUNCATE, MVT::v2i1, MVT::v4i32, 2 }, 1995 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, 1996 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, 1997 { ISD::TRUNCATE, MVT::v8i1, MVT::v4i64, 2 }, 1998 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 1999 2000 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 2001 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 2002 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 2003 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 2004 2005 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, 2006 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, 2007 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 }, 2008 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 1 }, 2009 2010 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v4f32, 1 }, 2011 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f32, 1 }, 2012 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, 2013 { ISD::FP_TO_SINT, MVT::v4i64, MVT::v4f64, 1 }, 2014 2015 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v4f32, 1 }, 2016 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 }, 2017 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 }, 2018 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f64, 1 }, 2019 }; 2020 2021 static const TypeConversionCostTblEntry AVX512VLConversionTbl[] = { 2022 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd 2023 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd 2024 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd 2025 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 8 }, // split+2*v8i8 2026 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq 2027 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq 2028 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq 2029 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 8 }, // split+2*v8i16 2030 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // vpslld+vptestmd 2031 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // vpslld+vptestmd 2032 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // vpslld+vptestmd 2033 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // vpsllq+vptestmq 2034 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // vpsllq+vptestmq 2035 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // vpmovqd 2036 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 }, // vpmovqb 2037 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, // vpmovqw 2038 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 }, // vpmovwb 2039 2040 // sign extend is vpcmpeq+maskedmove+vpmovdw+vpacksswb 2041 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw+vpackuswb 2042 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 5 }, 2043 { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 6 }, 2044 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 5 }, 2045 { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 6 }, 2046 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 5 }, 2047 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 6 }, 2048 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 10 }, 2049 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 12 }, 2050 2051 // sign extend is vpcmpeq+maskedmove+vpmovdw 2052 // zero extend is vpcmpeq+maskedmove+vpmovdw+vpsrlw 2053 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 4 }, 2054 { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 5 }, 2055 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 4 }, 2056 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 5 }, 2057 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 4 }, 2058 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 5 }, 2059 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 10 }, 2060 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 12 }, 2061 2062 { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // vpternlogd 2063 { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // vpternlogd+psrld 2064 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // vpternlogd 2065 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // vpternlogd+psrld 2066 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // vpternlogd 2067 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // vpternlogd+psrld 2068 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // vpternlogq 2069 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // vpternlogq+psrlq 2070 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // vpternlogq 2071 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // vpternlogq+psrlq 2072 2073 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2074 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 1 }, 2075 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2076 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 1 }, 2077 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2078 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 }, 2079 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2080 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 1 }, 2081 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2082 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 2083 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2084 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 2085 2086 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2087 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2088 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2089 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2090 2091 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2092 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2093 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2094 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 1 }, 2095 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2096 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 1 }, 2097 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 2098 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2099 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2100 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2101 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 5 }, 2102 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2103 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 5 }, 2104 2105 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2106 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 }, 2107 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f32, 5 }, 2108 2109 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 }, 2110 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 }, 2111 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 }, 2112 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 1 }, 2113 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 1 }, 2114 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 1 }, 2115 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 }, 2116 }; 2117 2118 static const TypeConversionCostTblEntry AVX2ConversionTbl[] = { 2119 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2120 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 }, 2121 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2122 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 }, 2123 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2124 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, 2125 2126 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2127 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 2 }, 2128 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2129 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 2 }, 2130 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2131 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, 2132 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2133 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 2 }, 2134 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2135 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, 2136 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2137 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 3 }, 2138 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2139 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 2140 2141 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, 2142 2143 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 4 }, 2144 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4 }, 2145 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 1 }, 2146 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 1 }, 2147 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 1 }, 2148 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 4 }, 2149 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 4 }, 2150 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 1 }, 2151 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 1 }, 2152 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 5 }, 2153 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 2154 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 }, 2155 2156 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, 2157 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, 2158 2159 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 1 }, 2160 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 1 }, 2161 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 1 }, 2162 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 3 }, 2163 2164 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 3 }, 2165 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 3 }, 2166 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 1 }, 2167 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2168 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2169 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4 }, 2170 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 3 }, 2171 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 4 }, 2172 2173 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2174 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2175 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2176 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2177 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 2178 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 2179 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 3 }, 2180 2181 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 2 }, 2182 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 2 }, 2183 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 2 }, 2184 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 2 }, 2185 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 2186 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 2187 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 2 }, 2188 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2189 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2190 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2191 }; 2192 2193 static const TypeConversionCostTblEntry AVXConversionTbl[] = { 2194 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 }, 2195 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 }, 2196 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 }, 2197 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 }, 2198 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2199 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 }, 2200 2201 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2202 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v16i8, 3 }, 2203 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2204 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v16i8, 3 }, 2205 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2206 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 }, 2207 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2208 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v8i16, 3 }, 2209 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2210 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 }, 2211 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2212 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 }, 2213 2214 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 4 }, 2215 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 5 }, 2216 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 4 }, 2217 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 9 }, 2218 { ISD::TRUNCATE, MVT::v16i1, MVT::v16i64, 11 }, 2219 2220 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 6 }, 2221 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 2222 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 2 }, // and+extract+packuswb 2223 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i32, 5 }, 2224 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2225 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i64, 5 }, 2226 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i64, 3 }, // and+extract+2*packusdw 2227 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 }, 2228 2229 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 2230 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 2231 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 2232 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2233 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2234 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2235 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2236 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2237 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, 2238 { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 4 }, 2239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 5 }, 2240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i64, 8 }, 2241 2242 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 2243 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 2244 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 2245 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v16i8, 4 }, 2246 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v16i8, 2 }, 2247 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, 2248 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v8i16, 2 }, 2249 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 4 }, 2250 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 4 }, 2251 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2252 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 2253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, 2254 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 10 }, 2255 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 10 }, 2256 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 18 }, 2257 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 5 }, 2258 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 10 }, 2259 2260 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v8f32, 2 }, 2261 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f64, 2 }, 2262 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v8f32, 2 }, 2263 { ISD::FP_TO_SINT, MVT::v32i8, MVT::v4f64, 2 }, 2264 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 2 }, 2265 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f64, 2 }, 2266 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v8f32, 2 }, 2267 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v4f64, 2 }, 2268 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f64, 2 }, 2269 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f32, 2 }, 2270 { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 5 }, 2271 2272 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v8f32, 2 }, 2273 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f64, 2 }, 2274 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v8f32, 2 }, 2275 { ISD::FP_TO_UINT, MVT::v32i8, MVT::v4f64, 2 }, 2276 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 2 }, 2277 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f64, 2 }, 2278 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v8f32, 2 }, 2279 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v4f64, 2 }, 2280 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 3 }, 2281 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2282 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 6 }, 2283 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 7 }, 2284 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v4f64, 7 }, 2285 2286 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, 2287 { ISD::FP_ROUND, MVT::v4f32, MVT::v4f64, 1 }, 2288 }; 2289 2290 static const TypeConversionCostTblEntry SSE41ConversionTbl[] = { 2291 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2292 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 1 }, 2293 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2294 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 1 }, 2295 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2296 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2297 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2298 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 1 }, 2299 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2300 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2301 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2302 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2303 2304 // These truncates end up widening elements. 2305 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 1 }, // PMOVXZBQ 2306 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 1 }, // PMOVXZWQ 2307 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 1 }, // PMOVXZBD 2308 2309 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 2 }, 2310 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 2 }, 2311 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 2 }, 2312 2313 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2314 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2315 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 1 }, 2316 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 1 }, 2317 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2318 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2319 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2320 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2321 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 2322 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 1 }, 2323 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 2 }, 2324 2325 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 1 }, 2326 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 1 }, 2327 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 4 }, 2328 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 4 }, 2329 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 1 }, 2330 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 1 }, 2331 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 1 }, 2332 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 1 }, 2333 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 3 }, 2334 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2335 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 2 }, 2336 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 12 }, 2337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 22 }, 2338 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 4 }, 2339 2340 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 1 }, 2341 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 1 }, 2342 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 1 }, 2343 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 1 }, 2344 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 2 }, 2345 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 2 }, 2346 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 1 }, 2347 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 1 }, 2348 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, 2349 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 1 }, 2350 2351 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 1 }, 2352 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2353 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 1 }, 2354 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 }, 2355 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 2 }, 2356 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 2 }, 2357 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 1 }, 2358 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 1 }, 2359 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 4 }, 2360 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 4 }, 2361 }; 2362 2363 static const TypeConversionCostTblEntry SSE2ConversionTbl[] = { 2364 // These are somewhat magic numbers justified by comparing the 2365 // output of llvm-mca for our various supported scheduler models 2366 // and basing it off the worst case scenario. 2367 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2368 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2369 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 3 }, 2370 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 3 }, 2371 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 3 }, 2372 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2373 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 3 }, 2374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2375 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 3 }, 2376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4 }, 2377 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 8 }, 2378 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 8 }, 2379 2380 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 3 }, 2381 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 3 }, 2382 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 8 }, 2383 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 9 }, 2384 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 4 }, 2385 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 4 }, 2386 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 4 }, 2387 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 4 }, 2388 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 7 }, 2389 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 7 }, 2390 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 5 }, 2391 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 15 }, 2392 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 18 }, 2393 2394 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 4 }, 2395 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 4 }, 2396 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 4 }, 2397 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 4 }, 2398 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v4f32, 6 }, 2399 { ISD::FP_TO_SINT, MVT::v16i8, MVT::v2f64, 6 }, 2400 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v4f32, 5 }, 2401 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v2f64, 5 }, 2402 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 4 }, 2403 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v2f64, 4 }, 2404 2405 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 4 }, 2406 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 }, 2407 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 4 }, 2408 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 15 }, 2409 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v4f32, 6 }, 2410 { ISD::FP_TO_UINT, MVT::v16i8, MVT::v2f64, 6 }, 2411 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v4f32, 5 }, 2412 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v2f64, 5 }, 2413 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 8 }, 2414 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v2f64, 8 }, 2415 2416 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2417 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v16i8, 4 }, 2418 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v16i8, 2 }, 2419 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v16i8, 3 }, 2420 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v16i8, 1 }, 2421 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v16i8, 2 }, 2422 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v8i16, 2 }, 2423 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v8i16, 3 }, 2424 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v8i16, 1 }, 2425 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v8i16, 2 }, 2426 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v4i32, 1 }, 2427 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v4i32, 2 }, 2428 2429 // These truncates are really widening elements. 2430 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 1 }, // PSHUFD 2431 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 2 }, // PUNPCKLWD+DQ 2432 { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // PUNPCKLBW+WD+PSHUFD 2433 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 1 }, // PUNPCKLWD 2434 { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 2 }, // PUNPCKLBW+WD 2435 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 1 }, // PUNPCKLBW 2436 2437 { ISD::TRUNCATE, MVT::v16i8, MVT::v8i16, 2 }, // PAND+PACKUSWB 2438 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, 2439 { ISD::TRUNCATE, MVT::v16i8, MVT::v4i32, 3 }, // PAND+2*PACKUSWB 2440 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 7 }, 2441 { ISD::TRUNCATE, MVT::v2i16, MVT::v2i32, 1 }, 2442 { ISD::TRUNCATE, MVT::v8i16, MVT::v4i32, 3 }, 2443 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 }, 2444 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32,10 }, 2445 { ISD::TRUNCATE, MVT::v16i8, MVT::v2i64, 4 }, // PAND+3*PACKUSWB 2446 { ISD::TRUNCATE, MVT::v8i16, MVT::v2i64, 2 }, // PSHUFD+PSHUFLW 2447 { ISD::TRUNCATE, MVT::v4i32, MVT::v2i64, 1 }, // PSHUFD 2448 }; 2449 2450 // Attempt to map directly to (simple) MVT types to let us match custom entries. 2451 EVT SrcTy = TLI->getValueType(DL, Src); 2452 EVT DstTy = TLI->getValueType(DL, Dst); 2453 2454 // The function getSimpleVT only handles simple value types. 2455 if (SrcTy.isSimple() && DstTy.isSimple()) { 2456 MVT SimpleSrcTy = SrcTy.getSimpleVT(); 2457 MVT SimpleDstTy = DstTy.getSimpleVT(); 2458 2459 if (ST->useAVX512Regs()) { 2460 if (ST->hasBWI()) 2461 if (const auto *Entry = ConvertCostTableLookup( 2462 AVX512BWConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2463 return AdjustCost(Entry->Cost); 2464 2465 if (ST->hasDQI()) 2466 if (const auto *Entry = ConvertCostTableLookup( 2467 AVX512DQConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2468 return AdjustCost(Entry->Cost); 2469 2470 if (ST->hasAVX512()) 2471 if (const auto *Entry = ConvertCostTableLookup( 2472 AVX512FConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2473 return AdjustCost(Entry->Cost); 2474 } 2475 2476 if (ST->hasBWI()) 2477 if (const auto *Entry = ConvertCostTableLookup( 2478 AVX512BWVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2479 return AdjustCost(Entry->Cost); 2480 2481 if (ST->hasDQI()) 2482 if (const auto *Entry = ConvertCostTableLookup( 2483 AVX512DQVLConversionTbl, ISD, SimpleDstTy, SimpleSrcTy)) 2484 return AdjustCost(Entry->Cost); 2485 2486 if (ST->hasAVX512()) 2487 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2488 SimpleDstTy, SimpleSrcTy)) 2489 return AdjustCost(Entry->Cost); 2490 2491 if (ST->hasAVX2()) { 2492 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2493 SimpleDstTy, SimpleSrcTy)) 2494 return AdjustCost(Entry->Cost); 2495 } 2496 2497 if (ST->hasAVX()) { 2498 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2499 SimpleDstTy, SimpleSrcTy)) 2500 return AdjustCost(Entry->Cost); 2501 } 2502 2503 if (ST->hasSSE41()) { 2504 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2505 SimpleDstTy, SimpleSrcTy)) 2506 return AdjustCost(Entry->Cost); 2507 } 2508 2509 if (ST->hasSSE2()) { 2510 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2511 SimpleDstTy, SimpleSrcTy)) 2512 return AdjustCost(Entry->Cost); 2513 } 2514 } 2515 2516 // Fall back to legalized types. 2517 std::pair<InstructionCost, MVT> LTSrc = TLI->getTypeLegalizationCost(DL, Src); 2518 std::pair<InstructionCost, MVT> LTDest = 2519 TLI->getTypeLegalizationCost(DL, Dst); 2520 2521 // If we're truncating to the same legalized type - just assume its free. 2522 if (ISD == ISD::TRUNCATE && LTSrc.second == LTDest.second) 2523 return TTI::TCC_Free; 2524 2525 if (ST->useAVX512Regs()) { 2526 if (ST->hasBWI()) 2527 if (const auto *Entry = ConvertCostTableLookup( 2528 AVX512BWConversionTbl, ISD, LTDest.second, LTSrc.second)) 2529 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2530 2531 if (ST->hasDQI()) 2532 if (const auto *Entry = ConvertCostTableLookup( 2533 AVX512DQConversionTbl, ISD, LTDest.second, LTSrc.second)) 2534 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2535 2536 if (ST->hasAVX512()) 2537 if (const auto *Entry = ConvertCostTableLookup( 2538 AVX512FConversionTbl, ISD, LTDest.second, LTSrc.second)) 2539 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2540 } 2541 2542 if (ST->hasBWI()) 2543 if (const auto *Entry = ConvertCostTableLookup(AVX512BWVLConversionTbl, ISD, 2544 LTDest.second, LTSrc.second)) 2545 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2546 2547 if (ST->hasDQI()) 2548 if (const auto *Entry = ConvertCostTableLookup(AVX512DQVLConversionTbl, ISD, 2549 LTDest.second, LTSrc.second)) 2550 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2551 2552 if (ST->hasAVX512()) 2553 if (const auto *Entry = ConvertCostTableLookup(AVX512VLConversionTbl, ISD, 2554 LTDest.second, LTSrc.second)) 2555 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2556 2557 if (ST->hasAVX2()) 2558 if (const auto *Entry = ConvertCostTableLookup(AVX2ConversionTbl, ISD, 2559 LTDest.second, LTSrc.second)) 2560 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2561 2562 if (ST->hasAVX()) 2563 if (const auto *Entry = ConvertCostTableLookup(AVXConversionTbl, ISD, 2564 LTDest.second, LTSrc.second)) 2565 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2566 2567 if (ST->hasSSE41()) 2568 if (const auto *Entry = ConvertCostTableLookup(SSE41ConversionTbl, ISD, 2569 LTDest.second, LTSrc.second)) 2570 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2571 2572 if (ST->hasSSE2()) 2573 if (const auto *Entry = ConvertCostTableLookup(SSE2ConversionTbl, ISD, 2574 LTDest.second, LTSrc.second)) 2575 return AdjustCost(std::max(LTSrc.first, LTDest.first) * Entry->Cost); 2576 2577 // Fallback, for i8/i16 sitofp/uitofp cases we need to extend to i32 for 2578 // sitofp. 2579 if ((ISD == ISD::SINT_TO_FP || ISD == ISD::UINT_TO_FP) && 2580 1 < Src->getScalarSizeInBits() && Src->getScalarSizeInBits() < 32) { 2581 Type *ExtSrc = Src->getWithNewBitWidth(32); 2582 unsigned ExtOpc = 2583 (ISD == ISD::SINT_TO_FP) ? Instruction::SExt : Instruction::ZExt; 2584 2585 // For scalar loads the extend would be free. 2586 InstructionCost ExtCost = 0; 2587 if (!(Src->isIntegerTy() && I && isa<LoadInst>(I->getOperand(0)))) 2588 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); 2589 2590 return ExtCost + getCastInstrCost(Instruction::SIToFP, Dst, ExtSrc, 2591 TTI::CastContextHint::None, CostKind); 2592 } 2593 2594 // Fallback for fptosi/fptoui i8/i16 cases we need to truncate from fptosi 2595 // i32. 2596 if ((ISD == ISD::FP_TO_SINT || ISD == ISD::FP_TO_UINT) && 2597 1 < Dst->getScalarSizeInBits() && Dst->getScalarSizeInBits() < 32) { 2598 Type *TruncDst = Dst->getWithNewBitWidth(32); 2599 return getCastInstrCost(Instruction::FPToSI, TruncDst, Src, CCH, CostKind) + 2600 getCastInstrCost(Instruction::Trunc, Dst, TruncDst, 2601 TTI::CastContextHint::None, CostKind); 2602 } 2603 2604 return AdjustCost( 2605 BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I)); 2606 } 2607 2608 InstructionCost X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 2609 Type *CondTy, 2610 CmpInst::Predicate VecPred, 2611 TTI::TargetCostKind CostKind, 2612 const Instruction *I) { 2613 // TODO: Handle other cost kinds. 2614 if (CostKind != TTI::TCK_RecipThroughput) 2615 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, 2616 I); 2617 2618 // Legalize the type. 2619 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 2620 2621 MVT MTy = LT.second; 2622 2623 int ISD = TLI->InstructionOpcodeToISD(Opcode); 2624 assert(ISD && "Invalid opcode"); 2625 2626 unsigned ExtraCost = 0; 2627 if (Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) { 2628 // Some vector comparison predicates cost extra instructions. 2629 // TODO: Should we invert this and assume worst case cmp costs 2630 // and reduce for particular predicates? 2631 if (MTy.isVector() && 2632 !((ST->hasXOP() && (!ST->hasAVX2() || MTy.is128BitVector())) || 2633 (ST->hasAVX512() && 32 <= MTy.getScalarSizeInBits()) || 2634 ST->hasBWI())) { 2635 // Fallback to I if a specific predicate wasn't specified. 2636 CmpInst::Predicate Pred = VecPred; 2637 if (I && (Pred == CmpInst::BAD_ICMP_PREDICATE || 2638 Pred == CmpInst::BAD_FCMP_PREDICATE)) 2639 Pred = cast<CmpInst>(I)->getPredicate(); 2640 2641 switch (Pred) { 2642 case CmpInst::Predicate::ICMP_NE: 2643 // xor(cmpeq(x,y),-1) 2644 ExtraCost = 1; 2645 break; 2646 case CmpInst::Predicate::ICMP_SGE: 2647 case CmpInst::Predicate::ICMP_SLE: 2648 // xor(cmpgt(x,y),-1) 2649 ExtraCost = 1; 2650 break; 2651 case CmpInst::Predicate::ICMP_ULT: 2652 case CmpInst::Predicate::ICMP_UGT: 2653 // cmpgt(xor(x,signbit),xor(y,signbit)) 2654 // xor(cmpeq(pmaxu(x,y),x),-1) 2655 ExtraCost = 2; 2656 break; 2657 case CmpInst::Predicate::ICMP_ULE: 2658 case CmpInst::Predicate::ICMP_UGE: 2659 if ((ST->hasSSE41() && MTy.getScalarSizeInBits() == 32) || 2660 (ST->hasSSE2() && MTy.getScalarSizeInBits() < 32)) { 2661 // cmpeq(psubus(x,y),0) 2662 // cmpeq(pminu(x,y),x) 2663 ExtraCost = 1; 2664 } else { 2665 // xor(cmpgt(xor(x,signbit),xor(y,signbit)),-1) 2666 ExtraCost = 3; 2667 } 2668 break; 2669 case CmpInst::Predicate::BAD_ICMP_PREDICATE: 2670 case CmpInst::Predicate::BAD_FCMP_PREDICATE: 2671 // Assume worst case scenario and add the maximum extra cost. 2672 ExtraCost = 3; 2673 break; 2674 default: 2675 break; 2676 } 2677 } 2678 } 2679 2680 static const CostTblEntry SLMCostTbl[] = { 2681 // slm pcmpeq/pcmpgt throughput is 2 2682 { ISD::SETCC, MVT::v2i64, 2 }, 2683 }; 2684 2685 static const CostTblEntry AVX512BWCostTbl[] = { 2686 { ISD::SETCC, MVT::v32i16, 1 }, 2687 { ISD::SETCC, MVT::v64i8, 1 }, 2688 2689 { ISD::SELECT, MVT::v32i16, 1 }, 2690 { ISD::SELECT, MVT::v64i8, 1 }, 2691 }; 2692 2693 static const CostTblEntry AVX512CostTbl[] = { 2694 { ISD::SETCC, MVT::v8i64, 1 }, 2695 { ISD::SETCC, MVT::v16i32, 1 }, 2696 { ISD::SETCC, MVT::v8f64, 1 }, 2697 { ISD::SETCC, MVT::v16f32, 1 }, 2698 2699 { ISD::SELECT, MVT::v8i64, 1 }, 2700 { ISD::SELECT, MVT::v16i32, 1 }, 2701 { ISD::SELECT, MVT::v8f64, 1 }, 2702 { ISD::SELECT, MVT::v16f32, 1 }, 2703 2704 { ISD::SETCC, MVT::v32i16, 2 }, // FIXME: should probably be 4 2705 { ISD::SETCC, MVT::v64i8, 2 }, // FIXME: should probably be 4 2706 2707 { ISD::SELECT, MVT::v32i16, 2 }, 2708 { ISD::SELECT, MVT::v64i8, 2 }, 2709 }; 2710 2711 static const CostTblEntry AVX2CostTbl[] = { 2712 { ISD::SETCC, MVT::v4i64, 1 }, 2713 { ISD::SETCC, MVT::v8i32, 1 }, 2714 { ISD::SETCC, MVT::v16i16, 1 }, 2715 { ISD::SETCC, MVT::v32i8, 1 }, 2716 2717 { ISD::SELECT, MVT::v4i64, 1 }, // pblendvb 2718 { ISD::SELECT, MVT::v8i32, 1 }, // pblendvb 2719 { ISD::SELECT, MVT::v16i16, 1 }, // pblendvb 2720 { ISD::SELECT, MVT::v32i8, 1 }, // pblendvb 2721 }; 2722 2723 static const CostTblEntry AVX1CostTbl[] = { 2724 { ISD::SETCC, MVT::v4f64, 1 }, 2725 { ISD::SETCC, MVT::v8f32, 1 }, 2726 // AVX1 does not support 8-wide integer compare. 2727 { ISD::SETCC, MVT::v4i64, 4 }, 2728 { ISD::SETCC, MVT::v8i32, 4 }, 2729 { ISD::SETCC, MVT::v16i16, 4 }, 2730 { ISD::SETCC, MVT::v32i8, 4 }, 2731 2732 { ISD::SELECT, MVT::v4f64, 1 }, // vblendvpd 2733 { ISD::SELECT, MVT::v8f32, 1 }, // vblendvps 2734 { ISD::SELECT, MVT::v4i64, 1 }, // vblendvpd 2735 { ISD::SELECT, MVT::v8i32, 1 }, // vblendvps 2736 { ISD::SELECT, MVT::v16i16, 2 }, // vandps + vandnps + vorps 2737 { ISD::SELECT, MVT::v32i8, 2 }, // vandps + vandnps + vorps 2738 }; 2739 2740 static const CostTblEntry SSE42CostTbl[] = { 2741 { ISD::SETCC, MVT::v2f64, 1 }, 2742 { ISD::SETCC, MVT::v4f32, 1 }, 2743 { ISD::SETCC, MVT::v2i64, 1 }, 2744 }; 2745 2746 static const CostTblEntry SSE41CostTbl[] = { 2747 { ISD::SELECT, MVT::v2f64, 1 }, // blendvpd 2748 { ISD::SELECT, MVT::v4f32, 1 }, // blendvps 2749 { ISD::SELECT, MVT::v2i64, 1 }, // pblendvb 2750 { ISD::SELECT, MVT::v4i32, 1 }, // pblendvb 2751 { ISD::SELECT, MVT::v8i16, 1 }, // pblendvb 2752 { ISD::SELECT, MVT::v16i8, 1 }, // pblendvb 2753 }; 2754 2755 static const CostTblEntry SSE2CostTbl[] = { 2756 { ISD::SETCC, MVT::v2f64, 2 }, 2757 { ISD::SETCC, MVT::f64, 1 }, 2758 { ISD::SETCC, MVT::v2i64, 5 }, // pcmpeqd/pcmpgtd expansion 2759 { ISD::SETCC, MVT::v4i32, 1 }, 2760 { ISD::SETCC, MVT::v8i16, 1 }, 2761 { ISD::SETCC, MVT::v16i8, 1 }, 2762 2763 { ISD::SELECT, MVT::v2f64, 2 }, // andpd + andnpd + orpd 2764 { ISD::SELECT, MVT::v2i64, 2 }, // pand + pandn + por 2765 { ISD::SELECT, MVT::v4i32, 2 }, // pand + pandn + por 2766 { ISD::SELECT, MVT::v8i16, 2 }, // pand + pandn + por 2767 { ISD::SELECT, MVT::v16i8, 2 }, // pand + pandn + por 2768 }; 2769 2770 static const CostTblEntry SSE1CostTbl[] = { 2771 { ISD::SETCC, MVT::v4f32, 2 }, 2772 { ISD::SETCC, MVT::f32, 1 }, 2773 2774 { ISD::SELECT, MVT::v4f32, 2 }, // andps + andnps + orps 2775 }; 2776 2777 if (ST->useSLMArithCosts()) 2778 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 2779 return LT.first * (ExtraCost + Entry->Cost); 2780 2781 if (ST->hasBWI()) 2782 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 2783 return LT.first * (ExtraCost + Entry->Cost); 2784 2785 if (ST->hasAVX512()) 2786 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 2787 return LT.first * (ExtraCost + Entry->Cost); 2788 2789 if (ST->hasAVX2()) 2790 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 2791 return LT.first * (ExtraCost + Entry->Cost); 2792 2793 if (ST->hasAVX()) 2794 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 2795 return LT.first * (ExtraCost + Entry->Cost); 2796 2797 if (ST->hasSSE42()) 2798 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 2799 return LT.first * (ExtraCost + Entry->Cost); 2800 2801 if (ST->hasSSE41()) 2802 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 2803 return LT.first * (ExtraCost + Entry->Cost); 2804 2805 if (ST->hasSSE2()) 2806 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 2807 return LT.first * (ExtraCost + Entry->Cost); 2808 2809 if (ST->hasSSE1()) 2810 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 2811 return LT.first * (ExtraCost + Entry->Cost); 2812 2813 return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I); 2814 } 2815 2816 unsigned X86TTIImpl::getAtomicMemIntrinsicMaxElementSize() const { return 16; } 2817 2818 InstructionCost 2819 X86TTIImpl::getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 2820 TTI::TargetCostKind CostKind) { 2821 2822 // Costs should match the codegen from: 2823 // BITREVERSE: llvm\test\CodeGen\X86\vector-bitreverse.ll 2824 // BSWAP: llvm\test\CodeGen\X86\bswap-vector.ll 2825 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll 2826 // CTPOP: llvm\test\CodeGen\X86\vector-popcnt-*.ll 2827 // CTTZ: llvm\test\CodeGen\X86\vector-tzcnt-*.ll 2828 2829 // TODO: Overflow intrinsics (*ADDO, *SUBO, *MULO) with vector types are not 2830 // specialized in these tables yet. 2831 static const CostTblEntry AVX512BITALGCostTbl[] = { 2832 { ISD::CTPOP, MVT::v32i16, 1 }, 2833 { ISD::CTPOP, MVT::v64i8, 1 }, 2834 { ISD::CTPOP, MVT::v16i16, 1 }, 2835 { ISD::CTPOP, MVT::v32i8, 1 }, 2836 { ISD::CTPOP, MVT::v8i16, 1 }, 2837 { ISD::CTPOP, MVT::v16i8, 1 }, 2838 }; 2839 static const CostTblEntry AVX512VPOPCNTDQCostTbl[] = { 2840 { ISD::CTPOP, MVT::v8i64, 1 }, 2841 { ISD::CTPOP, MVT::v16i32, 1 }, 2842 { ISD::CTPOP, MVT::v4i64, 1 }, 2843 { ISD::CTPOP, MVT::v8i32, 1 }, 2844 { ISD::CTPOP, MVT::v2i64, 1 }, 2845 { ISD::CTPOP, MVT::v4i32, 1 }, 2846 }; 2847 static const CostTblEntry AVX512CDCostTbl[] = { 2848 { ISD::CTLZ, MVT::v8i64, 1 }, 2849 { ISD::CTLZ, MVT::v16i32, 1 }, 2850 { ISD::CTLZ, MVT::v32i16, 8 }, 2851 { ISD::CTLZ, MVT::v64i8, 20 }, 2852 { ISD::CTLZ, MVT::v4i64, 1 }, 2853 { ISD::CTLZ, MVT::v8i32, 1 }, 2854 { ISD::CTLZ, MVT::v16i16, 4 }, 2855 { ISD::CTLZ, MVT::v32i8, 10 }, 2856 { ISD::CTLZ, MVT::v2i64, 1 }, 2857 { ISD::CTLZ, MVT::v4i32, 1 }, 2858 { ISD::CTLZ, MVT::v8i16, 4 }, 2859 { ISD::CTLZ, MVT::v16i8, 4 }, 2860 }; 2861 static const CostTblEntry AVX512BWCostTbl[] = { 2862 { ISD::ABS, MVT::v32i16, 1 }, 2863 { ISD::ABS, MVT::v64i8, 1 }, 2864 { ISD::BITREVERSE, MVT::v8i64, 3 }, 2865 { ISD::BITREVERSE, MVT::v16i32, 3 }, 2866 { ISD::BITREVERSE, MVT::v32i16, 3 }, 2867 { ISD::BITREVERSE, MVT::v64i8, 2 }, 2868 { ISD::BSWAP, MVT::v8i64, 1 }, 2869 { ISD::BSWAP, MVT::v16i32, 1 }, 2870 { ISD::BSWAP, MVT::v32i16, 1 }, 2871 { ISD::CTLZ, MVT::v8i64, 23 }, 2872 { ISD::CTLZ, MVT::v16i32, 22 }, 2873 { ISD::CTLZ, MVT::v32i16, 18 }, 2874 { ISD::CTLZ, MVT::v64i8, 17 }, 2875 { ISD::CTPOP, MVT::v8i64, 7 }, 2876 { ISD::CTPOP, MVT::v16i32, 11 }, 2877 { ISD::CTPOP, MVT::v32i16, 9 }, 2878 { ISD::CTPOP, MVT::v64i8, 6 }, 2879 { ISD::CTTZ, MVT::v8i64, 10 }, 2880 { ISD::CTTZ, MVT::v16i32, 14 }, 2881 { ISD::CTTZ, MVT::v32i16, 12 }, 2882 { ISD::CTTZ, MVT::v64i8, 9 }, 2883 { ISD::SADDSAT, MVT::v32i16, 1 }, 2884 { ISD::SADDSAT, MVT::v64i8, 1 }, 2885 { ISD::SMAX, MVT::v32i16, 1 }, 2886 { ISD::SMAX, MVT::v64i8, 1 }, 2887 { ISD::SMIN, MVT::v32i16, 1 }, 2888 { ISD::SMIN, MVT::v64i8, 1 }, 2889 { ISD::SSUBSAT, MVT::v32i16, 1 }, 2890 { ISD::SSUBSAT, MVT::v64i8, 1 }, 2891 { ISD::UADDSAT, MVT::v32i16, 1 }, 2892 { ISD::UADDSAT, MVT::v64i8, 1 }, 2893 { ISD::UMAX, MVT::v32i16, 1 }, 2894 { ISD::UMAX, MVT::v64i8, 1 }, 2895 { ISD::UMIN, MVT::v32i16, 1 }, 2896 { ISD::UMIN, MVT::v64i8, 1 }, 2897 { ISD::USUBSAT, MVT::v32i16, 1 }, 2898 { ISD::USUBSAT, MVT::v64i8, 1 }, 2899 }; 2900 static const CostTblEntry AVX512CostTbl[] = { 2901 { ISD::ABS, MVT::v8i64, 1 }, 2902 { ISD::ABS, MVT::v16i32, 1 }, 2903 { ISD::ABS, MVT::v32i16, 2 }, 2904 { ISD::ABS, MVT::v64i8, 2 }, 2905 { ISD::ABS, MVT::v4i64, 1 }, 2906 { ISD::ABS, MVT::v2i64, 1 }, 2907 { ISD::BITREVERSE, MVT::v8i64, 36 }, 2908 { ISD::BITREVERSE, MVT::v16i32, 24 }, 2909 { ISD::BITREVERSE, MVT::v32i16, 10 }, 2910 { ISD::BITREVERSE, MVT::v64i8, 10 }, 2911 { ISD::BSWAP, MVT::v8i64, 4 }, 2912 { ISD::BSWAP, MVT::v16i32, 4 }, 2913 { ISD::BSWAP, MVT::v32i16, 4 }, 2914 { ISD::CTLZ, MVT::v8i64, 29 }, 2915 { ISD::CTLZ, MVT::v16i32, 35 }, 2916 { ISD::CTLZ, MVT::v32i16, 28 }, 2917 { ISD::CTLZ, MVT::v64i8, 18 }, 2918 { ISD::CTPOP, MVT::v8i64, 16 }, 2919 { ISD::CTPOP, MVT::v16i32, 24 }, 2920 { ISD::CTPOP, MVT::v32i16, 18 }, 2921 { ISD::CTPOP, MVT::v64i8, 12 }, 2922 { ISD::CTTZ, MVT::v8i64, 20 }, 2923 { ISD::CTTZ, MVT::v16i32, 28 }, 2924 { ISD::CTTZ, MVT::v32i16, 24 }, 2925 { ISD::CTTZ, MVT::v64i8, 18 }, 2926 { ISD::SMAX, MVT::v8i64, 1 }, 2927 { ISD::SMAX, MVT::v16i32, 1 }, 2928 { ISD::SMAX, MVT::v32i16, 2 }, 2929 { ISD::SMAX, MVT::v64i8, 2 }, 2930 { ISD::SMAX, MVT::v4i64, 1 }, 2931 { ISD::SMAX, MVT::v2i64, 1 }, 2932 { ISD::SMIN, MVT::v8i64, 1 }, 2933 { ISD::SMIN, MVT::v16i32, 1 }, 2934 { ISD::SMIN, MVT::v32i16, 2 }, 2935 { ISD::SMIN, MVT::v64i8, 2 }, 2936 { ISD::SMIN, MVT::v4i64, 1 }, 2937 { ISD::SMIN, MVT::v2i64, 1 }, 2938 { ISD::UMAX, MVT::v8i64, 1 }, 2939 { ISD::UMAX, MVT::v16i32, 1 }, 2940 { ISD::UMAX, MVT::v32i16, 2 }, 2941 { ISD::UMAX, MVT::v64i8, 2 }, 2942 { ISD::UMAX, MVT::v4i64, 1 }, 2943 { ISD::UMAX, MVT::v2i64, 1 }, 2944 { ISD::UMIN, MVT::v8i64, 1 }, 2945 { ISD::UMIN, MVT::v16i32, 1 }, 2946 { ISD::UMIN, MVT::v32i16, 2 }, 2947 { ISD::UMIN, MVT::v64i8, 2 }, 2948 { ISD::UMIN, MVT::v4i64, 1 }, 2949 { ISD::UMIN, MVT::v2i64, 1 }, 2950 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd 2951 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq 2952 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq 2953 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq 2954 { ISD::UADDSAT, MVT::v16i32, 3 }, // not + pminud + paddd 2955 { ISD::UADDSAT, MVT::v2i64, 3 }, // not + pminuq + paddq 2956 { ISD::UADDSAT, MVT::v4i64, 3 }, // not + pminuq + paddq 2957 { ISD::UADDSAT, MVT::v8i64, 3 }, // not + pminuq + paddq 2958 { ISD::SADDSAT, MVT::v32i16, 2 }, 2959 { ISD::SADDSAT, MVT::v64i8, 2 }, 2960 { ISD::SSUBSAT, MVT::v32i16, 2 }, 2961 { ISD::SSUBSAT, MVT::v64i8, 2 }, 2962 { ISD::UADDSAT, MVT::v32i16, 2 }, 2963 { ISD::UADDSAT, MVT::v64i8, 2 }, 2964 { ISD::USUBSAT, MVT::v32i16, 2 }, 2965 { ISD::USUBSAT, MVT::v64i8, 2 }, 2966 { ISD::FMAXNUM, MVT::f32, 2 }, 2967 { ISD::FMAXNUM, MVT::v4f32, 2 }, 2968 { ISD::FMAXNUM, MVT::v8f32, 2 }, 2969 { ISD::FMAXNUM, MVT::v16f32, 2 }, 2970 { ISD::FMAXNUM, MVT::f64, 2 }, 2971 { ISD::FMAXNUM, MVT::v2f64, 2 }, 2972 { ISD::FMAXNUM, MVT::v4f64, 2 }, 2973 { ISD::FMAXNUM, MVT::v8f64, 2 }, 2974 }; 2975 static const CostTblEntry XOPCostTbl[] = { 2976 { ISD::BITREVERSE, MVT::v4i64, 4 }, 2977 { ISD::BITREVERSE, MVT::v8i32, 4 }, 2978 { ISD::BITREVERSE, MVT::v16i16, 4 }, 2979 { ISD::BITREVERSE, MVT::v32i8, 4 }, 2980 { ISD::BITREVERSE, MVT::v2i64, 1 }, 2981 { ISD::BITREVERSE, MVT::v4i32, 1 }, 2982 { ISD::BITREVERSE, MVT::v8i16, 1 }, 2983 { ISD::BITREVERSE, MVT::v16i8, 1 }, 2984 { ISD::BITREVERSE, MVT::i64, 3 }, 2985 { ISD::BITREVERSE, MVT::i32, 3 }, 2986 { ISD::BITREVERSE, MVT::i16, 3 }, 2987 { ISD::BITREVERSE, MVT::i8, 3 } 2988 }; 2989 static const CostTblEntry AVX2CostTbl[] = { 2990 { ISD::ABS, MVT::v4i64, 2 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 2991 { ISD::ABS, MVT::v8i32, 1 }, 2992 { ISD::ABS, MVT::v16i16, 1 }, 2993 { ISD::ABS, MVT::v32i8, 1 }, 2994 { ISD::BITREVERSE, MVT::v2i64, 3 }, 2995 { ISD::BITREVERSE, MVT::v4i64, 3 }, 2996 { ISD::BITREVERSE, MVT::v4i32, 3 }, 2997 { ISD::BITREVERSE, MVT::v8i32, 3 }, 2998 { ISD::BITREVERSE, MVT::v8i16, 3 }, 2999 { ISD::BITREVERSE, MVT::v16i16, 3 }, 3000 { ISD::BITREVERSE, MVT::v16i8, 3 }, 3001 { ISD::BITREVERSE, MVT::v32i8, 3 }, 3002 { ISD::BSWAP, MVT::v4i64, 1 }, 3003 { ISD::BSWAP, MVT::v8i32, 1 }, 3004 { ISD::BSWAP, MVT::v16i16, 1 }, 3005 { ISD::CTLZ, MVT::v2i64, 7 }, 3006 { ISD::CTLZ, MVT::v4i64, 7 }, 3007 { ISD::CTLZ, MVT::v4i32, 5 }, 3008 { ISD::CTLZ, MVT::v8i32, 5 }, 3009 { ISD::CTLZ, MVT::v8i16, 4 }, 3010 { ISD::CTLZ, MVT::v16i16, 4 }, 3011 { ISD::CTLZ, MVT::v16i8, 3 }, 3012 { ISD::CTLZ, MVT::v32i8, 3 }, 3013 { ISD::CTPOP, MVT::v2i64, 3 }, 3014 { ISD::CTPOP, MVT::v4i64, 3 }, 3015 { ISD::CTPOP, MVT::v4i32, 7 }, 3016 { ISD::CTPOP, MVT::v8i32, 7 }, 3017 { ISD::CTPOP, MVT::v8i16, 3 }, 3018 { ISD::CTPOP, MVT::v16i16, 3 }, 3019 { ISD::CTPOP, MVT::v16i8, 2 }, 3020 { ISD::CTPOP, MVT::v32i8, 2 }, 3021 { ISD::CTTZ, MVT::v2i64, 4 }, 3022 { ISD::CTTZ, MVT::v4i64, 4 }, 3023 { ISD::CTTZ, MVT::v4i32, 7 }, 3024 { ISD::CTTZ, MVT::v8i32, 7 }, 3025 { ISD::CTTZ, MVT::v8i16, 4 }, 3026 { ISD::CTTZ, MVT::v16i16, 4 }, 3027 { ISD::CTTZ, MVT::v16i8, 3 }, 3028 { ISD::CTTZ, MVT::v32i8, 3 }, 3029 { ISD::SADDSAT, MVT::v16i16, 1 }, 3030 { ISD::SADDSAT, MVT::v32i8, 1 }, 3031 { ISD::SMAX, MVT::v8i32, 1 }, 3032 { ISD::SMAX, MVT::v16i16, 1 }, 3033 { ISD::SMAX, MVT::v32i8, 1 }, 3034 { ISD::SMIN, MVT::v8i32, 1 }, 3035 { ISD::SMIN, MVT::v16i16, 1 }, 3036 { ISD::SMIN, MVT::v32i8, 1 }, 3037 { ISD::SSUBSAT, MVT::v16i16, 1 }, 3038 { ISD::SSUBSAT, MVT::v32i8, 1 }, 3039 { ISD::UADDSAT, MVT::v16i16, 1 }, 3040 { ISD::UADDSAT, MVT::v32i8, 1 }, 3041 { ISD::UADDSAT, MVT::v8i32, 3 }, // not + pminud + paddd 3042 { ISD::UMAX, MVT::v8i32, 1 }, 3043 { ISD::UMAX, MVT::v16i16, 1 }, 3044 { ISD::UMAX, MVT::v32i8, 1 }, 3045 { ISD::UMIN, MVT::v8i32, 1 }, 3046 { ISD::UMIN, MVT::v16i16, 1 }, 3047 { ISD::UMIN, MVT::v32i8, 1 }, 3048 { ISD::USUBSAT, MVT::v16i16, 1 }, 3049 { ISD::USUBSAT, MVT::v32i8, 1 }, 3050 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd 3051 { ISD::FMAXNUM, MVT::v8f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3052 { ISD::FMAXNUM, MVT::v4f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3053 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ 3054 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ 3055 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ 3056 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/ 3057 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/ 3058 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/ 3059 }; 3060 static const CostTblEntry AVX1CostTbl[] = { 3061 { ISD::ABS, MVT::v4i64, 5 }, // VBLENDVPD(X,VPSUBQ(0,X),X) 3062 { ISD::ABS, MVT::v8i32, 3 }, 3063 { ISD::ABS, MVT::v16i16, 3 }, 3064 { ISD::ABS, MVT::v32i8, 3 }, 3065 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert 3066 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert 3067 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert 3068 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert 3069 { ISD::BSWAP, MVT::v4i64, 4 }, 3070 { ISD::BSWAP, MVT::v8i32, 4 }, 3071 { ISD::BSWAP, MVT::v16i16, 4 }, 3072 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert 3073 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert 3074 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert 3075 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3076 { ISD::CTPOP, MVT::v4i64, 16 }, // 2 x 128-bit Op + extract/insert 3077 { ISD::CTPOP, MVT::v8i32, 24 }, // 2 x 128-bit Op + extract/insert 3078 { ISD::CTPOP, MVT::v16i16, 20 }, // 2 x 128-bit Op + extract/insert 3079 { ISD::CTPOP, MVT::v32i8, 14 }, // 2 x 128-bit Op + extract/insert 3080 { ISD::CTTZ, MVT::v4i64, 22 }, // 2 x 128-bit Op + extract/insert 3081 { ISD::CTTZ, MVT::v8i32, 30 }, // 2 x 128-bit Op + extract/insert 3082 { ISD::CTTZ, MVT::v16i16, 26 }, // 2 x 128-bit Op + extract/insert 3083 { ISD::CTTZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert 3084 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3085 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3086 { ISD::SMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3087 { ISD::SMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3088 { ISD::SMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3089 { ISD::SMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3090 { ISD::SMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3091 { ISD::SMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3092 { ISD::SSUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3093 { ISD::SSUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3094 { ISD::UADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3095 { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3096 { ISD::UADDSAT, MVT::v8i32, 8 }, // 2 x 128-bit Op + extract/insert 3097 { ISD::UMAX, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3098 { ISD::UMAX, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3099 { ISD::UMAX, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3100 { ISD::UMIN, MVT::v8i32, 4 }, // 2 x 128-bit Op + extract/insert 3101 { ISD::UMIN, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3102 { ISD::UMIN, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3103 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert 3104 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert 3105 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert 3106 { ISD::FMAXNUM, MVT::f32, 3 }, // MAXSS + CMPUNORDSS + BLENDVPS 3107 { ISD::FMAXNUM, MVT::v4f32, 3 }, // MAXPS + CMPUNORDPS + BLENDVPS 3108 { ISD::FMAXNUM, MVT::v8f32, 5 }, // MAXPS + CMPUNORDPS + BLENDVPS + ? 3109 { ISD::FMAXNUM, MVT::f64, 3 }, // MAXSD + CMPUNORDSD + BLENDVPD 3110 { ISD::FMAXNUM, MVT::v2f64, 3 }, // MAXPD + CMPUNORDPD + BLENDVPD 3111 { ISD::FMAXNUM, MVT::v4f64, 5 }, // MAXPD + CMPUNORDPD + BLENDVPD + ? 3112 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ 3113 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ 3114 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ 3115 { ISD::FSQRT, MVT::f64, 21 }, // SNB from http://www.agner.org/ 3116 { ISD::FSQRT, MVT::v2f64, 21 }, // SNB from http://www.agner.org/ 3117 { ISD::FSQRT, MVT::v4f64, 43 }, // SNB from http://www.agner.org/ 3118 }; 3119 static const CostTblEntry GLMCostTbl[] = { 3120 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss 3121 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps 3122 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd 3123 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd 3124 }; 3125 static const CostTblEntry SLMCostTbl[] = { 3126 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss 3127 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps 3128 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd 3129 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd 3130 }; 3131 static const CostTblEntry SSE42CostTbl[] = { 3132 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd 3133 { ISD::UADDSAT, MVT::v4i32, 3 }, // not + pminud + paddd 3134 { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ 3135 { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ 3136 }; 3137 static const CostTblEntry SSE41CostTbl[] = { 3138 { ISD::ABS, MVT::v2i64, 2 }, // BLENDVPD(X,PSUBQ(0,X),X) 3139 { ISD::SMAX, MVT::v4i32, 1 }, 3140 { ISD::SMAX, MVT::v16i8, 1 }, 3141 { ISD::SMIN, MVT::v4i32, 1 }, 3142 { ISD::SMIN, MVT::v16i8, 1 }, 3143 { ISD::UMAX, MVT::v4i32, 1 }, 3144 { ISD::UMAX, MVT::v8i16, 1 }, 3145 { ISD::UMIN, MVT::v4i32, 1 }, 3146 { ISD::UMIN, MVT::v8i16, 1 }, 3147 }; 3148 static const CostTblEntry SSSE3CostTbl[] = { 3149 { ISD::ABS, MVT::v4i32, 1 }, 3150 { ISD::ABS, MVT::v8i16, 1 }, 3151 { ISD::ABS, MVT::v16i8, 1 }, 3152 { ISD::BITREVERSE, MVT::v2i64, 5 }, 3153 { ISD::BITREVERSE, MVT::v4i32, 5 }, 3154 { ISD::BITREVERSE, MVT::v8i16, 5 }, 3155 { ISD::BITREVERSE, MVT::v16i8, 5 }, 3156 { ISD::BSWAP, MVT::v2i64, 1 }, 3157 { ISD::BSWAP, MVT::v4i32, 1 }, 3158 { ISD::BSWAP, MVT::v8i16, 1 }, 3159 { ISD::CTLZ, MVT::v2i64, 23 }, 3160 { ISD::CTLZ, MVT::v4i32, 18 }, 3161 { ISD::CTLZ, MVT::v8i16, 14 }, 3162 { ISD::CTLZ, MVT::v16i8, 9 }, 3163 { ISD::CTPOP, MVT::v2i64, 7 }, 3164 { ISD::CTPOP, MVT::v4i32, 11 }, 3165 { ISD::CTPOP, MVT::v8i16, 9 }, 3166 { ISD::CTPOP, MVT::v16i8, 6 }, 3167 { ISD::CTTZ, MVT::v2i64, 10 }, 3168 { ISD::CTTZ, MVT::v4i32, 14 }, 3169 { ISD::CTTZ, MVT::v8i16, 12 }, 3170 { ISD::CTTZ, MVT::v16i8, 9 } 3171 }; 3172 static const CostTblEntry SSE2CostTbl[] = { 3173 { ISD::ABS, MVT::v2i64, 4 }, 3174 { ISD::ABS, MVT::v4i32, 3 }, 3175 { ISD::ABS, MVT::v8i16, 2 }, 3176 { ISD::ABS, MVT::v16i8, 2 }, 3177 { ISD::BITREVERSE, MVT::v2i64, 29 }, 3178 { ISD::BITREVERSE, MVT::v4i32, 27 }, 3179 { ISD::BITREVERSE, MVT::v8i16, 27 }, 3180 { ISD::BITREVERSE, MVT::v16i8, 20 }, 3181 { ISD::BSWAP, MVT::v2i64, 7 }, 3182 { ISD::BSWAP, MVT::v4i32, 7 }, 3183 { ISD::BSWAP, MVT::v8i16, 7 }, 3184 { ISD::CTLZ, MVT::v2i64, 25 }, 3185 { ISD::CTLZ, MVT::v4i32, 26 }, 3186 { ISD::CTLZ, MVT::v8i16, 20 }, 3187 { ISD::CTLZ, MVT::v16i8, 17 }, 3188 { ISD::CTPOP, MVT::v2i64, 12 }, 3189 { ISD::CTPOP, MVT::v4i32, 15 }, 3190 { ISD::CTPOP, MVT::v8i16, 13 }, 3191 { ISD::CTPOP, MVT::v16i8, 10 }, 3192 { ISD::CTTZ, MVT::v2i64, 14 }, 3193 { ISD::CTTZ, MVT::v4i32, 18 }, 3194 { ISD::CTTZ, MVT::v8i16, 16 }, 3195 { ISD::CTTZ, MVT::v16i8, 13 }, 3196 { ISD::SADDSAT, MVT::v8i16, 1 }, 3197 { ISD::SADDSAT, MVT::v16i8, 1 }, 3198 { ISD::SMAX, MVT::v8i16, 1 }, 3199 { ISD::SMIN, MVT::v8i16, 1 }, 3200 { ISD::SSUBSAT, MVT::v8i16, 1 }, 3201 { ISD::SSUBSAT, MVT::v16i8, 1 }, 3202 { ISD::UADDSAT, MVT::v8i16, 1 }, 3203 { ISD::UADDSAT, MVT::v16i8, 1 }, 3204 { ISD::UMAX, MVT::v8i16, 2 }, 3205 { ISD::UMAX, MVT::v16i8, 1 }, 3206 { ISD::UMIN, MVT::v8i16, 2 }, 3207 { ISD::UMIN, MVT::v16i8, 1 }, 3208 { ISD::USUBSAT, MVT::v8i16, 1 }, 3209 { ISD::USUBSAT, MVT::v16i8, 1 }, 3210 { ISD::FMAXNUM, MVT::f64, 4 }, 3211 { ISD::FMAXNUM, MVT::v2f64, 4 }, 3212 { ISD::FSQRT, MVT::f64, 32 }, // Nehalem from http://www.agner.org/ 3213 { ISD::FSQRT, MVT::v2f64, 32 }, // Nehalem from http://www.agner.org/ 3214 }; 3215 static const CostTblEntry SSE1CostTbl[] = { 3216 { ISD::FMAXNUM, MVT::f32, 4 }, 3217 { ISD::FMAXNUM, MVT::v4f32, 4 }, 3218 { ISD::FSQRT, MVT::f32, 28 }, // Pentium III from http://www.agner.org/ 3219 { ISD::FSQRT, MVT::v4f32, 56 }, // Pentium III from http://www.agner.org/ 3220 }; 3221 static const CostTblEntry BMI64CostTbl[] = { // 64-bit targets 3222 { ISD::CTTZ, MVT::i64, 1 }, 3223 }; 3224 static const CostTblEntry BMI32CostTbl[] = { // 32 or 64-bit targets 3225 { ISD::CTTZ, MVT::i32, 1 }, 3226 { ISD::CTTZ, MVT::i16, 1 }, 3227 { ISD::CTTZ, MVT::i8, 1 }, 3228 }; 3229 static const CostTblEntry LZCNT64CostTbl[] = { // 64-bit targets 3230 { ISD::CTLZ, MVT::i64, 1 }, 3231 }; 3232 static const CostTblEntry LZCNT32CostTbl[] = { // 32 or 64-bit targets 3233 { ISD::CTLZ, MVT::i32, 1 }, 3234 { ISD::CTLZ, MVT::i16, 1 }, 3235 { ISD::CTLZ, MVT::i8, 1 }, 3236 }; 3237 static const CostTblEntry POPCNT64CostTbl[] = { // 64-bit targets 3238 { ISD::CTPOP, MVT::i64, 1 }, 3239 }; 3240 static const CostTblEntry POPCNT32CostTbl[] = { // 32 or 64-bit targets 3241 { ISD::CTPOP, MVT::i32, 1 }, 3242 { ISD::CTPOP, MVT::i16, 1 }, 3243 { ISD::CTPOP, MVT::i8, 1 }, 3244 }; 3245 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3246 { ISD::ABS, MVT::i64, 2 }, // SUB+CMOV 3247 { ISD::BITREVERSE, MVT::i64, 14 }, 3248 { ISD::BSWAP, MVT::i64, 1 }, 3249 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV 3250 { ISD::CTTZ, MVT::i64, 3 }, // TEST+BSF+CMOV/BRANCH 3251 { ISD::CTPOP, MVT::i64, 10 }, 3252 { ISD::SADDO, MVT::i64, 1 }, 3253 { ISD::UADDO, MVT::i64, 1 }, 3254 { ISD::UMULO, MVT::i64, 2 }, // mulq + seto 3255 }; 3256 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3257 { ISD::ABS, MVT::i32, 2 }, // SUB+CMOV 3258 { ISD::ABS, MVT::i16, 2 }, // SUB+CMOV 3259 { ISD::BITREVERSE, MVT::i32, 14 }, 3260 { ISD::BITREVERSE, MVT::i16, 14 }, 3261 { ISD::BITREVERSE, MVT::i8, 11 }, 3262 { ISD::BSWAP, MVT::i32, 1 }, 3263 { ISD::BSWAP, MVT::i16, 1 }, // ROL 3264 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV 3265 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV 3266 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV 3267 { ISD::CTTZ, MVT::i32, 3 }, // TEST+BSF+CMOV/BRANCH 3268 { ISD::CTTZ, MVT::i16, 3 }, // TEST+BSF+CMOV/BRANCH 3269 { ISD::CTTZ, MVT::i8, 3 }, // TEST+BSF+CMOV/BRANCH 3270 { ISD::CTPOP, MVT::i32, 8 }, 3271 { ISD::CTPOP, MVT::i16, 9 }, 3272 { ISD::CTPOP, MVT::i8, 7 }, 3273 { ISD::SADDO, MVT::i32, 1 }, 3274 { ISD::SADDO, MVT::i16, 1 }, 3275 { ISD::SADDO, MVT::i8, 1 }, 3276 { ISD::UADDO, MVT::i32, 1 }, 3277 { ISD::UADDO, MVT::i16, 1 }, 3278 { ISD::UADDO, MVT::i8, 1 }, 3279 { ISD::UMULO, MVT::i32, 2 }, // mul + seto 3280 { ISD::UMULO, MVT::i16, 2 }, 3281 { ISD::UMULO, MVT::i8, 2 }, 3282 }; 3283 3284 Type *RetTy = ICA.getReturnType(); 3285 Type *OpTy = RetTy; 3286 Intrinsic::ID IID = ICA.getID(); 3287 unsigned ISD = ISD::DELETED_NODE; 3288 switch (IID) { 3289 default: 3290 break; 3291 case Intrinsic::abs: 3292 ISD = ISD::ABS; 3293 break; 3294 case Intrinsic::bitreverse: 3295 ISD = ISD::BITREVERSE; 3296 break; 3297 case Intrinsic::bswap: 3298 ISD = ISD::BSWAP; 3299 break; 3300 case Intrinsic::ctlz: 3301 ISD = ISD::CTLZ; 3302 break; 3303 case Intrinsic::ctpop: 3304 ISD = ISD::CTPOP; 3305 break; 3306 case Intrinsic::cttz: 3307 ISD = ISD::CTTZ; 3308 break; 3309 case Intrinsic::maxnum: 3310 case Intrinsic::minnum: 3311 // FMINNUM has same costs so don't duplicate. 3312 ISD = ISD::FMAXNUM; 3313 break; 3314 case Intrinsic::sadd_sat: 3315 ISD = ISD::SADDSAT; 3316 break; 3317 case Intrinsic::smax: 3318 ISD = ISD::SMAX; 3319 break; 3320 case Intrinsic::smin: 3321 ISD = ISD::SMIN; 3322 break; 3323 case Intrinsic::ssub_sat: 3324 ISD = ISD::SSUBSAT; 3325 break; 3326 case Intrinsic::uadd_sat: 3327 ISD = ISD::UADDSAT; 3328 break; 3329 case Intrinsic::umax: 3330 ISD = ISD::UMAX; 3331 break; 3332 case Intrinsic::umin: 3333 ISD = ISD::UMIN; 3334 break; 3335 case Intrinsic::usub_sat: 3336 ISD = ISD::USUBSAT; 3337 break; 3338 case Intrinsic::sqrt: 3339 ISD = ISD::FSQRT; 3340 break; 3341 case Intrinsic::sadd_with_overflow: 3342 case Intrinsic::ssub_with_overflow: 3343 // SSUBO has same costs so don't duplicate. 3344 ISD = ISD::SADDO; 3345 OpTy = RetTy->getContainedType(0); 3346 break; 3347 case Intrinsic::uadd_with_overflow: 3348 case Intrinsic::usub_with_overflow: 3349 // USUBO has same costs so don't duplicate. 3350 ISD = ISD::UADDO; 3351 OpTy = RetTy->getContainedType(0); 3352 break; 3353 case Intrinsic::umul_with_overflow: 3354 case Intrinsic::smul_with_overflow: 3355 // SMULO has same costs so don't duplicate. 3356 ISD = ISD::UMULO; 3357 OpTy = RetTy->getContainedType(0); 3358 break; 3359 } 3360 3361 if (ISD != ISD::DELETED_NODE) { 3362 // Legalize the type. 3363 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, OpTy); 3364 MVT MTy = LT.second; 3365 3366 // Attempt to lookup cost. 3367 if (ISD == ISD::BITREVERSE && ST->hasGFNI() && ST->hasSSSE3() && 3368 MTy.isVector()) { 3369 // With PSHUFB the code is very similar for all types. If we have integer 3370 // byte operations, we just need a GF2P8AFFINEQB for vXi8. For other types 3371 // we also need a PSHUFB. 3372 unsigned Cost = MTy.getVectorElementType() == MVT::i8 ? 1 : 2; 3373 3374 // Without byte operations, we need twice as many GF2P8AFFINEQB and PSHUFB 3375 // instructions. We also need an extract and an insert. 3376 if (!(MTy.is128BitVector() || (ST->hasAVX2() && MTy.is256BitVector()) || 3377 (ST->hasBWI() && MTy.is512BitVector()))) 3378 Cost = Cost * 2 + 2; 3379 3380 return LT.first * Cost; 3381 } 3382 3383 auto adjustTableCost = [](const CostTblEntry &Entry, 3384 InstructionCost LegalizationCost, 3385 FastMathFlags FMF) { 3386 // If there are no NANs to deal with, then these are reduced to a 3387 // single MIN** or MAX** instruction instead of the MIN/CMP/SELECT that we 3388 // assume is used in the non-fast case. 3389 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { 3390 if (FMF.noNaNs()) 3391 return LegalizationCost * 1; 3392 } 3393 return LegalizationCost * (int)Entry.Cost; 3394 }; 3395 3396 if (ST->useGLMDivSqrtCosts()) 3397 if (const auto *Entry = CostTableLookup(GLMCostTbl, ISD, MTy)) 3398 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3399 3400 if (ST->useSLMArithCosts()) 3401 if (const auto *Entry = CostTableLookup(SLMCostTbl, ISD, MTy)) 3402 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3403 3404 if (ST->hasBITALG()) 3405 if (const auto *Entry = CostTableLookup(AVX512BITALGCostTbl, ISD, MTy)) 3406 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3407 3408 if (ST->hasVPOPCNTDQ()) 3409 if (const auto *Entry = CostTableLookup(AVX512VPOPCNTDQCostTbl, ISD, MTy)) 3410 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3411 3412 if (ST->hasCDI()) 3413 if (const auto *Entry = CostTableLookup(AVX512CDCostTbl, ISD, MTy)) 3414 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3415 3416 if (ST->hasBWI()) 3417 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3418 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3419 3420 if (ST->hasAVX512()) 3421 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3422 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3423 3424 if (ST->hasXOP()) 3425 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3426 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3427 3428 if (ST->hasAVX2()) 3429 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 3430 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3431 3432 if (ST->hasAVX()) 3433 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 3434 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3435 3436 if (ST->hasSSE42()) 3437 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 3438 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3439 3440 if (ST->hasSSE41()) 3441 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 3442 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3443 3444 if (ST->hasSSSE3()) 3445 if (const auto *Entry = CostTableLookup(SSSE3CostTbl, ISD, MTy)) 3446 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3447 3448 if (ST->hasSSE2()) 3449 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 3450 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3451 3452 if (ST->hasSSE1()) 3453 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 3454 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3455 3456 if (ST->hasBMI()) { 3457 if (ST->is64Bit()) 3458 if (const auto *Entry = CostTableLookup(BMI64CostTbl, ISD, MTy)) 3459 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3460 3461 if (const auto *Entry = CostTableLookup(BMI32CostTbl, ISD, MTy)) 3462 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3463 } 3464 3465 if (ST->hasLZCNT()) { 3466 if (ST->is64Bit()) 3467 if (const auto *Entry = CostTableLookup(LZCNT64CostTbl, ISD, MTy)) 3468 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3469 3470 if (const auto *Entry = CostTableLookup(LZCNT32CostTbl, ISD, MTy)) 3471 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3472 } 3473 3474 if (ST->hasPOPCNT()) { 3475 if (ST->is64Bit()) 3476 if (const auto *Entry = CostTableLookup(POPCNT64CostTbl, ISD, MTy)) 3477 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3478 3479 if (const auto *Entry = CostTableLookup(POPCNT32CostTbl, ISD, MTy)) 3480 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3481 } 3482 3483 if (ISD == ISD::BSWAP && ST->hasMOVBE() && ST->hasFastMOVBE()) { 3484 if (const Instruction *II = ICA.getInst()) { 3485 if (II->hasOneUse() && isa<StoreInst>(II->user_back())) 3486 return TTI::TCC_Free; 3487 if (auto *LI = dyn_cast<LoadInst>(II->getOperand(0))) { 3488 if (LI->hasOneUse()) 3489 return TTI::TCC_Free; 3490 } 3491 } 3492 } 3493 3494 if (ST->is64Bit()) 3495 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3496 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3497 3498 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3499 return adjustTableCost(*Entry, LT.first, ICA.getFlags()); 3500 } 3501 3502 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3503 } 3504 3505 InstructionCost 3506 X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 3507 TTI::TargetCostKind CostKind) { 3508 if (ICA.isTypeBasedOnly()) 3509 return getTypeBasedIntrinsicInstrCost(ICA, CostKind); 3510 3511 static const CostTblEntry AVX512BWCostTbl[] = { 3512 { ISD::ROTL, MVT::v32i16, 2 }, 3513 { ISD::ROTL, MVT::v16i16, 2 }, 3514 { ISD::ROTL, MVT::v8i16, 2 }, 3515 { ISD::ROTL, MVT::v64i8, 5 }, 3516 { ISD::ROTL, MVT::v32i8, 5 }, 3517 { ISD::ROTL, MVT::v16i8, 5 }, 3518 { ISD::ROTR, MVT::v32i16, 2 }, 3519 { ISD::ROTR, MVT::v16i16, 2 }, 3520 { ISD::ROTR, MVT::v8i16, 2 }, 3521 { ISD::ROTR, MVT::v64i8, 5 }, 3522 { ISD::ROTR, MVT::v32i8, 5 }, 3523 { ISD::ROTR, MVT::v16i8, 5 } 3524 }; 3525 static const CostTblEntry AVX512CostTbl[] = { 3526 { ISD::ROTL, MVT::v8i64, 1 }, 3527 { ISD::ROTL, MVT::v4i64, 1 }, 3528 { ISD::ROTL, MVT::v2i64, 1 }, 3529 { ISD::ROTL, MVT::v16i32, 1 }, 3530 { ISD::ROTL, MVT::v8i32, 1 }, 3531 { ISD::ROTL, MVT::v4i32, 1 }, 3532 { ISD::ROTR, MVT::v8i64, 1 }, 3533 { ISD::ROTR, MVT::v4i64, 1 }, 3534 { ISD::ROTR, MVT::v2i64, 1 }, 3535 { ISD::ROTR, MVT::v16i32, 1 }, 3536 { ISD::ROTR, MVT::v8i32, 1 }, 3537 { ISD::ROTR, MVT::v4i32, 1 } 3538 }; 3539 // XOP: ROTL = VPROT(X,Y), ROTR = VPROT(X,SUB(0,Y)) 3540 static const CostTblEntry XOPCostTbl[] = { 3541 { ISD::ROTL, MVT::v4i64, 4 }, 3542 { ISD::ROTL, MVT::v8i32, 4 }, 3543 { ISD::ROTL, MVT::v16i16, 4 }, 3544 { ISD::ROTL, MVT::v32i8, 4 }, 3545 { ISD::ROTL, MVT::v2i64, 1 }, 3546 { ISD::ROTL, MVT::v4i32, 1 }, 3547 { ISD::ROTL, MVT::v8i16, 1 }, 3548 { ISD::ROTL, MVT::v16i8, 1 }, 3549 { ISD::ROTR, MVT::v4i64, 6 }, 3550 { ISD::ROTR, MVT::v8i32, 6 }, 3551 { ISD::ROTR, MVT::v16i16, 6 }, 3552 { ISD::ROTR, MVT::v32i8, 6 }, 3553 { ISD::ROTR, MVT::v2i64, 2 }, 3554 { ISD::ROTR, MVT::v4i32, 2 }, 3555 { ISD::ROTR, MVT::v8i16, 2 }, 3556 { ISD::ROTR, MVT::v16i8, 2 } 3557 }; 3558 static const CostTblEntry X64CostTbl[] = { // 64-bit targets 3559 { ISD::ROTL, MVT::i64, 1 }, 3560 { ISD::ROTR, MVT::i64, 1 }, 3561 { ISD::FSHL, MVT::i64, 4 } 3562 }; 3563 static const CostTblEntry X86CostTbl[] = { // 32 or 64-bit targets 3564 { ISD::ROTL, MVT::i32, 1 }, 3565 { ISD::ROTL, MVT::i16, 1 }, 3566 { ISD::ROTL, MVT::i8, 1 }, 3567 { ISD::ROTR, MVT::i32, 1 }, 3568 { ISD::ROTR, MVT::i16, 1 }, 3569 { ISD::ROTR, MVT::i8, 1 }, 3570 { ISD::FSHL, MVT::i32, 4 }, 3571 { ISD::FSHL, MVT::i16, 4 }, 3572 { ISD::FSHL, MVT::i8, 4 } 3573 }; 3574 3575 Intrinsic::ID IID = ICA.getID(); 3576 Type *RetTy = ICA.getReturnType(); 3577 const SmallVectorImpl<const Value *> &Args = ICA.getArgs(); 3578 unsigned ISD = ISD::DELETED_NODE; 3579 switch (IID) { 3580 default: 3581 break; 3582 case Intrinsic::fshl: 3583 ISD = ISD::FSHL; 3584 if (Args[0] == Args[1]) 3585 ISD = ISD::ROTL; 3586 break; 3587 case Intrinsic::fshr: 3588 // FSHR has same costs so don't duplicate. 3589 ISD = ISD::FSHL; 3590 if (Args[0] == Args[1]) 3591 ISD = ISD::ROTR; 3592 break; 3593 } 3594 3595 if (ISD != ISD::DELETED_NODE) { 3596 // Legalize the type. 3597 std::pair<InstructionCost, MVT> LT = 3598 TLI->getTypeLegalizationCost(DL, RetTy); 3599 MVT MTy = LT.second; 3600 3601 // Attempt to lookup cost. 3602 if (ST->hasBWI()) 3603 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 3604 return LT.first * Entry->Cost; 3605 3606 if (ST->hasAVX512()) 3607 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 3608 return LT.first * Entry->Cost; 3609 3610 if (ST->hasXOP()) 3611 if (const auto *Entry = CostTableLookup(XOPCostTbl, ISD, MTy)) 3612 return LT.first * Entry->Cost; 3613 3614 if (ST->is64Bit()) 3615 if (const auto *Entry = CostTableLookup(X64CostTbl, ISD, MTy)) 3616 return LT.first * Entry->Cost; 3617 3618 if (const auto *Entry = CostTableLookup(X86CostTbl, ISD, MTy)) 3619 return LT.first * Entry->Cost; 3620 } 3621 3622 return BaseT::getIntrinsicInstrCost(ICA, CostKind); 3623 } 3624 3625 InstructionCost X86TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, 3626 unsigned Index) { 3627 static const CostTblEntry SLMCostTbl[] = { 3628 { ISD::EXTRACT_VECTOR_ELT, MVT::i8, 4 }, 3629 { ISD::EXTRACT_VECTOR_ELT, MVT::i16, 4 }, 3630 { ISD::EXTRACT_VECTOR_ELT, MVT::i32, 4 }, 3631 { ISD::EXTRACT_VECTOR_ELT, MVT::i64, 7 } 3632 }; 3633 3634 assert(Val->isVectorTy() && "This must be a vector type"); 3635 Type *ScalarType = Val->getScalarType(); 3636 int RegisterFileMoveCost = 0; 3637 3638 // Non-immediate extraction/insertion can be handled as a sequence of 3639 // aliased loads+stores via the stack. 3640 if (Index == -1U && (Opcode == Instruction::ExtractElement || 3641 Opcode == Instruction::InsertElement)) { 3642 // TODO: On some SSE41+ targets, we expand to cmp+splat+select patterns: 3643 // inselt N0, N1, N2 --> select (SplatN2 == {0,1,2...}) ? SplatN1 : N0. 3644 3645 // TODO: Move this to BasicTTIImpl.h? We'd need better gep + index handling. 3646 assert(isa<FixedVectorType>(Val) && "Fixed vector type expected"); 3647 Align VecAlign = DL.getPrefTypeAlign(Val); 3648 Align SclAlign = DL.getPrefTypeAlign(ScalarType); 3649 3650 // Extract - store vector to stack, load scalar. 3651 if (Opcode == Instruction::ExtractElement) { 3652 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3653 TTI::TargetCostKind::TCK_RecipThroughput) + 3654 getMemoryOpCost(Instruction::Load, ScalarType, SclAlign, 0, 3655 TTI::TargetCostKind::TCK_RecipThroughput); 3656 } 3657 // Insert - store vector to stack, store scalar, load vector. 3658 if (Opcode == Instruction::InsertElement) { 3659 return getMemoryOpCost(Instruction::Store, Val, VecAlign, 0, 3660 TTI::TargetCostKind::TCK_RecipThroughput) + 3661 getMemoryOpCost(Instruction::Store, ScalarType, SclAlign, 0, 3662 TTI::TargetCostKind::TCK_RecipThroughput) + 3663 getMemoryOpCost(Instruction::Load, Val, VecAlign, 0, 3664 TTI::TargetCostKind::TCK_RecipThroughput); 3665 } 3666 } 3667 3668 if (Index != -1U && (Opcode == Instruction::ExtractElement || 3669 Opcode == Instruction::InsertElement)) { 3670 // Extraction of vXi1 elements are now efficiently handled by MOVMSK. 3671 if (Opcode == Instruction::ExtractElement && 3672 ScalarType->getScalarSizeInBits() == 1 && 3673 cast<FixedVectorType>(Val)->getNumElements() > 1) 3674 return 1; 3675 3676 // Legalize the type. 3677 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Val); 3678 3679 // This type is legalized to a scalar type. 3680 if (!LT.second.isVector()) 3681 return 0; 3682 3683 // The type may be split. Normalize the index to the new type. 3684 unsigned SizeInBits = LT.second.getSizeInBits(); 3685 unsigned NumElts = LT.second.getVectorNumElements(); 3686 unsigned SubNumElts = NumElts; 3687 Index = Index % NumElts; 3688 3689 // For >128-bit vectors, we need to extract higher 128-bit subvectors. 3690 // For inserts, we also need to insert the subvector back. 3691 if (SizeInBits > 128) { 3692 assert((SizeInBits % 128) == 0 && "Illegal vector"); 3693 unsigned NumSubVecs = SizeInBits / 128; 3694 SubNumElts = NumElts / NumSubVecs; 3695 if (SubNumElts <= Index) { 3696 RegisterFileMoveCost += (Opcode == Instruction::InsertElement ? 2 : 1); 3697 Index %= SubNumElts; 3698 } 3699 } 3700 3701 if (Index == 0) { 3702 // Floating point scalars are already located in index #0. 3703 // Many insertions to #0 can fold away for scalar fp-ops, so let's assume 3704 // true for all. 3705 if (ScalarType->isFloatingPointTy()) 3706 return RegisterFileMoveCost; 3707 3708 // Assume movd/movq XMM -> GPR is relatively cheap on all targets. 3709 if (ScalarType->isIntegerTy() && Opcode == Instruction::ExtractElement) 3710 return 1 + RegisterFileMoveCost; 3711 } 3712 3713 int ISD = TLI->InstructionOpcodeToISD(Opcode); 3714 assert(ISD && "Unexpected vector opcode"); 3715 MVT MScalarTy = LT.second.getScalarType(); 3716 if (ST->useSLMArithCosts()) 3717 if (auto *Entry = CostTableLookup(SLMCostTbl, ISD, MScalarTy)) 3718 return Entry->Cost + RegisterFileMoveCost; 3719 3720 // Assume pinsr/pextr XMM <-> GPR is relatively cheap on all targets. 3721 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3722 (MScalarTy.isInteger() && ST->hasSSE41())) 3723 return 1 + RegisterFileMoveCost; 3724 3725 // Assume insertps is relatively cheap on all targets. 3726 if (MScalarTy == MVT::f32 && ST->hasSSE41() && 3727 Opcode == Instruction::InsertElement) 3728 return 1 + RegisterFileMoveCost; 3729 3730 // For extractions we just need to shuffle the element to index 0, which 3731 // should be very cheap (assume cost = 1). For insertions we need to shuffle 3732 // the elements to its destination. In both cases we must handle the 3733 // subvector move(s). 3734 // If the vector type is already less than 128-bits then don't reduce it. 3735 // TODO: Under what circumstances should we shuffle using the full width? 3736 InstructionCost ShuffleCost = 1; 3737 if (Opcode == Instruction::InsertElement) { 3738 auto *SubTy = cast<VectorType>(Val); 3739 EVT VT = TLI->getValueType(DL, Val); 3740 if (VT.getScalarType() != MScalarTy || VT.getSizeInBits() >= 128) 3741 SubTy = FixedVectorType::get(ScalarType, SubNumElts); 3742 ShuffleCost = 3743 getShuffleCost(TTI::SK_PermuteTwoSrc, SubTy, None, 0, SubTy); 3744 } 3745 int IntOrFpCost = ScalarType->isFloatingPointTy() ? 0 : 1; 3746 return ShuffleCost + IntOrFpCost + RegisterFileMoveCost; 3747 } 3748 3749 // Add to the base cost if we know that the extracted element of a vector is 3750 // destined to be moved to and used in the integer register file. 3751 if (Opcode == Instruction::ExtractElement && ScalarType->isPointerTy()) 3752 RegisterFileMoveCost += 1; 3753 3754 return BaseT::getVectorInstrCost(Opcode, Val, Index) + RegisterFileMoveCost; 3755 } 3756 3757 InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty, 3758 const APInt &DemandedElts, 3759 bool Insert, 3760 bool Extract) { 3761 InstructionCost Cost = 0; 3762 3763 // For insertions, a ISD::BUILD_VECTOR style vector initialization can be much 3764 // cheaper than an accumulation of ISD::INSERT_VECTOR_ELT. 3765 if (Insert) { 3766 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 3767 MVT MScalarTy = LT.second.getScalarType(); 3768 unsigned SizeInBits = LT.second.getSizeInBits(); 3769 3770 if ((MScalarTy == MVT::i16 && ST->hasSSE2()) || 3771 (MScalarTy.isInteger() && ST->hasSSE41()) || 3772 (MScalarTy == MVT::f32 && ST->hasSSE41())) { 3773 // For types we can insert directly, insertion into 128-bit sub vectors is 3774 // cheap, followed by a cheap chain of concatenations. 3775 if (SizeInBits <= 128) { 3776 Cost += 3777 BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, false); 3778 } else { 3779 // In each 128-lane, if at least one index is demanded but not all 3780 // indices are demanded and this 128-lane is not the first 128-lane of 3781 // the legalized-vector, then this 128-lane needs a extracti128; If in 3782 // each 128-lane, there is at least one demanded index, this 128-lane 3783 // needs a inserti128. 3784 3785 // The following cases will help you build a better understanding: 3786 // Assume we insert several elements into a v8i32 vector in avx2, 3787 // Case#1: inserting into 1th index needs vpinsrd + inserti128. 3788 // Case#2: inserting into 5th index needs extracti128 + vpinsrd + 3789 // inserti128. 3790 // Case#3: inserting into 4,5,6,7 index needs 4*vpinsrd + inserti128. 3791 const int CostValue = *LT.first.getValue(); 3792 assert(CostValue >= 0 && "Negative cost!"); 3793 unsigned Num128Lanes = SizeInBits / 128 * CostValue; 3794 unsigned NumElts = LT.second.getVectorNumElements() * CostValue; 3795 APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); 3796 unsigned Scale = NumElts / Num128Lanes; 3797 // We iterate each 128-lane, and check if we need a 3798 // extracti128/inserti128 for this 128-lane. 3799 for (unsigned I = 0; I < NumElts; I += Scale) { 3800 APInt Mask = WidenedDemandedElts.getBitsSet(NumElts, I, I + Scale); 3801 APInt MaskedDE = Mask & WidenedDemandedElts; 3802 unsigned Population = MaskedDE.countPopulation(); 3803 Cost += (Population > 0 && Population != Scale && 3804 I % LT.second.getVectorNumElements() != 0); 3805 Cost += Population > 0; 3806 } 3807 Cost += DemandedElts.countPopulation(); 3808 3809 // For vXf32 cases, insertion into the 0'th index in each v4f32 3810 // 128-bit vector is free. 3811 // NOTE: This assumes legalization widens vXf32 vectors. 3812 if (MScalarTy == MVT::f32) 3813 for (unsigned i = 0, e = cast<FixedVectorType>(Ty)->getNumElements(); 3814 i < e; i += 4) 3815 if (DemandedElts[i]) 3816 Cost--; 3817 } 3818 } else if (LT.second.isVector()) { 3819 // Without fast insertion, we need to use MOVD/MOVQ to pass each demanded 3820 // integer element as a SCALAR_TO_VECTOR, then we build the vector as a 3821 // series of UNPCK followed by CONCAT_VECTORS - all of these can be 3822 // considered cheap. 3823 if (Ty->isIntOrIntVectorTy()) 3824 Cost += DemandedElts.countPopulation(); 3825 3826 // Get the smaller of the legalized or original pow2-extended number of 3827 // vector elements, which represents the number of unpacks we'll end up 3828 // performing. 3829 unsigned NumElts = LT.second.getVectorNumElements(); 3830 unsigned Pow2Elts = 3831 PowerOf2Ceil(cast<FixedVectorType>(Ty)->getNumElements()); 3832 Cost += (std::min<unsigned>(NumElts, Pow2Elts) - 1) * LT.first; 3833 } 3834 } 3835 3836 if (Extract) { 3837 // vXi1 can be efficiently extracted with MOVMSK. 3838 // TODO: AVX512 predicate mask handling. 3839 // NOTE: This doesn't work well for roundtrip scalarization. 3840 if (!Insert && Ty->getScalarSizeInBits() == 1 && !ST->hasAVX512()) { 3841 unsigned NumElts = cast<FixedVectorType>(Ty)->getNumElements(); 3842 unsigned MaxElts = ST->hasAVX2() ? 32 : 16; 3843 unsigned MOVMSKCost = (NumElts + MaxElts - 1) / MaxElts; 3844 return MOVMSKCost; 3845 } 3846 3847 // TODO: Use default extraction for now, but we should investigate extending 3848 // this to handle repeated subvector extraction. 3849 Cost += BaseT::getScalarizationOverhead(Ty, DemandedElts, false, Extract); 3850 } 3851 3852 return Cost; 3853 } 3854 3855 InstructionCost 3856 X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 3857 int VF, const APInt &DemandedDstElts, 3858 TTI::TargetCostKind CostKind) { 3859 const unsigned EltTyBits = DL.getTypeSizeInBits(EltTy); 3860 // We don't differentiate element types here, only element bit width. 3861 EltTy = IntegerType::getIntNTy(EltTy->getContext(), EltTyBits); 3862 3863 auto bailout = [&]() { 3864 return BaseT::getReplicationShuffleCost(EltTy, ReplicationFactor, VF, 3865 DemandedDstElts, CostKind); 3866 }; 3867 3868 // For now, only deal with AVX512 cases. 3869 if (!ST->hasAVX512()) 3870 return bailout(); 3871 3872 // Do we have a native shuffle for this element type, or should we promote? 3873 unsigned PromEltTyBits = EltTyBits; 3874 switch (EltTyBits) { 3875 case 32: 3876 case 64: 3877 break; // AVX512F. 3878 case 16: 3879 if (!ST->hasBWI()) 3880 PromEltTyBits = 32; // promote to i32, AVX512F. 3881 break; // AVX512BW 3882 case 8: 3883 if (!ST->hasVBMI()) 3884 PromEltTyBits = 32; // promote to i32, AVX512F. 3885 break; // AVX512VBMI 3886 case 1: 3887 // There is no support for shuffling i1 elements. We *must* promote. 3888 if (ST->hasBWI()) { 3889 if (ST->hasVBMI()) 3890 PromEltTyBits = 8; // promote to i8, AVX512VBMI. 3891 else 3892 PromEltTyBits = 16; // promote to i16, AVX512BW. 3893 break; 3894 } 3895 if (ST->hasDQI()) { 3896 PromEltTyBits = 32; // promote to i32, AVX512F. 3897 break; 3898 } 3899 return bailout(); 3900 default: 3901 return bailout(); 3902 } 3903 auto *PromEltTy = IntegerType::getIntNTy(EltTy->getContext(), PromEltTyBits); 3904 3905 auto *SrcVecTy = FixedVectorType::get(EltTy, VF); 3906 auto *PromSrcVecTy = FixedVectorType::get(PromEltTy, VF); 3907 3908 int NumDstElements = VF * ReplicationFactor; 3909 auto *PromDstVecTy = FixedVectorType::get(PromEltTy, NumDstElements); 3910 auto *DstVecTy = FixedVectorType::get(EltTy, NumDstElements); 3911 3912 // Legalize the types. 3913 MVT LegalSrcVecTy = TLI->getTypeLegalizationCost(DL, SrcVecTy).second; 3914 MVT LegalPromSrcVecTy = TLI->getTypeLegalizationCost(DL, PromSrcVecTy).second; 3915 MVT LegalPromDstVecTy = TLI->getTypeLegalizationCost(DL, PromDstVecTy).second; 3916 MVT LegalDstVecTy = TLI->getTypeLegalizationCost(DL, DstVecTy).second; 3917 // They should have legalized into vector types. 3918 if (!LegalSrcVecTy.isVector() || !LegalPromSrcVecTy.isVector() || 3919 !LegalPromDstVecTy.isVector() || !LegalDstVecTy.isVector()) 3920 return bailout(); 3921 3922 if (PromEltTyBits != EltTyBits) { 3923 // If we have to perform the shuffle with wider elt type than our data type, 3924 // then we will first need to anyext (we don't care about the new bits) 3925 // the source elements, and then truncate Dst elements. 3926 InstructionCost PromotionCost; 3927 PromotionCost += getCastInstrCost( 3928 Instruction::SExt, /*Dst=*/PromSrcVecTy, /*Src=*/SrcVecTy, 3929 TargetTransformInfo::CastContextHint::None, CostKind); 3930 PromotionCost += 3931 getCastInstrCost(Instruction::Trunc, /*Dst=*/DstVecTy, 3932 /*Src=*/PromDstVecTy, 3933 TargetTransformInfo::CastContextHint::None, CostKind); 3934 return PromotionCost + getReplicationShuffleCost(PromEltTy, 3935 ReplicationFactor, VF, 3936 DemandedDstElts, CostKind); 3937 } 3938 3939 assert(LegalSrcVecTy.getScalarSizeInBits() == EltTyBits && 3940 LegalSrcVecTy.getScalarType() == LegalDstVecTy.getScalarType() && 3941 "We expect that the legalization doesn't affect the element width, " 3942 "doesn't coalesce/split elements."); 3943 3944 unsigned NumEltsPerDstVec = LegalDstVecTy.getVectorNumElements(); 3945 unsigned NumDstVectors = 3946 divideCeil(DstVecTy->getNumElements(), NumEltsPerDstVec); 3947 3948 auto *SingleDstVecTy = FixedVectorType::get(EltTy, NumEltsPerDstVec); 3949 3950 // Not all the produced Dst elements may be demanded. In our case, 3951 // given that a single Dst vector is formed by a single shuffle, 3952 // if all elements that will form a single Dst vector aren't demanded, 3953 // then we won't need to do that shuffle, so adjust the cost accordingly. 3954 APInt DemandedDstVectors = APIntOps::ScaleBitMask( 3955 DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), 3956 NumDstVectors); 3957 unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); 3958 3959 InstructionCost SingleShuffleCost = 3960 getShuffleCost(TTI::SK_PermuteSingleSrc, SingleDstVecTy, 3961 /*Mask=*/None, /*Index=*/0, /*SubTp=*/nullptr); 3962 return NumDstVectorsDemanded * SingleShuffleCost; 3963 } 3964 3965 InstructionCost X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, 3966 MaybeAlign Alignment, 3967 unsigned AddressSpace, 3968 TTI::TargetCostKind CostKind, 3969 const Instruction *I) { 3970 // TODO: Handle other cost kinds. 3971 if (CostKind != TTI::TCK_RecipThroughput) { 3972 if (auto *SI = dyn_cast_or_null<StoreInst>(I)) { 3973 // Store instruction with index and scale costs 2 Uops. 3974 // Check the preceding GEP to identify non-const indices. 3975 if (auto *GEP = dyn_cast<GetElementPtrInst>(SI->getPointerOperand())) { 3976 if (!all_of(GEP->indices(), [](Value *V) { return isa<Constant>(V); })) 3977 return TTI::TCC_Basic * 2; 3978 } 3979 } 3980 return TTI::TCC_Basic; 3981 } 3982 3983 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 3984 "Invalid Opcode"); 3985 // Type legalization can't handle structs 3986 if (TLI->getValueType(DL, Src, true) == MVT::Other) 3987 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 3988 CostKind); 3989 3990 // Legalize the type. 3991 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); 3992 3993 auto *VTy = dyn_cast<FixedVectorType>(Src); 3994 3995 // Handle the simple case of non-vectors. 3996 // NOTE: this assumes that legalization never creates vector from scalars! 3997 if (!VTy || !LT.second.isVector()) 3998 // Each load/store unit costs 1. 3999 return LT.first * 1; 4000 4001 bool IsLoad = Opcode == Instruction::Load; 4002 4003 Type *EltTy = VTy->getElementType(); 4004 4005 const int EltTyBits = DL.getTypeSizeInBits(EltTy); 4006 4007 InstructionCost Cost = 0; 4008 4009 // Source of truth: how many elements were there in the original IR vector? 4010 const unsigned SrcNumElt = VTy->getNumElements(); 4011 4012 // How far have we gotten? 4013 int NumEltRemaining = SrcNumElt; 4014 // Note that we intentionally capture by-reference, NumEltRemaining changes. 4015 auto NumEltDone = [&]() { return SrcNumElt - NumEltRemaining; }; 4016 4017 const int MaxLegalOpSizeBytes = divideCeil(LT.second.getSizeInBits(), 8); 4018 4019 // Note that even if we can store 64 bits of an XMM, we still operate on XMM. 4020 const unsigned XMMBits = 128; 4021 if (XMMBits % EltTyBits != 0) 4022 // Vector size must be a multiple of the element size. I.e. no padding. 4023 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4024 CostKind); 4025 const int NumEltPerXMM = XMMBits / EltTyBits; 4026 4027 auto *XMMVecTy = FixedVectorType::get(EltTy, NumEltPerXMM); 4028 4029 for (int CurrOpSizeBytes = MaxLegalOpSizeBytes, SubVecEltsLeft = 0; 4030 NumEltRemaining > 0; CurrOpSizeBytes /= 2) { 4031 // How many elements would a single op deal with at once? 4032 if ((8 * CurrOpSizeBytes) % EltTyBits != 0) 4033 // Vector size must be a multiple of the element size. I.e. no padding. 4034 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, 4035 CostKind); 4036 int CurrNumEltPerOp = (8 * CurrOpSizeBytes) / EltTyBits; 4037 4038 assert(CurrOpSizeBytes > 0 && CurrNumEltPerOp > 0 && "How'd we get here?"); 4039 assert((((NumEltRemaining * EltTyBits) < (2 * 8 * CurrOpSizeBytes)) || 4040 (CurrOpSizeBytes == MaxLegalOpSizeBytes)) && 4041 "Unless we haven't halved the op size yet, " 4042 "we have less than two op's sized units of work left."); 4043 4044 auto *CurrVecTy = CurrNumEltPerOp > NumEltPerXMM 4045 ? FixedVectorType::get(EltTy, CurrNumEltPerOp) 4046 : XMMVecTy; 4047 4048 assert(CurrVecTy->getNumElements() % CurrNumEltPerOp == 0 && 4049 "After halving sizes, the vector elt count is no longer a multiple " 4050 "of number of elements per operation?"); 4051 auto *CoalescedVecTy = 4052 CurrNumEltPerOp == 1 4053 ? CurrVecTy 4054 : FixedVectorType::get( 4055 IntegerType::get(Src->getContext(), 4056 EltTyBits * CurrNumEltPerOp), 4057 CurrVecTy->getNumElements() / CurrNumEltPerOp); 4058 assert(DL.getTypeSizeInBits(CoalescedVecTy) == 4059 DL.getTypeSizeInBits(CurrVecTy) && 4060 "coalesciing elements doesn't change vector width."); 4061 4062 while (NumEltRemaining > 0) { 4063 assert(SubVecEltsLeft >= 0 && "Subreg element count overconsumtion?"); 4064 4065 // Can we use this vector size, as per the remaining element count? 4066 // Iff the vector is naturally aligned, we can do a wide load regardless. 4067 if (NumEltRemaining < CurrNumEltPerOp && 4068 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) && 4069 CurrOpSizeBytes != 1) 4070 break; // Try smalled vector size. 4071 4072 bool Is0thSubVec = (NumEltDone() % LT.second.getVectorNumElements()) == 0; 4073 4074 // If we have fully processed the previous reg, we need to replenish it. 4075 if (SubVecEltsLeft == 0) { 4076 SubVecEltsLeft += CurrVecTy->getNumElements(); 4077 // And that's free only for the 0'th subvector of a legalized vector. 4078 if (!Is0thSubVec) 4079 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector 4080 : TTI::ShuffleKind::SK_ExtractSubvector, 4081 VTy, None, NumEltDone(), CurrVecTy); 4082 } 4083 4084 // While we can directly load/store ZMM, YMM, and 64-bit halves of XMM, 4085 // for smaller widths (32/16/8) we have to insert/extract them separately. 4086 // Again, it's free for the 0'th subreg (if op is 32/64 bit wide, 4087 // but let's pretend that it is also true for 16/8 bit wide ops...) 4088 if (CurrOpSizeBytes <= 32 / 8 && !Is0thSubVec) { 4089 int NumEltDoneInCurrXMM = NumEltDone() % NumEltPerXMM; 4090 assert(NumEltDoneInCurrXMM % CurrNumEltPerOp == 0 && ""); 4091 int CoalescedVecEltIdx = NumEltDoneInCurrXMM / CurrNumEltPerOp; 4092 APInt DemandedElts = 4093 APInt::getBitsSet(CoalescedVecTy->getNumElements(), 4094 CoalescedVecEltIdx, CoalescedVecEltIdx + 1); 4095 assert(DemandedElts.countPopulation() == 1 && "Inserting single value"); 4096 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad, 4097 !IsLoad); 4098 } 4099 4100 // This isn't exactly right. We're using slow unaligned 32-byte accesses 4101 // as a proxy for a double-pumped AVX memory interface such as on 4102 // Sandybridge. 4103 if (CurrOpSizeBytes == 32 && ST->isUnalignedMem32Slow()) 4104 Cost += 2; 4105 else 4106 Cost += 1; 4107 4108 SubVecEltsLeft -= CurrNumEltPerOp; 4109 NumEltRemaining -= CurrNumEltPerOp; 4110 Alignment = commonAlignment(Alignment.valueOrOne(), CurrOpSizeBytes); 4111 } 4112 } 4113 4114 assert(NumEltRemaining <= 0 && "Should have processed all the elements."); 4115 4116 return Cost; 4117 } 4118 4119 InstructionCost 4120 X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, Align Alignment, 4121 unsigned AddressSpace, 4122 TTI::TargetCostKind CostKind) { 4123 bool IsLoad = (Instruction::Load == Opcode); 4124 bool IsStore = (Instruction::Store == Opcode); 4125 4126 auto *SrcVTy = dyn_cast<FixedVectorType>(SrcTy); 4127 if (!SrcVTy) 4128 // To calculate scalar take the regular cost, without mask 4129 return getMemoryOpCost(Opcode, SrcTy, Alignment, AddressSpace, CostKind); 4130 4131 unsigned NumElem = SrcVTy->getNumElements(); 4132 auto *MaskTy = 4133 FixedVectorType::get(Type::getInt8Ty(SrcVTy->getContext()), NumElem); 4134 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || 4135 (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { 4136 // Scalarization 4137 APInt DemandedElts = APInt::getAllOnes(NumElem); 4138 InstructionCost MaskSplitCost = 4139 getScalarizationOverhead(MaskTy, DemandedElts, false, true); 4140 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 4141 Instruction::ICmp, Type::getInt8Ty(SrcVTy->getContext()), nullptr, 4142 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4143 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 4144 InstructionCost MaskCmpCost = NumElem * (BranchCost + ScalarCompareCost); 4145 InstructionCost ValueSplitCost = 4146 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore); 4147 InstructionCost MemopCost = 4148 NumElem * BaseT::getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 4149 Alignment, AddressSpace, CostKind); 4150 return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost; 4151 } 4152 4153 // Legalize the type. 4154 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, SrcVTy); 4155 auto VT = TLI->getValueType(DL, SrcVTy); 4156 InstructionCost Cost = 0; 4157 if (VT.isSimple() && LT.second != VT.getSimpleVT() && 4158 LT.second.getVectorNumElements() == NumElem) 4159 // Promotion requires extend/truncate for data and a shuffle for mask. 4160 Cost += getShuffleCost(TTI::SK_PermuteTwoSrc, SrcVTy, None, 0, nullptr) + 4161 getShuffleCost(TTI::SK_PermuteTwoSrc, MaskTy, None, 0, nullptr); 4162 4163 else if (LT.first * LT.second.getVectorNumElements() > NumElem) { 4164 auto *NewMaskTy = FixedVectorType::get(MaskTy->getElementType(), 4165 LT.second.getVectorNumElements()); 4166 // Expanding requires fill mask with zeroes 4167 Cost += getShuffleCost(TTI::SK_InsertSubvector, NewMaskTy, None, 0, MaskTy); 4168 } 4169 4170 // Pre-AVX512 - each maskmov load costs 2 + store costs ~8. 4171 if (!ST->hasAVX512()) 4172 return Cost + LT.first * (IsLoad ? 2 : 8); 4173 4174 // AVX-512 masked load/store is cheapper 4175 return Cost + LT.first; 4176 } 4177 4178 InstructionCost X86TTIImpl::getAddressComputationCost(Type *Ty, 4179 ScalarEvolution *SE, 4180 const SCEV *Ptr) { 4181 // Address computations in vectorized code with non-consecutive addresses will 4182 // likely result in more instructions compared to scalar code where the 4183 // computation can more often be merged into the index mode. The resulting 4184 // extra micro-ops can significantly decrease throughput. 4185 const unsigned NumVectorInstToHideOverhead = 10; 4186 4187 // Cost modeling of Strided Access Computation is hidden by the indexing 4188 // modes of X86 regardless of the stride value. We dont believe that there 4189 // is a difference between constant strided access in gerenal and constant 4190 // strided value which is less than or equal to 64. 4191 // Even in the case of (loop invariant) stride whose value is not known at 4192 // compile time, the address computation will not incur more than one extra 4193 // ADD instruction. 4194 if (Ty->isVectorTy() && SE && !ST->hasAVX2()) { 4195 // TODO: AVX2 is the current cut-off because we don't have correct 4196 // interleaving costs for prior ISA's. 4197 if (!BaseT::isStridedAccess(Ptr)) 4198 return NumVectorInstToHideOverhead; 4199 if (!BaseT::getConstantStrideStep(SE, Ptr)) 4200 return 1; 4201 } 4202 4203 return BaseT::getAddressComputationCost(Ty, SE, Ptr); 4204 } 4205 4206 InstructionCost 4207 X86TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, 4208 Optional<FastMathFlags> FMF, 4209 TTI::TargetCostKind CostKind) { 4210 if (TTI::requiresOrderedReduction(FMF)) 4211 return BaseT::getArithmeticReductionCost(Opcode, ValTy, FMF, CostKind); 4212 4213 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4214 // and make it as the cost. 4215 4216 static const CostTblEntry SLMCostTblNoPairWise[] = { 4217 { ISD::FADD, MVT::v2f64, 3 }, 4218 { ISD::ADD, MVT::v2i64, 5 }, 4219 }; 4220 4221 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4222 { ISD::FADD, MVT::v2f64, 2 }, 4223 { ISD::FADD, MVT::v2f32, 2 }, 4224 { ISD::FADD, MVT::v4f32, 4 }, 4225 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6". 4226 { ISD::ADD, MVT::v2i32, 2 }, // FIXME: chosen to be less than v4i32 4227 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3". 4228 { ISD::ADD, MVT::v2i16, 2 }, // The data reported by the IACA tool is "4.3". 4229 { ISD::ADD, MVT::v4i16, 3 }, // The data reported by the IACA tool is "4.3". 4230 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3". 4231 { ISD::ADD, MVT::v2i8, 2 }, 4232 { ISD::ADD, MVT::v4i8, 2 }, 4233 { ISD::ADD, MVT::v8i8, 2 }, 4234 { ISD::ADD, MVT::v16i8, 3 }, 4235 }; 4236 4237 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4238 { ISD::FADD, MVT::v4f64, 3 }, 4239 { ISD::FADD, MVT::v4f32, 3 }, 4240 { ISD::FADD, MVT::v8f32, 4 }, 4241 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5". 4242 { ISD::ADD, MVT::v4i64, 3 }, 4243 { ISD::ADD, MVT::v8i32, 5 }, 4244 { ISD::ADD, MVT::v16i16, 5 }, 4245 { ISD::ADD, MVT::v32i8, 4 }, 4246 }; 4247 4248 int ISD = TLI->InstructionOpcodeToISD(Opcode); 4249 assert(ISD && "Invalid opcode"); 4250 4251 // Before legalizing the type, give a chance to look up illegal narrow types 4252 // in the table. 4253 // FIXME: Is there a better way to do this? 4254 EVT VT = TLI->getValueType(DL, ValTy); 4255 if (VT.isSimple()) { 4256 MVT MTy = VT.getSimpleVT(); 4257 if (ST->useSLMArithCosts()) 4258 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4259 return Entry->Cost; 4260 4261 if (ST->hasAVX()) 4262 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4263 return Entry->Cost; 4264 4265 if (ST->hasSSE2()) 4266 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4267 return Entry->Cost; 4268 } 4269 4270 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4271 4272 MVT MTy = LT.second; 4273 4274 auto *ValVTy = cast<FixedVectorType>(ValTy); 4275 4276 // Special case: vXi8 mul reductions are performed as vXi16. 4277 if (ISD == ISD::MUL && MTy.getScalarType() == MVT::i8) { 4278 auto *WideSclTy = IntegerType::get(ValVTy->getContext(), 16); 4279 auto *WideVecTy = FixedVectorType::get(WideSclTy, ValVTy->getNumElements()); 4280 return getCastInstrCost(Instruction::ZExt, WideVecTy, ValTy, 4281 TargetTransformInfo::CastContextHint::None, 4282 CostKind) + 4283 getArithmeticReductionCost(Opcode, WideVecTy, FMF, CostKind); 4284 } 4285 4286 InstructionCost ArithmeticCost = 0; 4287 if (LT.first != 1 && MTy.isVector() && 4288 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4289 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4290 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4291 MTy.getVectorNumElements()); 4292 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4293 ArithmeticCost *= LT.first - 1; 4294 } 4295 4296 if (ST->useSLMArithCosts()) 4297 if (const auto *Entry = CostTableLookup(SLMCostTblNoPairWise, ISD, MTy)) 4298 return ArithmeticCost + Entry->Cost; 4299 4300 if (ST->hasAVX()) 4301 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4302 return ArithmeticCost + Entry->Cost; 4303 4304 if (ST->hasSSE2()) 4305 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4306 return ArithmeticCost + Entry->Cost; 4307 4308 // FIXME: These assume a naive kshift+binop lowering, which is probably 4309 // conservative in most cases. 4310 static const CostTblEntry AVX512BoolReduction[] = { 4311 { ISD::AND, MVT::v2i1, 3 }, 4312 { ISD::AND, MVT::v4i1, 5 }, 4313 { ISD::AND, MVT::v8i1, 7 }, 4314 { ISD::AND, MVT::v16i1, 9 }, 4315 { ISD::AND, MVT::v32i1, 11 }, 4316 { ISD::AND, MVT::v64i1, 13 }, 4317 { ISD::OR, MVT::v2i1, 3 }, 4318 { ISD::OR, MVT::v4i1, 5 }, 4319 { ISD::OR, MVT::v8i1, 7 }, 4320 { ISD::OR, MVT::v16i1, 9 }, 4321 { ISD::OR, MVT::v32i1, 11 }, 4322 { ISD::OR, MVT::v64i1, 13 }, 4323 }; 4324 4325 static const CostTblEntry AVX2BoolReduction[] = { 4326 { ISD::AND, MVT::v16i16, 2 }, // vpmovmskb + cmp 4327 { ISD::AND, MVT::v32i8, 2 }, // vpmovmskb + cmp 4328 { ISD::OR, MVT::v16i16, 2 }, // vpmovmskb + cmp 4329 { ISD::OR, MVT::v32i8, 2 }, // vpmovmskb + cmp 4330 }; 4331 4332 static const CostTblEntry AVX1BoolReduction[] = { 4333 { ISD::AND, MVT::v4i64, 2 }, // vmovmskpd + cmp 4334 { ISD::AND, MVT::v8i32, 2 }, // vmovmskps + cmp 4335 { ISD::AND, MVT::v16i16, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4336 { ISD::AND, MVT::v32i8, 4 }, // vextractf128 + vpand + vpmovmskb + cmp 4337 { ISD::OR, MVT::v4i64, 2 }, // vmovmskpd + cmp 4338 { ISD::OR, MVT::v8i32, 2 }, // vmovmskps + cmp 4339 { ISD::OR, MVT::v16i16, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4340 { ISD::OR, MVT::v32i8, 4 }, // vextractf128 + vpor + vpmovmskb + cmp 4341 }; 4342 4343 static const CostTblEntry SSE2BoolReduction[] = { 4344 { ISD::AND, MVT::v2i64, 2 }, // movmskpd + cmp 4345 { ISD::AND, MVT::v4i32, 2 }, // movmskps + cmp 4346 { ISD::AND, MVT::v8i16, 2 }, // pmovmskb + cmp 4347 { ISD::AND, MVT::v16i8, 2 }, // pmovmskb + cmp 4348 { ISD::OR, MVT::v2i64, 2 }, // movmskpd + cmp 4349 { ISD::OR, MVT::v4i32, 2 }, // movmskps + cmp 4350 { ISD::OR, MVT::v8i16, 2 }, // pmovmskb + cmp 4351 { ISD::OR, MVT::v16i8, 2 }, // pmovmskb + cmp 4352 }; 4353 4354 // Handle bool allof/anyof patterns. 4355 if (ValVTy->getElementType()->isIntegerTy(1)) { 4356 InstructionCost ArithmeticCost = 0; 4357 if (LT.first != 1 && MTy.isVector() && 4358 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4359 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4360 auto *SingleOpTy = FixedVectorType::get(ValVTy->getElementType(), 4361 MTy.getVectorNumElements()); 4362 ArithmeticCost = getArithmeticInstrCost(Opcode, SingleOpTy, CostKind); 4363 ArithmeticCost *= LT.first - 1; 4364 } 4365 4366 if (ST->hasAVX512()) 4367 if (const auto *Entry = CostTableLookup(AVX512BoolReduction, ISD, MTy)) 4368 return ArithmeticCost + Entry->Cost; 4369 if (ST->hasAVX2()) 4370 if (const auto *Entry = CostTableLookup(AVX2BoolReduction, ISD, MTy)) 4371 return ArithmeticCost + Entry->Cost; 4372 if (ST->hasAVX()) 4373 if (const auto *Entry = CostTableLookup(AVX1BoolReduction, ISD, MTy)) 4374 return ArithmeticCost + Entry->Cost; 4375 if (ST->hasSSE2()) 4376 if (const auto *Entry = CostTableLookup(SSE2BoolReduction, ISD, MTy)) 4377 return ArithmeticCost + Entry->Cost; 4378 4379 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4380 } 4381 4382 unsigned NumVecElts = ValVTy->getNumElements(); 4383 unsigned ScalarSize = ValVTy->getScalarSizeInBits(); 4384 4385 // Special case power of 2 reductions where the scalar type isn't changed 4386 // by type legalization. 4387 if (!isPowerOf2_32(NumVecElts) || ScalarSize != MTy.getScalarSizeInBits()) 4388 return BaseT::getArithmeticReductionCost(Opcode, ValVTy, FMF, CostKind); 4389 4390 InstructionCost ReductionCost = 0; 4391 4392 auto *Ty = ValVTy; 4393 if (LT.first != 1 && MTy.isVector() && 4394 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4395 // Type needs to be split. We need LT.first - 1 arithmetic ops. 4396 Ty = FixedVectorType::get(ValVTy->getElementType(), 4397 MTy.getVectorNumElements()); 4398 ReductionCost = getArithmeticInstrCost(Opcode, Ty, CostKind); 4399 ReductionCost *= LT.first - 1; 4400 NumVecElts = MTy.getVectorNumElements(); 4401 } 4402 4403 // Now handle reduction with the legal type, taking into account size changes 4404 // at each level. 4405 while (NumVecElts > 1) { 4406 // Determine the size of the remaining vector we need to reduce. 4407 unsigned Size = NumVecElts * ScalarSize; 4408 NumVecElts /= 2; 4409 // If we're reducing from 256/512 bits, use an extract_subvector. 4410 if (Size > 128) { 4411 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4412 ReductionCost += 4413 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4414 Ty = SubTy; 4415 } else if (Size == 128) { 4416 // Reducing from 128 bits is a permute of v2f64/v2i64. 4417 FixedVectorType *ShufTy; 4418 if (ValVTy->isFloatingPointTy()) 4419 ShufTy = 4420 FixedVectorType::get(Type::getDoubleTy(ValVTy->getContext()), 2); 4421 else 4422 ShufTy = 4423 FixedVectorType::get(Type::getInt64Ty(ValVTy->getContext()), 2); 4424 ReductionCost += 4425 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4426 } else if (Size == 64) { 4427 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4428 FixedVectorType *ShufTy; 4429 if (ValVTy->isFloatingPointTy()) 4430 ShufTy = 4431 FixedVectorType::get(Type::getFloatTy(ValVTy->getContext()), 4); 4432 else 4433 ShufTy = 4434 FixedVectorType::get(Type::getInt32Ty(ValVTy->getContext()), 4); 4435 ReductionCost += 4436 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4437 } else { 4438 // Reducing from smaller size is a shift by immediate. 4439 auto *ShiftTy = FixedVectorType::get( 4440 Type::getIntNTy(ValVTy->getContext(), Size), 128 / Size); 4441 ReductionCost += getArithmeticInstrCost( 4442 Instruction::LShr, ShiftTy, CostKind, 4443 TargetTransformInfo::OK_AnyValue, 4444 TargetTransformInfo::OK_UniformConstantValue, 4445 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4446 } 4447 4448 // Add the arithmetic op for this level. 4449 ReductionCost += getArithmeticInstrCost(Opcode, Ty, CostKind); 4450 } 4451 4452 // Add the final extract element to the cost. 4453 return ReductionCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4454 } 4455 4456 InstructionCost X86TTIImpl::getMinMaxCost(Type *Ty, Type *CondTy, 4457 bool IsUnsigned) { 4458 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); 4459 4460 MVT MTy = LT.second; 4461 4462 int ISD; 4463 if (Ty->isIntOrIntVectorTy()) { 4464 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4465 } else { 4466 assert(Ty->isFPOrFPVectorTy() && 4467 "Expected float point or integer vector type."); 4468 ISD = ISD::FMINNUM; 4469 } 4470 4471 static const CostTblEntry SSE1CostTbl[] = { 4472 {ISD::FMINNUM, MVT::v4f32, 1}, 4473 }; 4474 4475 static const CostTblEntry SSE2CostTbl[] = { 4476 {ISD::FMINNUM, MVT::v2f64, 1}, 4477 {ISD::SMIN, MVT::v8i16, 1}, 4478 {ISD::UMIN, MVT::v16i8, 1}, 4479 }; 4480 4481 static const CostTblEntry SSE41CostTbl[] = { 4482 {ISD::SMIN, MVT::v4i32, 1}, 4483 {ISD::UMIN, MVT::v4i32, 1}, 4484 {ISD::UMIN, MVT::v8i16, 1}, 4485 {ISD::SMIN, MVT::v16i8, 1}, 4486 }; 4487 4488 static const CostTblEntry SSE42CostTbl[] = { 4489 {ISD::UMIN, MVT::v2i64, 3}, // xor+pcmpgtq+blendvpd 4490 }; 4491 4492 static const CostTblEntry AVX1CostTbl[] = { 4493 {ISD::FMINNUM, MVT::v8f32, 1}, 4494 {ISD::FMINNUM, MVT::v4f64, 1}, 4495 {ISD::SMIN, MVT::v8i32, 3}, 4496 {ISD::UMIN, MVT::v8i32, 3}, 4497 {ISD::SMIN, MVT::v16i16, 3}, 4498 {ISD::UMIN, MVT::v16i16, 3}, 4499 {ISD::SMIN, MVT::v32i8, 3}, 4500 {ISD::UMIN, MVT::v32i8, 3}, 4501 }; 4502 4503 static const CostTblEntry AVX2CostTbl[] = { 4504 {ISD::SMIN, MVT::v8i32, 1}, 4505 {ISD::UMIN, MVT::v8i32, 1}, 4506 {ISD::SMIN, MVT::v16i16, 1}, 4507 {ISD::UMIN, MVT::v16i16, 1}, 4508 {ISD::SMIN, MVT::v32i8, 1}, 4509 {ISD::UMIN, MVT::v32i8, 1}, 4510 }; 4511 4512 static const CostTblEntry AVX512CostTbl[] = { 4513 {ISD::FMINNUM, MVT::v16f32, 1}, 4514 {ISD::FMINNUM, MVT::v8f64, 1}, 4515 {ISD::SMIN, MVT::v2i64, 1}, 4516 {ISD::UMIN, MVT::v2i64, 1}, 4517 {ISD::SMIN, MVT::v4i64, 1}, 4518 {ISD::UMIN, MVT::v4i64, 1}, 4519 {ISD::SMIN, MVT::v8i64, 1}, 4520 {ISD::UMIN, MVT::v8i64, 1}, 4521 {ISD::SMIN, MVT::v16i32, 1}, 4522 {ISD::UMIN, MVT::v16i32, 1}, 4523 }; 4524 4525 static const CostTblEntry AVX512BWCostTbl[] = { 4526 {ISD::SMIN, MVT::v32i16, 1}, 4527 {ISD::UMIN, MVT::v32i16, 1}, 4528 {ISD::SMIN, MVT::v64i8, 1}, 4529 {ISD::UMIN, MVT::v64i8, 1}, 4530 }; 4531 4532 // If we have a native MIN/MAX instruction for this type, use it. 4533 if (ST->hasBWI()) 4534 if (const auto *Entry = CostTableLookup(AVX512BWCostTbl, ISD, MTy)) 4535 return LT.first * Entry->Cost; 4536 4537 if (ST->hasAVX512()) 4538 if (const auto *Entry = CostTableLookup(AVX512CostTbl, ISD, MTy)) 4539 return LT.first * Entry->Cost; 4540 4541 if (ST->hasAVX2()) 4542 if (const auto *Entry = CostTableLookup(AVX2CostTbl, ISD, MTy)) 4543 return LT.first * Entry->Cost; 4544 4545 if (ST->hasAVX()) 4546 if (const auto *Entry = CostTableLookup(AVX1CostTbl, ISD, MTy)) 4547 return LT.first * Entry->Cost; 4548 4549 if (ST->hasSSE42()) 4550 if (const auto *Entry = CostTableLookup(SSE42CostTbl, ISD, MTy)) 4551 return LT.first * Entry->Cost; 4552 4553 if (ST->hasSSE41()) 4554 if (const auto *Entry = CostTableLookup(SSE41CostTbl, ISD, MTy)) 4555 return LT.first * Entry->Cost; 4556 4557 if (ST->hasSSE2()) 4558 if (const auto *Entry = CostTableLookup(SSE2CostTbl, ISD, MTy)) 4559 return LT.first * Entry->Cost; 4560 4561 if (ST->hasSSE1()) 4562 if (const auto *Entry = CostTableLookup(SSE1CostTbl, ISD, MTy)) 4563 return LT.first * Entry->Cost; 4564 4565 unsigned CmpOpcode; 4566 if (Ty->isFPOrFPVectorTy()) { 4567 CmpOpcode = Instruction::FCmp; 4568 } else { 4569 assert(Ty->isIntOrIntVectorTy() && 4570 "expecting floating point or integer type for min/max reduction"); 4571 CmpOpcode = Instruction::ICmp; 4572 } 4573 4574 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 4575 // Otherwise fall back to cmp+select. 4576 InstructionCost Result = 4577 getCmpSelInstrCost(CmpOpcode, Ty, CondTy, CmpInst::BAD_ICMP_PREDICATE, 4578 CostKind) + 4579 getCmpSelInstrCost(Instruction::Select, Ty, CondTy, 4580 CmpInst::BAD_ICMP_PREDICATE, CostKind); 4581 return Result; 4582 } 4583 4584 InstructionCost 4585 X86TTIImpl::getMinMaxReductionCost(VectorType *ValTy, VectorType *CondTy, 4586 bool IsUnsigned, 4587 TTI::TargetCostKind CostKind) { 4588 std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy); 4589 4590 MVT MTy = LT.second; 4591 4592 int ISD; 4593 if (ValTy->isIntOrIntVectorTy()) { 4594 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; 4595 } else { 4596 assert(ValTy->isFPOrFPVectorTy() && 4597 "Expected float point or integer vector type."); 4598 ISD = ISD::FMINNUM; 4599 } 4600 4601 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput 4602 // and make it as the cost. 4603 4604 static const CostTblEntry SSE2CostTblNoPairWise[] = { 4605 {ISD::UMIN, MVT::v2i16, 5}, // need pxors to use pminsw/pmaxsw 4606 {ISD::UMIN, MVT::v4i16, 7}, // need pxors to use pminsw/pmaxsw 4607 {ISD::UMIN, MVT::v8i16, 9}, // need pxors to use pminsw/pmaxsw 4608 }; 4609 4610 static const CostTblEntry SSE41CostTblNoPairWise[] = { 4611 {ISD::SMIN, MVT::v2i16, 3}, // same as sse2 4612 {ISD::SMIN, MVT::v4i16, 5}, // same as sse2 4613 {ISD::UMIN, MVT::v2i16, 5}, // same as sse2 4614 {ISD::UMIN, MVT::v4i16, 7}, // same as sse2 4615 {ISD::SMIN, MVT::v8i16, 4}, // phminposuw+xor 4616 {ISD::UMIN, MVT::v8i16, 4}, // FIXME: umin is cheaper than umax 4617 {ISD::SMIN, MVT::v2i8, 3}, // pminsb 4618 {ISD::SMIN, MVT::v4i8, 5}, // pminsb 4619 {ISD::SMIN, MVT::v8i8, 7}, // pminsb 4620 {ISD::SMIN, MVT::v16i8, 6}, 4621 {ISD::UMIN, MVT::v2i8, 3}, // same as sse2 4622 {ISD::UMIN, MVT::v4i8, 5}, // same as sse2 4623 {ISD::UMIN, MVT::v8i8, 7}, // same as sse2 4624 {ISD::UMIN, MVT::v16i8, 6}, // FIXME: umin is cheaper than umax 4625 }; 4626 4627 static const CostTblEntry AVX1CostTblNoPairWise[] = { 4628 {ISD::SMIN, MVT::v16i16, 6}, 4629 {ISD::UMIN, MVT::v16i16, 6}, // FIXME: umin is cheaper than umax 4630 {ISD::SMIN, MVT::v32i8, 8}, 4631 {ISD::UMIN, MVT::v32i8, 8}, 4632 }; 4633 4634 static const CostTblEntry AVX512BWCostTblNoPairWise[] = { 4635 {ISD::SMIN, MVT::v32i16, 8}, 4636 {ISD::UMIN, MVT::v32i16, 8}, // FIXME: umin is cheaper than umax 4637 {ISD::SMIN, MVT::v64i8, 10}, 4638 {ISD::UMIN, MVT::v64i8, 10}, 4639 }; 4640 4641 // Before legalizing the type, give a chance to look up illegal narrow types 4642 // in the table. 4643 // FIXME: Is there a better way to do this? 4644 EVT VT = TLI->getValueType(DL, ValTy); 4645 if (VT.isSimple()) { 4646 MVT MTy = VT.getSimpleVT(); 4647 if (ST->hasBWI()) 4648 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4649 return Entry->Cost; 4650 4651 if (ST->hasAVX()) 4652 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4653 return Entry->Cost; 4654 4655 if (ST->hasSSE41()) 4656 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4657 return Entry->Cost; 4658 4659 if (ST->hasSSE2()) 4660 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4661 return Entry->Cost; 4662 } 4663 4664 auto *ValVTy = cast<FixedVectorType>(ValTy); 4665 unsigned NumVecElts = ValVTy->getNumElements(); 4666 4667 auto *Ty = ValVTy; 4668 InstructionCost MinMaxCost = 0; 4669 if (LT.first != 1 && MTy.isVector() && 4670 MTy.getVectorNumElements() < ValVTy->getNumElements()) { 4671 // Type needs to be split. We need LT.first - 1 operations ops. 4672 Ty = FixedVectorType::get(ValVTy->getElementType(), 4673 MTy.getVectorNumElements()); 4674 auto *SubCondTy = FixedVectorType::get(CondTy->getElementType(), 4675 MTy.getVectorNumElements()); 4676 MinMaxCost = getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4677 MinMaxCost *= LT.first - 1; 4678 NumVecElts = MTy.getVectorNumElements(); 4679 } 4680 4681 if (ST->hasBWI()) 4682 if (const auto *Entry = CostTableLookup(AVX512BWCostTblNoPairWise, ISD, MTy)) 4683 return MinMaxCost + Entry->Cost; 4684 4685 if (ST->hasAVX()) 4686 if (const auto *Entry = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy)) 4687 return MinMaxCost + Entry->Cost; 4688 4689 if (ST->hasSSE41()) 4690 if (const auto *Entry = CostTableLookup(SSE41CostTblNoPairWise, ISD, MTy)) 4691 return MinMaxCost + Entry->Cost; 4692 4693 if (ST->hasSSE2()) 4694 if (const auto *Entry = CostTableLookup(SSE2CostTblNoPairWise, ISD, MTy)) 4695 return MinMaxCost + Entry->Cost; 4696 4697 unsigned ScalarSize = ValTy->getScalarSizeInBits(); 4698 4699 // Special case power of 2 reductions where the scalar type isn't changed 4700 // by type legalization. 4701 if (!isPowerOf2_32(ValVTy->getNumElements()) || 4702 ScalarSize != MTy.getScalarSizeInBits()) 4703 return BaseT::getMinMaxReductionCost(ValTy, CondTy, IsUnsigned, CostKind); 4704 4705 // Now handle reduction with the legal type, taking into account size changes 4706 // at each level. 4707 while (NumVecElts > 1) { 4708 // Determine the size of the remaining vector we need to reduce. 4709 unsigned Size = NumVecElts * ScalarSize; 4710 NumVecElts /= 2; 4711 // If we're reducing from 256/512 bits, use an extract_subvector. 4712 if (Size > 128) { 4713 auto *SubTy = FixedVectorType::get(ValVTy->getElementType(), NumVecElts); 4714 MinMaxCost += 4715 getShuffleCost(TTI::SK_ExtractSubvector, Ty, None, NumVecElts, SubTy); 4716 Ty = SubTy; 4717 } else if (Size == 128) { 4718 // Reducing from 128 bits is a permute of v2f64/v2i64. 4719 VectorType *ShufTy; 4720 if (ValTy->isFloatingPointTy()) 4721 ShufTy = 4722 FixedVectorType::get(Type::getDoubleTy(ValTy->getContext()), 2); 4723 else 4724 ShufTy = FixedVectorType::get(Type::getInt64Ty(ValTy->getContext()), 2); 4725 MinMaxCost += 4726 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4727 } else if (Size == 64) { 4728 // Reducing from 64 bits is a shuffle of v4f32/v4i32. 4729 FixedVectorType *ShufTy; 4730 if (ValTy->isFloatingPointTy()) 4731 ShufTy = FixedVectorType::get(Type::getFloatTy(ValTy->getContext()), 4); 4732 else 4733 ShufTy = FixedVectorType::get(Type::getInt32Ty(ValTy->getContext()), 4); 4734 MinMaxCost += 4735 getShuffleCost(TTI::SK_PermuteSingleSrc, ShufTy, None, 0, nullptr); 4736 } else { 4737 // Reducing from smaller size is a shift by immediate. 4738 auto *ShiftTy = FixedVectorType::get( 4739 Type::getIntNTy(ValTy->getContext(), Size), 128 / Size); 4740 MinMaxCost += getArithmeticInstrCost( 4741 Instruction::LShr, ShiftTy, TTI::TCK_RecipThroughput, 4742 TargetTransformInfo::OK_AnyValue, 4743 TargetTransformInfo::OK_UniformConstantValue, 4744 TargetTransformInfo::OP_None, TargetTransformInfo::OP_None); 4745 } 4746 4747 // Add the arithmetic op for this level. 4748 auto *SubCondTy = 4749 FixedVectorType::get(CondTy->getElementType(), Ty->getNumElements()); 4750 MinMaxCost += getMinMaxCost(Ty, SubCondTy, IsUnsigned); 4751 } 4752 4753 // Add the final extract element to the cost. 4754 return MinMaxCost + getVectorInstrCost(Instruction::ExtractElement, Ty, 0); 4755 } 4756 4757 /// Calculate the cost of materializing a 64-bit value. This helper 4758 /// method might only calculate a fraction of a larger immediate. Therefore it 4759 /// is valid to return a cost of ZERO. 4760 InstructionCost X86TTIImpl::getIntImmCost(int64_t Val) { 4761 if (Val == 0) 4762 return TTI::TCC_Free; 4763 4764 if (isInt<32>(Val)) 4765 return TTI::TCC_Basic; 4766 4767 return 2 * TTI::TCC_Basic; 4768 } 4769 4770 InstructionCost X86TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 4771 TTI::TargetCostKind CostKind) { 4772 assert(Ty->isIntegerTy()); 4773 4774 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4775 if (BitSize == 0) 4776 return ~0U; 4777 4778 // Never hoist constants larger than 128bit, because this might lead to 4779 // incorrect code generation or assertions in codegen. 4780 // Fixme: Create a cost model for types larger than i128 once the codegen 4781 // issues have been fixed. 4782 if (BitSize > 128) 4783 return TTI::TCC_Free; 4784 4785 if (Imm == 0) 4786 return TTI::TCC_Free; 4787 4788 // Sign-extend all constants to a multiple of 64-bit. 4789 APInt ImmVal = Imm; 4790 if (BitSize % 64 != 0) 4791 ImmVal = Imm.sext(alignTo(BitSize, 64)); 4792 4793 // Split the constant into 64-bit chunks and calculate the cost for each 4794 // chunk. 4795 InstructionCost Cost = 0; 4796 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { 4797 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); 4798 int64_t Val = Tmp.getSExtValue(); 4799 Cost += getIntImmCost(Val); 4800 } 4801 // We need at least one instruction to materialize the constant. 4802 return std::max<InstructionCost>(1, Cost); 4803 } 4804 4805 InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 4806 const APInt &Imm, Type *Ty, 4807 TTI::TargetCostKind CostKind, 4808 Instruction *Inst) { 4809 assert(Ty->isIntegerTy()); 4810 4811 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4812 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4813 // here, so that constant hoisting will ignore this constant. 4814 if (BitSize == 0) 4815 return TTI::TCC_Free; 4816 4817 unsigned ImmIdx = ~0U; 4818 switch (Opcode) { 4819 default: 4820 return TTI::TCC_Free; 4821 case Instruction::GetElementPtr: 4822 // Always hoist the base address of a GetElementPtr. This prevents the 4823 // creation of new constants for every base constant that gets constant 4824 // folded with the offset. 4825 if (Idx == 0) 4826 return 2 * TTI::TCC_Basic; 4827 return TTI::TCC_Free; 4828 case Instruction::Store: 4829 ImmIdx = 0; 4830 break; 4831 case Instruction::ICmp: 4832 // This is an imperfect hack to prevent constant hoisting of 4833 // compares that might be trying to check if a 64-bit value fits in 4834 // 32-bits. The backend can optimize these cases using a right shift by 32. 4835 // Ideally we would check the compare predicate here. There also other 4836 // similar immediates the backend can use shifts for. 4837 if (Idx == 1 && Imm.getBitWidth() == 64) { 4838 uint64_t ImmVal = Imm.getZExtValue(); 4839 if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff) 4840 return TTI::TCC_Free; 4841 } 4842 ImmIdx = 1; 4843 break; 4844 case Instruction::And: 4845 // We support 64-bit ANDs with immediates with 32-bits of leading zeroes 4846 // by using a 32-bit operation with implicit zero extension. Detect such 4847 // immediates here as the normal path expects bit 31 to be sign extended. 4848 if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32>(Imm.getZExtValue())) 4849 return TTI::TCC_Free; 4850 ImmIdx = 1; 4851 break; 4852 case Instruction::Add: 4853 case Instruction::Sub: 4854 // For add/sub, we can use the opposite instruction for INT32_MIN. 4855 if (Idx == 1 && Imm.getBitWidth() == 64 && Imm.getZExtValue() == 0x80000000) 4856 return TTI::TCC_Free; 4857 ImmIdx = 1; 4858 break; 4859 case Instruction::UDiv: 4860 case Instruction::SDiv: 4861 case Instruction::URem: 4862 case Instruction::SRem: 4863 // Division by constant is typically expanded later into a different 4864 // instruction sequence. This completely changes the constants. 4865 // Report them as "free" to stop ConstantHoist from marking them as opaque. 4866 return TTI::TCC_Free; 4867 case Instruction::Mul: 4868 case Instruction::Or: 4869 case Instruction::Xor: 4870 ImmIdx = 1; 4871 break; 4872 // Always return TCC_Free for the shift value of a shift instruction. 4873 case Instruction::Shl: 4874 case Instruction::LShr: 4875 case Instruction::AShr: 4876 if (Idx == 1) 4877 return TTI::TCC_Free; 4878 break; 4879 case Instruction::Trunc: 4880 case Instruction::ZExt: 4881 case Instruction::SExt: 4882 case Instruction::IntToPtr: 4883 case Instruction::PtrToInt: 4884 case Instruction::BitCast: 4885 case Instruction::PHI: 4886 case Instruction::Call: 4887 case Instruction::Select: 4888 case Instruction::Ret: 4889 case Instruction::Load: 4890 break; 4891 } 4892 4893 if (Idx == ImmIdx) { 4894 int NumConstants = divideCeil(BitSize, 64); 4895 InstructionCost Cost = X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4896 return (Cost <= NumConstants * TTI::TCC_Basic) 4897 ? static_cast<int>(TTI::TCC_Free) 4898 : Cost; 4899 } 4900 4901 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4902 } 4903 4904 InstructionCost X86TTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 4905 const APInt &Imm, Type *Ty, 4906 TTI::TargetCostKind CostKind) { 4907 assert(Ty->isIntegerTy()); 4908 4909 unsigned BitSize = Ty->getPrimitiveSizeInBits(); 4910 // There is no cost model for constants with a bit size of 0. Return TCC_Free 4911 // here, so that constant hoisting will ignore this constant. 4912 if (BitSize == 0) 4913 return TTI::TCC_Free; 4914 4915 switch (IID) { 4916 default: 4917 return TTI::TCC_Free; 4918 case Intrinsic::sadd_with_overflow: 4919 case Intrinsic::uadd_with_overflow: 4920 case Intrinsic::ssub_with_overflow: 4921 case Intrinsic::usub_with_overflow: 4922 case Intrinsic::smul_with_overflow: 4923 case Intrinsic::umul_with_overflow: 4924 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue())) 4925 return TTI::TCC_Free; 4926 break; 4927 case Intrinsic::experimental_stackmap: 4928 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4929 return TTI::TCC_Free; 4930 break; 4931 case Intrinsic::experimental_patchpoint_void: 4932 case Intrinsic::experimental_patchpoint_i64: 4933 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))) 4934 return TTI::TCC_Free; 4935 break; 4936 } 4937 return X86TTIImpl::getIntImmCost(Imm, Ty, CostKind); 4938 } 4939 4940 InstructionCost X86TTIImpl::getCFInstrCost(unsigned Opcode, 4941 TTI::TargetCostKind CostKind, 4942 const Instruction *I) { 4943 if (CostKind != TTI::TCK_RecipThroughput) 4944 return Opcode == Instruction::PHI ? 0 : 1; 4945 // Branches are assumed to be predicted. 4946 return 0; 4947 } 4948 4949 int X86TTIImpl::getGatherOverhead() const { 4950 // Some CPUs have more overhead for gather. The specified overhead is relative 4951 // to the Load operation. "2" is the number provided by Intel architects. This 4952 // parameter is used for cost estimation of Gather Op and comparison with 4953 // other alternatives. 4954 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 4955 // enable gather with a -march. 4956 if (ST->hasAVX512() || (ST->hasAVX2() && ST->hasFastGather())) 4957 return 2; 4958 4959 return 1024; 4960 } 4961 4962 int X86TTIImpl::getScatterOverhead() const { 4963 if (ST->hasAVX512()) 4964 return 2; 4965 4966 return 1024; 4967 } 4968 4969 // Return an average cost of Gather / Scatter instruction, maybe improved later. 4970 // FIXME: Add TargetCostKind support. 4971 InstructionCost X86TTIImpl::getGSVectorCost(unsigned Opcode, Type *SrcVTy, 4972 const Value *Ptr, Align Alignment, 4973 unsigned AddressSpace) { 4974 4975 assert(isa<VectorType>(SrcVTy) && "Unexpected type in getGSVectorCost"); 4976 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 4977 4978 // Try to reduce index size from 64 bit (default for GEP) 4979 // to 32. It is essential for VF 16. If the index can't be reduced to 32, the 4980 // operation will use 16 x 64 indices which do not fit in a zmm and needs 4981 // to split. Also check that the base pointer is the same for all lanes, 4982 // and that there's at most one variable index. 4983 auto getIndexSizeInBits = [](const Value *Ptr, const DataLayout &DL) { 4984 unsigned IndexSize = DL.getPointerSizeInBits(); 4985 const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr); 4986 if (IndexSize < 64 || !GEP) 4987 return IndexSize; 4988 4989 unsigned NumOfVarIndices = 0; 4990 const Value *Ptrs = GEP->getPointerOperand(); 4991 if (Ptrs->getType()->isVectorTy() && !getSplatValue(Ptrs)) 4992 return IndexSize; 4993 for (unsigned i = 1; i < GEP->getNumOperands(); ++i) { 4994 if (isa<Constant>(GEP->getOperand(i))) 4995 continue; 4996 Type *IndxTy = GEP->getOperand(i)->getType(); 4997 if (auto *IndexVTy = dyn_cast<VectorType>(IndxTy)) 4998 IndxTy = IndexVTy->getElementType(); 4999 if ((IndxTy->getPrimitiveSizeInBits() == 64 && 5000 !isa<SExtInst>(GEP->getOperand(i))) || 5001 ++NumOfVarIndices > 1) 5002 return IndexSize; // 64 5003 } 5004 return (unsigned)32; 5005 }; 5006 5007 // Trying to reduce IndexSize to 32 bits for vector 16. 5008 // By default the IndexSize is equal to pointer size. 5009 unsigned IndexSize = (ST->hasAVX512() && VF >= 16) 5010 ? getIndexSizeInBits(Ptr, DL) 5011 : DL.getPointerSizeInBits(); 5012 5013 auto *IndexVTy = FixedVectorType::get( 5014 IntegerType::get(SrcVTy->getContext(), IndexSize), VF); 5015 std::pair<InstructionCost, MVT> IdxsLT = 5016 TLI->getTypeLegalizationCost(DL, IndexVTy); 5017 std::pair<InstructionCost, MVT> SrcLT = 5018 TLI->getTypeLegalizationCost(DL, SrcVTy); 5019 InstructionCost::CostType SplitFactor = 5020 *std::max(IdxsLT.first, SrcLT.first).getValue(); 5021 if (SplitFactor > 1) { 5022 // Handle splitting of vector of pointers 5023 auto *SplitSrcTy = 5024 FixedVectorType::get(SrcVTy->getScalarType(), VF / SplitFactor); 5025 return SplitFactor * getGSVectorCost(Opcode, SplitSrcTy, Ptr, Alignment, 5026 AddressSpace); 5027 } 5028 5029 // The gather / scatter cost is given by Intel architects. It is a rough 5030 // number since we are looking at one instruction in a time. 5031 const int GSOverhead = (Opcode == Instruction::Load) 5032 ? getGatherOverhead() 5033 : getScatterOverhead(); 5034 return GSOverhead + VF * getMemoryOpCost(Opcode, SrcVTy->getScalarType(), 5035 MaybeAlign(Alignment), AddressSpace, 5036 TTI::TCK_RecipThroughput); 5037 } 5038 5039 /// Return the cost of full scalarization of gather / scatter operation. 5040 /// 5041 /// Opcode - Load or Store instruction. 5042 /// SrcVTy - The type of the data vector that should be gathered or scattered. 5043 /// VariableMask - The mask is non-constant at compile time. 5044 /// Alignment - Alignment for one element. 5045 /// AddressSpace - pointer[s] address space. 5046 /// 5047 /// FIXME: Add TargetCostKind support. 5048 InstructionCost X86TTIImpl::getGSScalarCost(unsigned Opcode, Type *SrcVTy, 5049 bool VariableMask, Align Alignment, 5050 unsigned AddressSpace) { 5051 Type *ScalarTy = SrcVTy->getScalarType(); 5052 unsigned VF = cast<FixedVectorType>(SrcVTy)->getNumElements(); 5053 APInt DemandedElts = APInt::getAllOnes(VF); 5054 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; 5055 5056 InstructionCost MaskUnpackCost = 0; 5057 if (VariableMask) { 5058 auto *MaskTy = 5059 FixedVectorType::get(Type::getInt1Ty(SrcVTy->getContext()), VF); 5060 MaskUnpackCost = getScalarizationOverhead( 5061 MaskTy, DemandedElts, /*Insert=*/false, /*Extract=*/true); 5062 InstructionCost ScalarCompareCost = getCmpSelInstrCost( 5063 Instruction::ICmp, Type::getInt1Ty(SrcVTy->getContext()), nullptr, 5064 CmpInst::BAD_ICMP_PREDICATE, CostKind); 5065 InstructionCost BranchCost = getCFInstrCost(Instruction::Br, CostKind); 5066 MaskUnpackCost += VF * (BranchCost + ScalarCompareCost); 5067 } 5068 5069 InstructionCost AddressUnpackCost = getScalarizationOverhead( 5070 FixedVectorType::get(ScalarTy->getPointerTo(), VF), DemandedElts, 5071 /*Insert=*/false, /*Extract=*/true); 5072 5073 // The cost of the scalar loads/stores. 5074 InstructionCost MemoryOpCost = 5075 VF * getMemoryOpCost(Opcode, ScalarTy, MaybeAlign(Alignment), 5076 AddressSpace, CostKind); 5077 5078 // The cost of forming the vector from loaded scalars/ 5079 // scalarizing the vector to perform scalar stores. 5080 InstructionCost InsertExtractCost = 5081 getScalarizationOverhead(cast<FixedVectorType>(SrcVTy), DemandedElts, 5082 /*Insert=*/Opcode == Instruction::Load, 5083 /*Extract=*/Opcode == Instruction::Store); 5084 5085 return AddressUnpackCost + MemoryOpCost + MaskUnpackCost + InsertExtractCost; 5086 } 5087 5088 /// Calculate the cost of Gather / Scatter operation 5089 InstructionCost X86TTIImpl::getGatherScatterOpCost( 5090 unsigned Opcode, Type *SrcVTy, const Value *Ptr, bool VariableMask, 5091 Align Alignment, TTI::TargetCostKind CostKind, 5092 const Instruction *I = nullptr) { 5093 if (CostKind != TTI::TCK_RecipThroughput) { 5094 if ((Opcode == Instruction::Load && 5095 isLegalMaskedGather(SrcVTy, Align(Alignment)) && 5096 !forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5097 Align(Alignment))) || 5098 (Opcode == Instruction::Store && 5099 isLegalMaskedScatter(SrcVTy, Align(Alignment)) && 5100 !forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5101 Align(Alignment)))) 5102 return 1; 5103 return BaseT::getGatherScatterOpCost(Opcode, SrcVTy, Ptr, VariableMask, 5104 Alignment, CostKind, I); 5105 } 5106 5107 assert(SrcVTy->isVectorTy() && "Unexpected data type for Gather/Scatter"); 5108 PointerType *PtrTy = dyn_cast<PointerType>(Ptr->getType()); 5109 if (!PtrTy && Ptr->getType()->isVectorTy()) 5110 PtrTy = dyn_cast<PointerType>( 5111 cast<VectorType>(Ptr->getType())->getElementType()); 5112 assert(PtrTy && "Unexpected type for Ptr argument"); 5113 unsigned AddressSpace = PtrTy->getAddressSpace(); 5114 5115 if ((Opcode == Instruction::Load && 5116 (!isLegalMaskedGather(SrcVTy, Align(Alignment)) || 5117 forceScalarizeMaskedGather(cast<VectorType>(SrcVTy), 5118 Align(Alignment)))) || 5119 (Opcode == Instruction::Store && 5120 (!isLegalMaskedScatter(SrcVTy, Align(Alignment)) || 5121 forceScalarizeMaskedScatter(cast<VectorType>(SrcVTy), 5122 Align(Alignment))))) 5123 return getGSScalarCost(Opcode, SrcVTy, VariableMask, Alignment, 5124 AddressSpace); 5125 5126 return getGSVectorCost(Opcode, SrcVTy, Ptr, Alignment, AddressSpace); 5127 } 5128 5129 bool X86TTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1, 5130 TargetTransformInfo::LSRCost &C2) { 5131 // X86 specific here are "instruction number 1st priority". 5132 return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, 5133 C1.NumIVMuls, C1.NumBaseAdds, 5134 C1.ScaleCost, C1.ImmCost, C1.SetupCost) < 5135 std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, 5136 C2.NumIVMuls, C2.NumBaseAdds, 5137 C2.ScaleCost, C2.ImmCost, C2.SetupCost); 5138 } 5139 5140 bool X86TTIImpl::canMacroFuseCmp() { 5141 return ST->hasMacroFusion() || ST->hasBranchFusion(); 5142 } 5143 5144 bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, Align Alignment) { 5145 if (!ST->hasAVX()) 5146 return false; 5147 5148 // The backend can't handle a single element vector. 5149 if (isa<VectorType>(DataTy) && 5150 cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5151 return false; 5152 Type *ScalarTy = DataTy->getScalarType(); 5153 5154 if (ScalarTy->isPointerTy()) 5155 return true; 5156 5157 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5158 return true; 5159 5160 if (ScalarTy->isHalfTy() && ST->hasBWI() && ST->hasFP16()) 5161 return true; 5162 5163 if (!ScalarTy->isIntegerTy()) 5164 return false; 5165 5166 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5167 return IntWidth == 32 || IntWidth == 64 || 5168 ((IntWidth == 8 || IntWidth == 16) && ST->hasBWI()); 5169 } 5170 5171 bool X86TTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment) { 5172 return isLegalMaskedLoad(DataType, Alignment); 5173 } 5174 5175 bool X86TTIImpl::isLegalNTLoad(Type *DataType, Align Alignment) { 5176 unsigned DataSize = DL.getTypeStoreSize(DataType); 5177 // The only supported nontemporal loads are for aligned vectors of 16 or 32 5178 // bytes. Note that 32-byte nontemporal vector loads are supported by AVX2 5179 // (the equivalent stores only require AVX). 5180 if (Alignment >= DataSize && (DataSize == 16 || DataSize == 32)) 5181 return DataSize == 16 ? ST->hasSSE1() : ST->hasAVX2(); 5182 5183 return false; 5184 } 5185 5186 bool X86TTIImpl::isLegalNTStore(Type *DataType, Align Alignment) { 5187 unsigned DataSize = DL.getTypeStoreSize(DataType); 5188 5189 // SSE4A supports nontemporal stores of float and double at arbitrary 5190 // alignment. 5191 if (ST->hasSSE4A() && (DataType->isFloatTy() || DataType->isDoubleTy())) 5192 return true; 5193 5194 // Besides the SSE4A subtarget exception above, only aligned stores are 5195 // available nontemporaly on any other subtarget. And only stores with a size 5196 // of 4..32 bytes (powers of 2, only) are permitted. 5197 if (Alignment < DataSize || DataSize < 4 || DataSize > 32 || 5198 !isPowerOf2_32(DataSize)) 5199 return false; 5200 5201 // 32-byte vector nontemporal stores are supported by AVX (the equivalent 5202 // loads require AVX2). 5203 if (DataSize == 32) 5204 return ST->hasAVX(); 5205 if (DataSize == 16) 5206 return ST->hasSSE1(); 5207 return true; 5208 } 5209 5210 bool X86TTIImpl::isLegalBroadcastLoad(Type *ElementTy, 5211 ElementCount NumElements) const { 5212 // movddup 5213 return ST->hasSSE3() && !NumElements.isScalable() && 5214 NumElements.getFixedValue() == 2 && 5215 ElementTy == Type::getDoubleTy(ElementTy->getContext()); 5216 } 5217 5218 bool X86TTIImpl::isLegalMaskedExpandLoad(Type *DataTy) { 5219 if (!isa<VectorType>(DataTy)) 5220 return false; 5221 5222 if (!ST->hasAVX512()) 5223 return false; 5224 5225 // The backend can't handle a single element vector. 5226 if (cast<FixedVectorType>(DataTy)->getNumElements() == 1) 5227 return false; 5228 5229 Type *ScalarTy = cast<VectorType>(DataTy)->getElementType(); 5230 5231 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5232 return true; 5233 5234 if (!ScalarTy->isIntegerTy()) 5235 return false; 5236 5237 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5238 return IntWidth == 32 || IntWidth == 64 || 5239 ((IntWidth == 8 || IntWidth == 16) && ST->hasVBMI2()); 5240 } 5241 5242 bool X86TTIImpl::isLegalMaskedCompressStore(Type *DataTy) { 5243 return isLegalMaskedExpandLoad(DataTy); 5244 } 5245 5246 bool X86TTIImpl::supportsGather() const { 5247 // Some CPUs have better gather performance than others. 5248 // TODO: Remove the explicit ST->hasAVX512()?, That would mean we would only 5249 // enable gather with a -march. 5250 return ST->hasAVX512() || (ST->hasFastGather() && ST->hasAVX2()); 5251 } 5252 5253 bool X86TTIImpl::forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) { 5254 // Gather / Scatter for vector 2 is not profitable on KNL / SKX 5255 // Vector-4 of gather/scatter instruction does not exist on KNL. We can extend 5256 // it to 8 elements, but zeroing upper bits of the mask vector will add more 5257 // instructions. Right now we give the scalar cost of vector-4 for KNL. TODO: 5258 // Check, maybe the gather/scatter instruction is better in the VariableMask 5259 // case. 5260 unsigned NumElts = cast<FixedVectorType>(VTy)->getNumElements(); 5261 return NumElts == 1 || 5262 (ST->hasAVX512() && (NumElts == 2 || (NumElts == 4 && !ST->hasVLX()))); 5263 } 5264 5265 bool X86TTIImpl::isLegalMaskedGather(Type *DataTy, Align Alignment) { 5266 if (!supportsGather()) 5267 return false; 5268 Type *ScalarTy = DataTy->getScalarType(); 5269 if (ScalarTy->isPointerTy()) 5270 return true; 5271 5272 if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy()) 5273 return true; 5274 5275 if (!ScalarTy->isIntegerTy()) 5276 return false; 5277 5278 unsigned IntWidth = ScalarTy->getIntegerBitWidth(); 5279 return IntWidth == 32 || IntWidth == 64; 5280 } 5281 5282 bool X86TTIImpl::isLegalMaskedScatter(Type *DataType, Align Alignment) { 5283 // AVX2 doesn't support scatter 5284 if (!ST->hasAVX512()) 5285 return false; 5286 return isLegalMaskedGather(DataType, Alignment); 5287 } 5288 5289 bool X86TTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) { 5290 EVT VT = TLI->getValueType(DL, DataType); 5291 return TLI->isOperationLegal(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, VT); 5292 } 5293 5294 bool X86TTIImpl::isFCmpOrdCheaperThanFCmpZero(Type *Ty) { 5295 return false; 5296 } 5297 5298 bool X86TTIImpl::areInlineCompatible(const Function *Caller, 5299 const Function *Callee) const { 5300 const TargetMachine &TM = getTLI()->getTargetMachine(); 5301 5302 // Work this as a subsetting of subtarget features. 5303 const FeatureBitset &CallerBits = 5304 TM.getSubtargetImpl(*Caller)->getFeatureBits(); 5305 const FeatureBitset &CalleeBits = 5306 TM.getSubtargetImpl(*Callee)->getFeatureBits(); 5307 5308 // Check whether features are the same (apart from the ignore list). 5309 FeatureBitset RealCallerBits = CallerBits & ~InlineFeatureIgnoreList; 5310 FeatureBitset RealCalleeBits = CalleeBits & ~InlineFeatureIgnoreList; 5311 if (RealCallerBits == RealCalleeBits) 5312 return true; 5313 5314 // If the features are a subset, we need to additionally check for calls 5315 // that may become ABI-incompatible as a result of inlining. 5316 if ((RealCallerBits & RealCalleeBits) != RealCalleeBits) 5317 return false; 5318 5319 for (const Instruction &I : instructions(Callee)) { 5320 if (const auto *CB = dyn_cast<CallBase>(&I)) { 5321 SmallVector<Type *, 8> Types; 5322 for (Value *Arg : CB->args()) 5323 Types.push_back(Arg->getType()); 5324 if (!CB->getType()->isVoidTy()) 5325 Types.push_back(CB->getType()); 5326 5327 // Simple types are always ABI compatible. 5328 auto IsSimpleTy = [](Type *Ty) { 5329 return !Ty->isVectorTy() && !Ty->isAggregateType(); 5330 }; 5331 if (all_of(Types, IsSimpleTy)) 5332 continue; 5333 5334 if (Function *NestedCallee = CB->getCalledFunction()) { 5335 // Assume that intrinsics are always ABI compatible. 5336 if (NestedCallee->isIntrinsic()) 5337 continue; 5338 5339 // Do a precise compatibility check. 5340 if (!areTypesABICompatible(Caller, NestedCallee, Types)) 5341 return false; 5342 } else { 5343 // We don't know the target features of the callee, 5344 // assume it is incompatible. 5345 return false; 5346 } 5347 } 5348 } 5349 return true; 5350 } 5351 5352 bool X86TTIImpl::areTypesABICompatible(const Function *Caller, 5353 const Function *Callee, 5354 const ArrayRef<Type *> &Types) const { 5355 if (!BaseT::areTypesABICompatible(Caller, Callee, Types)) 5356 return false; 5357 5358 // If we get here, we know the target features match. If one function 5359 // considers 512-bit vectors legal and the other does not, consider them 5360 // incompatible. 5361 const TargetMachine &TM = getTLI()->getTargetMachine(); 5362 5363 if (TM.getSubtarget<X86Subtarget>(*Caller).useAVX512Regs() == 5364 TM.getSubtarget<X86Subtarget>(*Callee).useAVX512Regs()) 5365 return true; 5366 5367 // Consider the arguments compatible if they aren't vectors or aggregates. 5368 // FIXME: Look at the size of vectors. 5369 // FIXME: Look at the element types of aggregates to see if there are vectors. 5370 return llvm::none_of(Types, 5371 [](Type *T) { return T->isVectorTy() || T->isAggregateType(); }); 5372 } 5373 5374 X86TTIImpl::TTI::MemCmpExpansionOptions 5375 X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { 5376 TTI::MemCmpExpansionOptions Options; 5377 Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize); 5378 Options.NumLoadsPerBlock = 2; 5379 // All GPR and vector loads can be unaligned. 5380 Options.AllowOverlappingLoads = true; 5381 if (IsZeroCmp) { 5382 // Only enable vector loads for equality comparison. Right now the vector 5383 // version is not as fast for three way compare (see #33329). 5384 const unsigned PreferredWidth = ST->getPreferVectorWidth(); 5385 if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); 5386 if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); 5387 if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); 5388 } 5389 if (ST->is64Bit()) { 5390 Options.LoadSizes.push_back(8); 5391 } 5392 Options.LoadSizes.push_back(4); 5393 Options.LoadSizes.push_back(2); 5394 Options.LoadSizes.push_back(1); 5395 return Options; 5396 } 5397 5398 bool X86TTIImpl::prefersVectorizedAddressing() const { 5399 return supportsGather(); 5400 } 5401 5402 bool X86TTIImpl::supportsEfficientVectorElementLoadStore() const { 5403 return false; 5404 } 5405 5406 bool X86TTIImpl::enableInterleavedAccessVectorization() { 5407 // TODO: We expect this to be beneficial regardless of arch, 5408 // but there are currently some unexplained performance artifacts on Atom. 5409 // As a temporary solution, disable on Atom. 5410 return !(ST->isAtom()); 5411 } 5412 5413 // Get estimation for interleaved load/store operations and strided load. 5414 // \p Indices contains indices for strided load. 5415 // \p Factor - the factor of interleaving. 5416 // AVX-512 provides 3-src shuffles that significantly reduces the cost. 5417 InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX512( 5418 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 5419 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 5420 TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) { 5421 // VecTy for interleave memop is <VF*Factor x Elt>. 5422 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5423 // VecTy = <12 x i32>. 5424 5425 // Calculate the number of memory operations (NumOfMemOps), required 5426 // for load/store the VecTy. 5427 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5428 unsigned VecTySize = DL.getTypeStoreSize(VecTy); 5429 unsigned LegalVTSize = LegalVT.getStoreSize(); 5430 unsigned NumOfMemOps = (VecTySize + LegalVTSize - 1) / LegalVTSize; 5431 5432 // Get the cost of one memory operation. 5433 auto *SingleMemOpTy = FixedVectorType::get(VecTy->getElementType(), 5434 LegalVT.getVectorNumElements()); 5435 InstructionCost MemOpCost; 5436 bool UseMaskedMemOp = UseMaskForCond || UseMaskForGaps; 5437 if (UseMaskedMemOp) 5438 MemOpCost = getMaskedMemoryOpCost(Opcode, SingleMemOpTy, Alignment, 5439 AddressSpace, CostKind); 5440 else 5441 MemOpCost = getMemoryOpCost(Opcode, SingleMemOpTy, MaybeAlign(Alignment), 5442 AddressSpace, CostKind); 5443 5444 unsigned VF = VecTy->getNumElements() / Factor; 5445 MVT VT = MVT::getVectorVT(MVT::getVT(VecTy->getScalarType()), VF); 5446 5447 InstructionCost MaskCost; 5448 if (UseMaskedMemOp) { 5449 APInt DemandedLoadStoreElts = APInt::getZero(VecTy->getNumElements()); 5450 for (unsigned Index : Indices) { 5451 assert(Index < Factor && "Invalid index for interleaved memory op"); 5452 for (unsigned Elm = 0; Elm < VF; Elm++) 5453 DemandedLoadStoreElts.setBit(Index + Elm * Factor); 5454 } 5455 5456 Type *I1Type = Type::getInt1Ty(VecTy->getContext()); 5457 5458 MaskCost = getReplicationShuffleCost( 5459 I1Type, Factor, VF, 5460 UseMaskForGaps ? DemandedLoadStoreElts 5461 : APInt::getAllOnes(VecTy->getNumElements()), 5462 CostKind); 5463 5464 // The Gaps mask is invariant and created outside the loop, therefore the 5465 // cost of creating it is not accounted for here. However if we have both 5466 // a MaskForGaps and some other mask that guards the execution of the 5467 // memory access, we need to account for the cost of And-ing the two masks 5468 // inside the loop. 5469 if (UseMaskForGaps) { 5470 auto *MaskVT = FixedVectorType::get(I1Type, VecTy->getNumElements()); 5471 MaskCost += getArithmeticInstrCost(BinaryOperator::And, MaskVT, CostKind); 5472 } 5473 } 5474 5475 if (Opcode == Instruction::Load) { 5476 // The tables (AVX512InterleavedLoadTbl and AVX512InterleavedStoreTbl) 5477 // contain the cost of the optimized shuffle sequence that the 5478 // X86InterleavedAccess pass will generate. 5479 // The cost of loads and stores are computed separately from the table. 5480 5481 // X86InterleavedAccess support only the following interleaved-access group. 5482 static const CostTblEntry AVX512InterleavedLoadTbl[] = { 5483 {3, MVT::v16i8, 12}, //(load 48i8 and) deinterleave into 3 x 16i8 5484 {3, MVT::v32i8, 14}, //(load 96i8 and) deinterleave into 3 x 32i8 5485 {3, MVT::v64i8, 22}, //(load 96i8 and) deinterleave into 3 x 32i8 5486 }; 5487 5488 if (const auto *Entry = 5489 CostTableLookup(AVX512InterleavedLoadTbl, Factor, VT)) 5490 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5491 //If an entry does not exist, fallback to the default implementation. 5492 5493 // Kind of shuffle depends on number of loaded values. 5494 // If we load the entire data in one register, we can use a 1-src shuffle. 5495 // Otherwise, we'll merge 2 sources in each operation. 5496 TTI::ShuffleKind ShuffleKind = 5497 (NumOfMemOps > 1) ? TTI::SK_PermuteTwoSrc : TTI::SK_PermuteSingleSrc; 5498 5499 InstructionCost ShuffleCost = 5500 getShuffleCost(ShuffleKind, SingleMemOpTy, None, 0, nullptr); 5501 5502 unsigned NumOfLoadsInInterleaveGrp = 5503 Indices.size() ? Indices.size() : Factor; 5504 auto *ResultTy = FixedVectorType::get(VecTy->getElementType(), 5505 VecTy->getNumElements() / Factor); 5506 InstructionCost NumOfResults = 5507 getTLI()->getTypeLegalizationCost(DL, ResultTy).first * 5508 NumOfLoadsInInterleaveGrp; 5509 5510 // About a half of the loads may be folded in shuffles when we have only 5511 // one result. If we have more than one result, or the loads are masked, 5512 // we do not fold loads at all. 5513 unsigned NumOfUnfoldedLoads = 5514 UseMaskedMemOp || NumOfResults > 1 ? NumOfMemOps : NumOfMemOps / 2; 5515 5516 // Get a number of shuffle operations per result. 5517 unsigned NumOfShufflesPerResult = 5518 std::max((unsigned)1, (unsigned)(NumOfMemOps - 1)); 5519 5520 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5521 // When we have more than one destination, we need additional instructions 5522 // to keep sources. 5523 InstructionCost NumOfMoves = 0; 5524 if (NumOfResults > 1 && ShuffleKind == TTI::SK_PermuteTwoSrc) 5525 NumOfMoves = NumOfResults * NumOfShufflesPerResult / 2; 5526 5527 InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + 5528 MaskCost + NumOfUnfoldedLoads * MemOpCost + 5529 NumOfMoves; 5530 5531 return Cost; 5532 } 5533 5534 // Store. 5535 assert(Opcode == Instruction::Store && 5536 "Expected Store Instruction at this point"); 5537 // X86InterleavedAccess support only the following interleaved-access group. 5538 static const CostTblEntry AVX512InterleavedStoreTbl[] = { 5539 {3, MVT::v16i8, 12}, // interleave 3 x 16i8 into 48i8 (and store) 5540 {3, MVT::v32i8, 14}, // interleave 3 x 32i8 into 96i8 (and store) 5541 {3, MVT::v64i8, 26}, // interleave 3 x 64i8 into 96i8 (and store) 5542 5543 {4, MVT::v8i8, 10}, // interleave 4 x 8i8 into 32i8 (and store) 5544 {4, MVT::v16i8, 11}, // interleave 4 x 16i8 into 64i8 (and store) 5545 {4, MVT::v32i8, 14}, // interleave 4 x 32i8 into 128i8 (and store) 5546 {4, MVT::v64i8, 24} // interleave 4 x 32i8 into 256i8 (and store) 5547 }; 5548 5549 if (const auto *Entry = 5550 CostTableLookup(AVX512InterleavedStoreTbl, Factor, VT)) 5551 return MaskCost + NumOfMemOps * MemOpCost + Entry->Cost; 5552 //If an entry does not exist, fallback to the default implementation. 5553 5554 // There is no strided stores meanwhile. And store can't be folded in 5555 // shuffle. 5556 unsigned NumOfSources = Factor; // The number of values to be merged. 5557 InstructionCost ShuffleCost = 5558 getShuffleCost(TTI::SK_PermuteTwoSrc, SingleMemOpTy, None, 0, nullptr); 5559 unsigned NumOfShufflesPerStore = NumOfSources - 1; 5560 5561 // The SK_MergeTwoSrc shuffle clobbers one of src operands. 5562 // We need additional instructions to keep sources. 5563 unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / 2; 5564 InstructionCost Cost = 5565 MaskCost + 5566 NumOfMemOps * (MemOpCost + NumOfShufflesPerStore * ShuffleCost) + 5567 NumOfMoves; 5568 return Cost; 5569 } 5570 5571 InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( 5572 unsigned Opcode, Type *BaseTy, unsigned Factor, ArrayRef<unsigned> Indices, 5573 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 5574 bool UseMaskForCond, bool UseMaskForGaps) { 5575 auto *VecTy = cast<FixedVectorType>(BaseTy); 5576 5577 auto isSupportedOnAVX512 = [&](Type *VecTy, bool HasBW) { 5578 Type *EltTy = cast<VectorType>(VecTy)->getElementType(); 5579 if (EltTy->isFloatTy() || EltTy->isDoubleTy() || EltTy->isIntegerTy(64) || 5580 EltTy->isIntegerTy(32) || EltTy->isPointerTy()) 5581 return true; 5582 if (EltTy->isIntegerTy(16) || EltTy->isIntegerTy(8) || 5583 (!ST->useSoftFloat() && ST->hasFP16() && EltTy->isHalfTy())) 5584 return HasBW; 5585 return false; 5586 }; 5587 if (ST->hasAVX512() && isSupportedOnAVX512(VecTy, ST->hasBWI())) 5588 return getInterleavedMemoryOpCostAVX512( 5589 Opcode, VecTy, Factor, Indices, Alignment, 5590 AddressSpace, CostKind, UseMaskForCond, UseMaskForGaps); 5591 5592 if (UseMaskForCond || UseMaskForGaps) 5593 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5594 Alignment, AddressSpace, CostKind, 5595 UseMaskForCond, UseMaskForGaps); 5596 5597 // Get estimation for interleaved load/store operations for SSE-AVX2. 5598 // As opposed to AVX-512, SSE-AVX2 do not have generic shuffles that allow 5599 // computing the cost using a generic formula as a function of generic 5600 // shuffles. We therefore use a lookup table instead, filled according to 5601 // the instruction sequences that codegen currently generates. 5602 5603 // VecTy for interleave memop is <VF*Factor x Elt>. 5604 // So, for VF=4, Interleave Factor = 3, Element type = i32 we have 5605 // VecTy = <12 x i32>. 5606 MVT LegalVT = getTLI()->getTypeLegalizationCost(DL, VecTy).second; 5607 5608 // This function can be called with VecTy=<6xi128>, Factor=3, in which case 5609 // the VF=2, while v2i128 is an unsupported MVT vector type 5610 // (see MachineValueType.h::getVectorVT()). 5611 if (!LegalVT.isVector()) 5612 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5613 Alignment, AddressSpace, CostKind); 5614 5615 unsigned VF = VecTy->getNumElements() / Factor; 5616 Type *ScalarTy = VecTy->getElementType(); 5617 // Deduplicate entries, model floats/pointers as appropriately-sized integers. 5618 if (!ScalarTy->isIntegerTy()) 5619 ScalarTy = 5620 Type::getIntNTy(ScalarTy->getContext(), DL.getTypeSizeInBits(ScalarTy)); 5621 5622 // Get the cost of all the memory operations. 5623 // FIXME: discount dead loads. 5624 InstructionCost MemOpCosts = getMemoryOpCost( 5625 Opcode, VecTy, MaybeAlign(Alignment), AddressSpace, CostKind); 5626 5627 auto *VT = FixedVectorType::get(ScalarTy, VF); 5628 EVT ETy = TLI->getValueType(DL, VT); 5629 if (!ETy.isSimple()) 5630 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5631 Alignment, AddressSpace, CostKind); 5632 5633 // TODO: Complete for other data-types and strides. 5634 // Each combination of Stride, element bit width and VF results in a different 5635 // sequence; The cost tables are therefore accessed with: 5636 // Factor (stride) and VectorType=VFxiN. 5637 // The Cost accounts only for the shuffle sequence; 5638 // The cost of the loads/stores is accounted for separately. 5639 // 5640 static const CostTblEntry AVX2InterleavedLoadTbl[] = { 5641 {2, MVT::v2i8, 2}, // (load 4i8 and) deinterleave into 2 x 2i8 5642 {2, MVT::v4i8, 2}, // (load 8i8 and) deinterleave into 2 x 4i8 5643 {2, MVT::v8i8, 2}, // (load 16i8 and) deinterleave into 2 x 8i8 5644 {2, MVT::v16i8, 4}, // (load 32i8 and) deinterleave into 2 x 16i8 5645 {2, MVT::v32i8, 6}, // (load 64i8 and) deinterleave into 2 x 32i8 5646 5647 {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16 5648 {2, MVT::v16i16, 9}, // (load 32i16 and) deinterleave into 2 x 16i16 5649 {2, MVT::v32i16, 18}, // (load 64i16 and) deinterleave into 2 x 32i16 5650 5651 {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32 5652 {2, MVT::v16i32, 8}, // (load 32i32 and) deinterleave into 2 x 16i32 5653 {2, MVT::v32i32, 16}, // (load 64i32 and) deinterleave into 2 x 32i32 5654 5655 {2, MVT::v4i64, 4}, // (load 8i64 and) deinterleave into 2 x 4i64 5656 {2, MVT::v8i64, 8}, // (load 16i64 and) deinterleave into 2 x 8i64 5657 {2, MVT::v16i64, 16}, // (load 32i64 and) deinterleave into 2 x 16i64 5658 {2, MVT::v32i64, 32}, // (load 64i64 and) deinterleave into 2 x 32i64 5659 5660 {3, MVT::v2i8, 3}, // (load 6i8 and) deinterleave into 3 x 2i8 5661 {3, MVT::v4i8, 3}, // (load 12i8 and) deinterleave into 3 x 4i8 5662 {3, MVT::v8i8, 6}, // (load 24i8 and) deinterleave into 3 x 8i8 5663 {3, MVT::v16i8, 11}, // (load 48i8 and) deinterleave into 3 x 16i8 5664 {3, MVT::v32i8, 14}, // (load 96i8 and) deinterleave into 3 x 32i8 5665 5666 {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 5667 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 5668 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 5669 {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 5670 {3, MVT::v32i16, 56}, // (load 96i16 and) deinterleave into 3 x 32i16 5671 5672 {3, MVT::v2i32, 3}, // (load 6i32 and) deinterleave into 3 x 2i32 5673 {3, MVT::v4i32, 3}, // (load 12i32 and) deinterleave into 3 x 4i32 5674 {3, MVT::v8i32, 7}, // (load 24i32 and) deinterleave into 3 x 8i32 5675 {3, MVT::v16i32, 14}, // (load 48i32 and) deinterleave into 3 x 16i32 5676 {3, MVT::v32i32, 32}, // (load 96i32 and) deinterleave into 3 x 32i32 5677 5678 {3, MVT::v2i64, 1}, // (load 6i64 and) deinterleave into 3 x 2i64 5679 {3, MVT::v4i64, 5}, // (load 12i64 and) deinterleave into 3 x 4i64 5680 {3, MVT::v8i64, 10}, // (load 24i64 and) deinterleave into 3 x 8i64 5681 {3, MVT::v16i64, 20}, // (load 48i64 and) deinterleave into 3 x 16i64 5682 5683 {4, MVT::v2i8, 4}, // (load 8i8 and) deinterleave into 4 x 2i8 5684 {4, MVT::v4i8, 4}, // (load 16i8 and) deinterleave into 4 x 4i8 5685 {4, MVT::v8i8, 12}, // (load 32i8 and) deinterleave into 4 x 8i8 5686 {4, MVT::v16i8, 24}, // (load 64i8 and) deinterleave into 4 x 16i8 5687 {4, MVT::v32i8, 56}, // (load 128i8 and) deinterleave into 4 x 32i8 5688 5689 {4, MVT::v2i16, 6}, // (load 8i16 and) deinterleave into 4 x 2i16 5690 {4, MVT::v4i16, 17}, // (load 16i16 and) deinterleave into 4 x 4i16 5691 {4, MVT::v8i16, 33}, // (load 32i16 and) deinterleave into 4 x 8i16 5692 {4, MVT::v16i16, 75}, // (load 64i16 and) deinterleave into 4 x 16i16 5693 {4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16 5694 5695 {4, MVT::v2i32, 4}, // (load 8i32 and) deinterleave into 4 x 2i32 5696 {4, MVT::v4i32, 8}, // (load 16i32 and) deinterleave into 4 x 4i32 5697 {4, MVT::v8i32, 16}, // (load 32i32 and) deinterleave into 4 x 8i32 5698 {4, MVT::v16i32, 32}, // (load 64i32 and) deinterleave into 4 x 16i32 5699 {4, MVT::v32i32, 68}, // (load 128i32 and) deinterleave into 4 x 32i32 5700 5701 {4, MVT::v2i64, 6}, // (load 8i64 and) deinterleave into 4 x 2i64 5702 {4, MVT::v4i64, 8}, // (load 16i64 and) deinterleave into 4 x 4i64 5703 {4, MVT::v8i64, 20}, // (load 32i64 and) deinterleave into 4 x 8i64 5704 {4, MVT::v16i64, 40}, // (load 64i64 and) deinterleave into 4 x 16i64 5705 5706 {6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8 5707 {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8 5708 {6, MVT::v8i8, 18}, // (load 48i8 and) deinterleave into 6 x 8i8 5709 {6, MVT::v16i8, 43}, // (load 96i8 and) deinterleave into 6 x 16i8 5710 {6, MVT::v32i8, 82}, // (load 192i8 and) deinterleave into 6 x 32i8 5711 5712 {6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16 5713 {6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16 5714 {6, MVT::v8i16, 39}, // (load 48i16 and) deinterleave into 6 x 8i16 5715 {6, MVT::v16i16, 106}, // (load 96i16 and) deinterleave into 6 x 16i16 5716 {6, MVT::v32i16, 212}, // (load 192i16 and) deinterleave into 6 x 32i16 5717 5718 {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 5719 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 5720 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 5721 {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 5722 5723 {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64 5724 {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64 5725 {6, MVT::v8i64, 36}, // (load 48i64 and) deinterleave into 6 x 8i64 5726 5727 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 5728 }; 5729 5730 static const CostTblEntry SSSE3InterleavedLoadTbl[] = { 5731 {2, MVT::v4i16, 2}, // (load 8i16 and) deinterleave into 2 x 4i16 5732 }; 5733 5734 static const CostTblEntry SSE2InterleavedLoadTbl[] = { 5735 {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16 5736 {2, MVT::v4i16, 7}, // (load 8i16 and) deinterleave into 2 x 4i16 5737 5738 {2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32 5739 {2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32 5740 5741 {2, MVT::v2i64, 2}, // (load 4i64 and) deinterleave into 2 x 2i64 5742 }; 5743 5744 static const CostTblEntry AVX2InterleavedStoreTbl[] = { 5745 {2, MVT::v16i8, 3}, // interleave 2 x 16i8 into 32i8 (and store) 5746 {2, MVT::v32i8, 4}, // interleave 2 x 32i8 into 64i8 (and store) 5747 5748 {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store) 5749 {2, MVT::v16i16, 4}, // interleave 2 x 16i16 into 32i16 (and store) 5750 {2, MVT::v32i16, 8}, // interleave 2 x 32i16 into 64i16 (and store) 5751 5752 {2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store) 5753 {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store) 5754 {2, MVT::v16i32, 8}, // interleave 2 x 16i32 into 32i32 (and store) 5755 {2, MVT::v32i32, 16}, // interleave 2 x 32i32 into 64i32 (and store) 5756 5757 {2, MVT::v2i64, 2}, // interleave 2 x 2i64 into 4i64 (and store) 5758 {2, MVT::v4i64, 4}, // interleave 2 x 4i64 into 8i64 (and store) 5759 {2, MVT::v8i64, 8}, // interleave 2 x 8i64 into 16i64 (and store) 5760 {2, MVT::v16i64, 16}, // interleave 2 x 16i64 into 32i64 (and store) 5761 {2, MVT::v32i64, 32}, // interleave 2 x 32i64 into 64i64 (and store) 5762 5763 {3, MVT::v2i8, 4}, // interleave 3 x 2i8 into 6i8 (and store) 5764 {3, MVT::v4i8, 4}, // interleave 3 x 4i8 into 12i8 (and store) 5765 {3, MVT::v8i8, 6}, // interleave 3 x 8i8 into 24i8 (and store) 5766 {3, MVT::v16i8, 11}, // interleave 3 x 16i8 into 48i8 (and store) 5767 {3, MVT::v32i8, 13}, // interleave 3 x 32i8 into 96i8 (and store) 5768 5769 {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) 5770 {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) 5771 {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) 5772 {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) 5773 {3, MVT::v32i16, 54}, // interleave 3 x 32i16 into 96i16 (and store) 5774 5775 {3, MVT::v2i32, 4}, // interleave 3 x 2i32 into 6i32 (and store) 5776 {3, MVT::v4i32, 5}, // interleave 3 x 4i32 into 12i32 (and store) 5777 {3, MVT::v8i32, 11}, // interleave 3 x 8i32 into 24i32 (and store) 5778 {3, MVT::v16i32, 22}, // interleave 3 x 16i32 into 48i32 (and store) 5779 {3, MVT::v32i32, 48}, // interleave 3 x 32i32 into 96i32 (and store) 5780 5781 {3, MVT::v2i64, 4}, // interleave 3 x 2i64 into 6i64 (and store) 5782 {3, MVT::v4i64, 6}, // interleave 3 x 4i64 into 12i64 (and store) 5783 {3, MVT::v8i64, 12}, // interleave 3 x 8i64 into 24i64 (and store) 5784 {3, MVT::v16i64, 24}, // interleave 3 x 16i64 into 48i64 (and store) 5785 5786 {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) 5787 {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) 5788 {4, MVT::v8i8, 4}, // interleave 4 x 8i8 into 32i8 (and store) 5789 {4, MVT::v16i8, 8}, // interleave 4 x 16i8 into 64i8 (and store) 5790 {4, MVT::v32i8, 12}, // interleave 4 x 32i8 into 128i8 (and store) 5791 5792 {4, MVT::v2i16, 2}, // interleave 4 x 2i16 into 8i16 (and store) 5793 {4, MVT::v4i16, 6}, // interleave 4 x 4i16 into 16i16 (and store) 5794 {4, MVT::v8i16, 10}, // interleave 4 x 8i16 into 32i16 (and store) 5795 {4, MVT::v16i16, 32}, // interleave 4 x 16i16 into 64i16 (and store) 5796 {4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store) 5797 5798 {4, MVT::v2i32, 5}, // interleave 4 x 2i32 into 8i32 (and store) 5799 {4, MVT::v4i32, 6}, // interleave 4 x 4i32 into 16i32 (and store) 5800 {4, MVT::v8i32, 16}, // interleave 4 x 8i32 into 32i32 (and store) 5801 {4, MVT::v16i32, 32}, // interleave 4 x 16i32 into 64i32 (and store) 5802 {4, MVT::v32i32, 64}, // interleave 4 x 32i32 into 128i32 (and store) 5803 5804 {4, MVT::v2i64, 6}, // interleave 4 x 2i64 into 8i64 (and store) 5805 {4, MVT::v4i64, 8}, // interleave 4 x 4i64 into 16i64 (and store) 5806 {4, MVT::v8i64, 20}, // interleave 4 x 8i64 into 32i64 (and store) 5807 {4, MVT::v16i64, 40}, // interleave 4 x 16i64 into 64i64 (and store) 5808 5809 {6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store) 5810 {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store) 5811 {6, MVT::v8i8, 16}, // interleave 6 x 8i8 into 48i8 (and store) 5812 {6, MVT::v16i8, 27}, // interleave 6 x 16i8 into 96i8 (and store) 5813 {6, MVT::v32i8, 90}, // interleave 6 x 32i8 into 192i8 (and store) 5814 5815 {6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store) 5816 {6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store) 5817 {6, MVT::v8i16, 21}, // interleave 6 x 8i16 into 48i16 (and store) 5818 {6, MVT::v16i16, 58}, // interleave 6 x 16i16 into 96i16 (and store) 5819 {6, MVT::v32i16, 90}, // interleave 6 x 32i16 into 192i16 (and store) 5820 5821 {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) 5822 {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) 5823 {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) 5824 {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) 5825 5826 {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store) 5827 {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store) 5828 {6, MVT::v8i64, 30}, // interleave 6 x 8i64 into 48i64 (and store) 5829 }; 5830 5831 static const CostTblEntry SSE2InterleavedStoreTbl[] = { 5832 {2, MVT::v2i8, 1}, // interleave 2 x 2i8 into 4i8 (and store) 5833 {2, MVT::v4i8, 1}, // interleave 2 x 4i8 into 8i8 (and store) 5834 {2, MVT::v8i8, 1}, // interleave 2 x 8i8 into 16i8 (and store) 5835 5836 {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store) 5837 {2, MVT::v4i16, 1}, // interleave 2 x 4i16 into 8i16 (and store) 5838 5839 {2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store) 5840 }; 5841 5842 if (Opcode == Instruction::Load) { 5843 auto GetDiscountedCost = [Factor, NumMembers = Indices.size(), 5844 MemOpCosts](const CostTblEntry *Entry) { 5845 // NOTE: this is just an approximation! 5846 // It can over/under -estimate the cost! 5847 return MemOpCosts + divideCeil(NumMembers * Entry->Cost, Factor); 5848 }; 5849 5850 if (ST->hasAVX2()) 5851 if (const auto *Entry = CostTableLookup(AVX2InterleavedLoadTbl, Factor, 5852 ETy.getSimpleVT())) 5853 return GetDiscountedCost(Entry); 5854 5855 if (ST->hasSSSE3()) 5856 if (const auto *Entry = CostTableLookup(SSSE3InterleavedLoadTbl, Factor, 5857 ETy.getSimpleVT())) 5858 return GetDiscountedCost(Entry); 5859 5860 if (ST->hasSSE2()) 5861 if (const auto *Entry = CostTableLookup(SSE2InterleavedLoadTbl, Factor, 5862 ETy.getSimpleVT())) 5863 return GetDiscountedCost(Entry); 5864 } else { 5865 assert(Opcode == Instruction::Store && 5866 "Expected Store Instruction at this point"); 5867 assert((!Indices.size() || Indices.size() == Factor) && 5868 "Interleaved store only supports fully-interleaved groups."); 5869 if (ST->hasAVX2()) 5870 if (const auto *Entry = CostTableLookup(AVX2InterleavedStoreTbl, Factor, 5871 ETy.getSimpleVT())) 5872 return MemOpCosts + Entry->Cost; 5873 5874 if (ST->hasSSE2()) 5875 if (const auto *Entry = CostTableLookup(SSE2InterleavedStoreTbl, Factor, 5876 ETy.getSimpleVT())) 5877 return MemOpCosts + Entry->Cost; 5878 } 5879 5880 return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices, 5881 Alignment, AddressSpace, CostKind, 5882 UseMaskForCond, UseMaskForGaps); 5883 } 5884