1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
22 using namespace llvm;
23 
24 extern "C" void LLVMInitializeX86Target() {
25   // Register the target.
26   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
27   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
28 }
29 
30 void X86TargetMachine::anchor() { }
31 
32 static std::string computeDataLayout(const X86Subtarget &ST) {
33   // X86 is little endian
34   std::string Ret = "e";
35 
36   Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
37   // X86 and x32 have 32 bit pointers.
38   if (ST.isTarget64BitILP32() || !ST.is64Bit())
39     Ret += "-p:32:32";
40 
41   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42   if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC() ||
43       ST.isTargetNaCl())
44     Ret += "-i64:64";
45   else
46     Ret += "-f64:32:64";
47 
48   // Some ABIs align long double to 128 bits, others to 32.
49   if (ST.isTargetNaCl())
50     ; // No f80
51   else if (ST.is64Bit() || ST.isTargetDarwin())
52     Ret += "-f80:128";
53   else
54     Ret += "-f80:32";
55 
56   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
57   if (ST.is64Bit())
58     Ret += "-n8:16:32:64";
59   else
60     Ret += "-n8:16:32";
61 
62   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
63   if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC()))
64     Ret += "-S32";
65   else
66     Ret += "-S128";
67 
68   return Ret;
69 }
70 
71 /// X86TargetMachine ctor - Create an X86 target.
72 ///
73 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
74                                    StringRef CPU, StringRef FS,
75                                    const TargetOptions &Options,
76                                    Reloc::Model RM, CodeModel::Model CM,
77                                    CodeGenOpt::Level OL)
78   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
80     FrameLowering(*this, Subtarget),
81     InstrItins(Subtarget.getInstrItineraryData()),
82     DL(computeDataLayout(*getSubtargetImpl())),
83     InstrInfo(*this),
84     TLInfo(*this),
85     TSInfo(*this),
86     JITInfo(*this) {
87   // Determine the PICStyle based on the target selected.
88   if (getRelocationModel() == Reloc::Static) {
89     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
90     Subtarget.setPICStyle(PICStyles::None);
91   } else if (Subtarget.is64Bit()) {
92     // PIC in 64 bit mode is always rip-rel.
93     Subtarget.setPICStyle(PICStyles::RIPRel);
94   } else if (Subtarget.isTargetCOFF()) {
95     Subtarget.setPICStyle(PICStyles::None);
96   } else if (Subtarget.isTargetDarwin()) {
97     if (getRelocationModel() == Reloc::PIC_)
98       Subtarget.setPICStyle(PICStyles::StubPIC);
99     else {
100       assert(getRelocationModel() == Reloc::DynamicNoPIC);
101       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
102     }
103   } else if (Subtarget.isTargetELF()) {
104     Subtarget.setPICStyle(PICStyles::GOT);
105   }
106 
107   // default to hard float ABI
108   if (Options.FloatABIType == FloatABI::Default)
109     this->Options.FloatABIType = FloatABI::Hard;
110 
111   // Windows stack unwinder gets confused when execution flow "falls through"
112   // after a call to 'noreturn' function.
113   // To prevent that, we emit a trap for 'unreachable' IR instructions.
114   // (which on X86, happens to be the 'ud2' instruction)
115   if (Subtarget.isTargetWin64())
116     this->Options.TrapUnreachable = true;
117 
118   initAsmInfo();
119 }
120 
121 //===----------------------------------------------------------------------===//
122 // Command line options for x86
123 //===----------------------------------------------------------------------===//
124 static cl::opt<bool>
125 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
126   cl::desc("Minimize AVX to SSE transition penalty"),
127   cl::init(true));
128 
129 // Temporary option to control early if-conversion for x86 while adding machine
130 // models.
131 static cl::opt<bool>
132 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
133 	       cl::desc("Enable early if-conversion on X86"));
134 
135 //===----------------------------------------------------------------------===//
136 // X86 Analysis Pass Setup
137 //===----------------------------------------------------------------------===//
138 
139 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
140   // Add first the target-independent BasicTTI pass, then our X86 pass. This
141   // allows the X86 pass to delegate to the target independent layer when
142   // appropriate.
143   PM.add(createBasicTargetTransformInfoPass(this));
144   PM.add(createX86TargetTransformInfoPass(this));
145 }
146 
147 
148 //===----------------------------------------------------------------------===//
149 // Pass Pipeline Configuration
150 //===----------------------------------------------------------------------===//
151 
152 namespace {
153 /// X86 Code Generator Pass Configuration Options.
154 class X86PassConfig : public TargetPassConfig {
155 public:
156   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
157     : TargetPassConfig(TM, PM) {}
158 
159   X86TargetMachine &getX86TargetMachine() const {
160     return getTM<X86TargetMachine>();
161   }
162 
163   const X86Subtarget &getX86Subtarget() const {
164     return *getX86TargetMachine().getSubtargetImpl();
165   }
166 
167   bool addInstSelector() override;
168   bool addILPOpts() override;
169   bool addPreRegAlloc() override;
170   bool addPostRegAlloc() override;
171   bool addPreEmitPass() override;
172 };
173 } // namespace
174 
175 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
176   return new X86PassConfig(this, PM);
177 }
178 
179 bool X86PassConfig::addInstSelector() {
180   // Install an instruction selector.
181   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
182 
183   // For ELF, cleanup any local-dynamic TLS accesses.
184   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
185     addPass(createCleanupLocalDynamicTLSPass());
186 
187   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
188   if (!getX86Subtarget().is64Bit())
189     addPass(createGlobalBaseRegPass());
190 
191   return false;
192 }
193 
194 bool X86PassConfig::addILPOpts() {
195   if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
196     addPass(&EarlyIfConverterID);
197     return true;
198   }
199   return false;
200 }
201 
202 bool X86PassConfig::addPreRegAlloc() {
203   return false;  // -print-machineinstr shouldn't print after this.
204 }
205 
206 bool X86PassConfig::addPostRegAlloc() {
207   addPass(createX86FloatingPointStackifierPass());
208   return true;  // -print-machineinstr should print after this.
209 }
210 
211 bool X86PassConfig::addPreEmitPass() {
212   bool ShouldPrint = false;
213   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
214     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
215     ShouldPrint = true;
216   }
217 
218   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
219     addPass(createX86IssueVZeroUpperPass());
220     ShouldPrint = true;
221   }
222 
223   if (getOptLevel() != CodeGenOpt::None &&
224       getX86Subtarget().padShortFunctions()) {
225     addPass(createX86PadShortFunctions());
226     ShouldPrint = true;
227   }
228   if (getOptLevel() != CodeGenOpt::None &&
229       getX86Subtarget().LEAusesAG()){
230     addPass(createX86FixupLEAs());
231     ShouldPrint = true;
232   }
233 
234   return ShouldPrint;
235 }
236 
237 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
238                                       JITCodeEmitter &JCE) {
239   PM.add(createX86JITCodeEmitterPass(*this, JCE));
240 
241   return false;
242 }
243