1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 using namespace llvm;
26 
27 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
28                                cl::desc("Enable the machine combiner pass"),
29                                cl::init(true), cl::Hidden);
30 
31 namespace llvm {
32 void initializeWinEHStatePassPass(PassRegistry &);
33 }
34 
35 extern "C" void LLVMInitializeX86Target() {
36   // Register the target.
37   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
38   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
39 
40   PassRegistry &PR = *PassRegistry::getPassRegistry();
41   initializeWinEHStatePassPass(PR);
42 }
43 
44 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
45   if (TT.isOSBinFormatMachO()) {
46     if (TT.getArch() == Triple::x86_64)
47       return make_unique<X86_64MachoTargetObjectFile>();
48     return make_unique<TargetLoweringObjectFileMachO>();
49   }
50 
51   if (TT.isOSLinux() || TT.isOSNaCl())
52     return make_unique<X86LinuxNaClTargetObjectFile>();
53   if (TT.isOSBinFormatELF())
54     return make_unique<X86ELFTargetObjectFile>();
55   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
56     return make_unique<X86WindowsTargetObjectFile>();
57   if (TT.isOSBinFormatCOFF())
58     return make_unique<TargetLoweringObjectFileCOFF>();
59   llvm_unreachable("unknown subtarget type");
60 }
61 
62 static std::string computeDataLayout(const Triple &TT) {
63   // X86 is little endian
64   std::string Ret = "e";
65 
66   Ret += DataLayout::getManglingComponent(TT);
67   // X86 and x32 have 32 bit pointers.
68   if ((TT.isArch64Bit() &&
69        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
70       !TT.isArch64Bit())
71     Ret += "-p:32:32";
72 
73   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
74   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
75     Ret += "-i64:64";
76   else if (TT.isOSIAMCU())
77     Ret += "-i64:32-f64:32";
78   else
79     Ret += "-f64:32:64";
80 
81   // Some ABIs align long double to 128 bits, others to 32.
82   if (TT.isOSNaCl() || TT.isOSIAMCU())
83     ; // No f80
84   else if (TT.isArch64Bit() || TT.isOSDarwin())
85     Ret += "-f80:128";
86   else
87     Ret += "-f80:32";
88 
89   if (TT.isOSIAMCU())
90     Ret += "-f128:32";
91 
92   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
93   if (TT.isArch64Bit())
94     Ret += "-n8:16:32:64";
95   else
96     Ret += "-n8:16:32";
97 
98   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
99   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
100     Ret += "-a:0:32-S32";
101   else
102     Ret += "-S128";
103 
104   return Ret;
105 }
106 
107 /// X86TargetMachine ctor - Create an X86 target.
108 ///
109 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
110                                    StringRef CPU, StringRef FS,
111                                    const TargetOptions &Options,
112                                    Reloc::Model RM, CodeModel::Model CM,
113                                    CodeGenOpt::Level OL)
114     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
115                         OL),
116       TLOF(createTLOF(getTargetTriple())),
117       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
118   // Windows stack unwinder gets confused when execution flow "falls through"
119   // after a call to 'noreturn' function.
120   // To prevent that, we emit a trap for 'unreachable' IR instructions.
121   // (which on X86, happens to be the 'ud2' instruction)
122   // On PS4, the "return address" of a 'noreturn' call must still be within
123   // the calling function, and TrapUnreachable is an easy way to get that.
124   if (Subtarget.isTargetWin64() || Subtarget.isTargetPS4())
125     this->Options.TrapUnreachable = true;
126 
127   // By default (and when -ffast-math is on), enable estimate codegen for
128   // everything except scalar division. By default, use 1 refinement step for
129   // all operations. Defaults may be overridden by using command-line options.
130   // Scalar division estimates are disabled because they break too much
131   // real-world code. These defaults match GCC behavior.
132   this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
133   this->Options.Reciprocals.setDefaults("divf", false, 1);
134   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
135   this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
136 
137   initAsmInfo();
138 }
139 
140 X86TargetMachine::~X86TargetMachine() {}
141 
142 const X86Subtarget *
143 X86TargetMachine::getSubtargetImpl(const Function &F) const {
144   Attribute CPUAttr = F.getFnAttribute("target-cpu");
145   Attribute FSAttr = F.getFnAttribute("target-features");
146 
147   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
148                         ? CPUAttr.getValueAsString().str()
149                         : TargetCPU;
150   std::string FS = !FSAttr.hasAttribute(Attribute::None)
151                        ? FSAttr.getValueAsString().str()
152                        : TargetFS;
153 
154   // FIXME: This is related to the code below to reset the target options,
155   // we need to know whether or not the soft float flag is set on the
156   // function before we can generate a subtarget. We also need to use
157   // it as a key for the subtarget since that can be the only difference
158   // between two functions.
159   bool SoftFloat =
160       F.hasFnAttribute("use-soft-float") &&
161       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
162   // If the soft float attribute is set on the function turn on the soft float
163   // subtarget feature.
164   if (SoftFloat)
165     FS += FS.empty() ? "+soft-float" : ",+soft-float";
166 
167   auto &I = SubtargetMap[CPU + FS];
168   if (!I) {
169     // This needs to be done before we create a new subtarget since any
170     // creation will depend on the TM and the code generation flags on the
171     // function that reside in TargetOptions.
172     resetTargetOptions(F);
173     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
174                                         Options.StackAlignmentOverride);
175   }
176   return I.get();
177 }
178 
179 //===----------------------------------------------------------------------===//
180 // Command line options for x86
181 //===----------------------------------------------------------------------===//
182 static cl::opt<bool>
183 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
184   cl::desc("Minimize AVX to SSE transition penalty"),
185   cl::init(true));
186 
187 //===----------------------------------------------------------------------===//
188 // X86 TTI query.
189 //===----------------------------------------------------------------------===//
190 
191 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
192   return TargetIRAnalysis([this](const Function &F) {
193     return TargetTransformInfo(X86TTIImpl(this, F));
194   });
195 }
196 
197 
198 //===----------------------------------------------------------------------===//
199 // Pass Pipeline Configuration
200 //===----------------------------------------------------------------------===//
201 
202 namespace {
203 /// X86 Code Generator Pass Configuration Options.
204 class X86PassConfig : public TargetPassConfig {
205 public:
206   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
207     : TargetPassConfig(TM, PM) {}
208 
209   X86TargetMachine &getX86TargetMachine() const {
210     return getTM<X86TargetMachine>();
211   }
212 
213   void addIRPasses() override;
214   bool addInstSelector() override;
215   bool addILPOpts() override;
216   bool addPreISel() override;
217   void addPreRegAlloc() override;
218   void addPostRegAlloc() override;
219   void addPreEmitPass() override;
220   void addPreSched2() override;
221 };
222 } // namespace
223 
224 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
225   return new X86PassConfig(this, PM);
226 }
227 
228 void X86PassConfig::addIRPasses() {
229   addPass(createAtomicExpandPass(&getX86TargetMachine()));
230 
231   TargetPassConfig::addIRPasses();
232 }
233 
234 bool X86PassConfig::addInstSelector() {
235   // Install an instruction selector.
236   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
237 
238   // For ELF, cleanup any local-dynamic TLS accesses.
239   if (TM->getTargetTriple().isOSBinFormatELF() &&
240       getOptLevel() != CodeGenOpt::None)
241     addPass(createCleanupLocalDynamicTLSPass());
242 
243   addPass(createX86GlobalBaseRegPass());
244 
245   return false;
246 }
247 
248 bool X86PassConfig::addILPOpts() {
249   addPass(&EarlyIfConverterID);
250   if (EnableMachineCombinerPass)
251     addPass(&MachineCombinerID);
252   return true;
253 }
254 
255 bool X86PassConfig::addPreISel() {
256   // Only add this pass for 32-bit x86 Windows.
257   const Triple &TT = TM->getTargetTriple();
258   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
259     addPass(createX86WinEHStatePass());
260   return true;
261 }
262 
263 void X86PassConfig::addPreRegAlloc() {
264   if (getOptLevel() != CodeGenOpt::None)
265     addPass(createX86OptimizeLEAs());
266 
267   addPass(createX86CallFrameOptimization());
268 }
269 
270 void X86PassConfig::addPostRegAlloc() {
271   addPass(createX86FloatingPointStackifierPass());
272 }
273 
274 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
275 
276 void X86PassConfig::addPreEmitPass() {
277   if (getOptLevel() != CodeGenOpt::None)
278     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
279 
280   if (UseVZeroUpper)
281     addPass(createX86IssueVZeroUpperPass());
282 
283   if (getOptLevel() != CodeGenOpt::None) {
284     addPass(createX86FixupBWInsts());
285     addPass(createX86PadShortFunctions());
286     addPass(createX86FixupLEAs());
287   }
288 }
289