1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
60                                cl::desc("Enable the conditional branch "
61                                         "folding pass"),
62                                cl::init(false), cl::Hidden);
63 
64 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
65   // Register the target.
66   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
67   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
68 
69   PassRegistry &PR = *PassRegistry::getPassRegistry();
70   initializeGlobalISel(PR);
71   initializeWinEHStatePassPass(PR);
72   initializeFixupBWInstPassPass(PR);
73   initializeEvexToVexInstPassPass(PR);
74   initializeFixupLEAPassPass(PR);
75   initializeFPSPass(PR);
76   initializeX86CallFrameOptimizationPass(PR);
77   initializeX86CmovConverterPassPass(PR);
78   initializeX86ExpandPseudoPass(PR);
79   initializeX86ExecutionDomainFixPass(PR);
80   initializeX86DomainReassignmentPass(PR);
81   initializeX86AvoidSFBPassPass(PR);
82   initializeX86AvoidTrailingCallPassPass(PR);
83   initializeX86SpeculativeLoadHardeningPassPass(PR);
84   initializeX86FlagsCopyLoweringPassPass(PR);
85   initializeX86CondBrFoldingPassPass(PR);
86   initializeX86OptimizeLEAPassPass(PR);
87   initializeX86PartialReductionPass(PR);
88 }
89 
90 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
91   if (TT.isOSBinFormatMachO()) {
92     if (TT.getArch() == Triple::x86_64)
93       return std::make_unique<X86_64MachoTargetObjectFile>();
94     return std::make_unique<TargetLoweringObjectFileMachO>();
95   }
96 
97   if (TT.isOSBinFormatCOFF())
98     return std::make_unique<TargetLoweringObjectFileCOFF>();
99   return std::make_unique<X86ELFTargetObjectFile>();
100 }
101 
102 static std::string computeDataLayout(const Triple &TT) {
103   // X86 is little endian
104   std::string Ret = "e";
105 
106   Ret += DataLayout::getManglingComponent(TT);
107   // X86 and x32 have 32 bit pointers.
108   if ((TT.isArch64Bit() &&
109        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
110       !TT.isArch64Bit())
111     Ret += "-p:32:32";
112 
113   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
114   Ret += "-p270:32:32-p271:32:32-p272:64:64";
115 
116   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
117   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
118     Ret += "-i64:64";
119   else if (TT.isOSIAMCU())
120     Ret += "-i64:32-f64:32";
121   else
122     Ret += "-f64:32:64";
123 
124   // Some ABIs align long double to 128 bits, others to 32.
125   if (TT.isOSNaCl() || TT.isOSIAMCU())
126     ; // No f80
127   else if (TT.isArch64Bit() || TT.isOSDarwin())
128     Ret += "-f80:128";
129   else
130     Ret += "-f80:32";
131 
132   if (TT.isOSIAMCU())
133     Ret += "-f128:32";
134 
135   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
136   if (TT.isArch64Bit())
137     Ret += "-n8:16:32:64";
138   else
139     Ret += "-n8:16:32";
140 
141   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
142   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
143     Ret += "-a:0:32-S32";
144   else
145     Ret += "-S128";
146 
147   return Ret;
148 }
149 
150 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
151                                            bool JIT,
152                                            Optional<Reloc::Model> RM) {
153   bool is64Bit = TT.getArch() == Triple::x86_64;
154   if (!RM.hasValue()) {
155     // JIT codegen should use static relocations by default, since it's
156     // typically executed in process and not relocatable.
157     if (JIT)
158       return Reloc::Static;
159 
160     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
161     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
162     // use static relocation model by default.
163     if (TT.isOSDarwin()) {
164       if (is64Bit)
165         return Reloc::PIC_;
166       return Reloc::DynamicNoPIC;
167     }
168     if (TT.isOSWindows() && is64Bit)
169       return Reloc::PIC_;
170     return Reloc::Static;
171   }
172 
173   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
174   // is defined as a model for code which may be used in static or dynamic
175   // executables but not necessarily a shared library. On X86-32 we just
176   // compile in -static mode, in x86-64 we use PIC.
177   if (*RM == Reloc::DynamicNoPIC) {
178     if (is64Bit)
179       return Reloc::PIC_;
180     if (!TT.isOSDarwin())
181       return Reloc::Static;
182   }
183 
184   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
185   // the Mach-O file format doesn't support it.
186   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
187     return Reloc::PIC_;
188 
189   return *RM;
190 }
191 
192 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
193                                                  bool JIT, bool Is64Bit) {
194   if (CM) {
195     if (*CM == CodeModel::Tiny)
196       report_fatal_error("Target does not support the tiny CodeModel", false);
197     return *CM;
198   }
199   if (JIT)
200     return Is64Bit ? CodeModel::Large : CodeModel::Small;
201   return CodeModel::Small;
202 }
203 
204 /// Create an X86 target.
205 ///
206 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
207                                    StringRef CPU, StringRef FS,
208                                    const TargetOptions &Options,
209                                    Optional<Reloc::Model> RM,
210                                    Optional<CodeModel::Model> CM,
211                                    CodeGenOpt::Level OL, bool JIT)
212     : LLVMTargetMachine(
213           T, computeDataLayout(TT), TT, CPU, FS, Options,
214           getEffectiveRelocModel(TT, JIT, RM),
215           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
216           OL),
217       TLOF(createTLOF(getTargetTriple())) {
218   // On PS4, the "return address" of a 'noreturn' call must still be within
219   // the calling function, and TrapUnreachable is an easy way to get that.
220   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
221     this->Options.TrapUnreachable = true;
222     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
223   }
224 
225   setMachineOutliner(true);
226 
227   // x86 supports the debug entry values.
228   setSupportsDebugEntryValues(true);
229 
230   initAsmInfo();
231 }
232 
233 X86TargetMachine::~X86TargetMachine() = default;
234 
235 const X86Subtarget *
236 X86TargetMachine::getSubtargetImpl(const Function &F) const {
237   Attribute CPUAttr = F.getFnAttribute("target-cpu");
238   Attribute FSAttr = F.getFnAttribute("target-features");
239 
240   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
241                       ? CPUAttr.getValueAsString()
242                       : (StringRef)TargetCPU;
243   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
244                      ? FSAttr.getValueAsString()
245                      : (StringRef)TargetFS;
246 
247   SmallString<512> Key;
248   Key.reserve(CPU.size() + FS.size());
249   Key += CPU;
250   Key += FS;
251 
252   // FIXME: This is related to the code below to reset the target options,
253   // we need to know whether or not the soft float flag is set on the
254   // function before we can generate a subtarget. We also need to use
255   // it as a key for the subtarget since that can be the only difference
256   // between two functions.
257   bool SoftFloat =
258       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
259   // If the soft float attribute is set on the function turn on the soft float
260   // subtarget feature.
261   if (SoftFloat)
262     Key += FS.empty() ? "+soft-float" : ",+soft-float";
263 
264   // Keep track of the key width after all features are added so we can extract
265   // the feature string out later.
266   unsigned CPUFSWidth = Key.size();
267 
268   // Extract prefer-vector-width attribute.
269   unsigned PreferVectorWidthOverride = 0;
270   if (F.hasFnAttribute("prefer-vector-width")) {
271     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
272     unsigned Width;
273     if (!Val.getAsInteger(0, Width)) {
274       Key += ",prefer-vector-width=";
275       Key += Val;
276       PreferVectorWidthOverride = Width;
277     }
278   }
279 
280   // Extract min-legal-vector-width attribute.
281   unsigned RequiredVectorWidth = UINT32_MAX;
282   if (F.hasFnAttribute("min-legal-vector-width")) {
283     StringRef Val =
284         F.getFnAttribute("min-legal-vector-width").getValueAsString();
285     unsigned Width;
286     if (!Val.getAsInteger(0, Width)) {
287       Key += ",min-legal-vector-width=";
288       Key += Val;
289       RequiredVectorWidth = Width;
290     }
291   }
292 
293   // Extracted here so that we make sure there is backing for the StringRef. If
294   // we assigned earlier, its possible the SmallString reallocated leaving a
295   // dangling StringRef.
296   FS = Key.slice(CPU.size(), CPUFSWidth);
297 
298   auto &I = SubtargetMap[Key];
299   if (!I) {
300     // This needs to be done before we create a new subtarget since any
301     // creation will depend on the TM and the code generation flags on the
302     // function that reside in TargetOptions.
303     resetTargetOptions(F);
304     I = std::make_unique<X86Subtarget>(
305         TargetTriple, CPU, FS, *this,
306         MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
307         RequiredVectorWidth);
308   }
309   return I.get();
310 }
311 
312 //===----------------------------------------------------------------------===//
313 // Command line options for x86
314 //===----------------------------------------------------------------------===//
315 static cl::opt<bool>
316 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
317   cl::desc("Minimize AVX to SSE transition penalty"),
318   cl::init(true));
319 
320 //===----------------------------------------------------------------------===//
321 // X86 TTI query.
322 //===----------------------------------------------------------------------===//
323 
324 TargetTransformInfo
325 X86TargetMachine::getTargetTransformInfo(const Function &F) {
326   return TargetTransformInfo(X86TTIImpl(this, F));
327 }
328 
329 //===----------------------------------------------------------------------===//
330 // Pass Pipeline Configuration
331 //===----------------------------------------------------------------------===//
332 
333 namespace {
334 
335 /// X86 Code Generator Pass Configuration Options.
336 class X86PassConfig : public TargetPassConfig {
337 public:
338   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
339     : TargetPassConfig(TM, PM) {}
340 
341   X86TargetMachine &getX86TargetMachine() const {
342     return getTM<X86TargetMachine>();
343   }
344 
345   ScheduleDAGInstrs *
346   createMachineScheduler(MachineSchedContext *C) const override {
347     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
348     DAG->addMutation(createX86MacroFusionDAGMutation());
349     return DAG;
350   }
351 
352   ScheduleDAGInstrs *
353   createPostMachineScheduler(MachineSchedContext *C) const override {
354     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
355     DAG->addMutation(createX86MacroFusionDAGMutation());
356     return DAG;
357   }
358 
359   void addIRPasses() override;
360   bool addInstSelector() override;
361   bool addIRTranslator() override;
362   bool addLegalizeMachineIR() override;
363   bool addRegBankSelect() override;
364   bool addGlobalInstructionSelect() override;
365   bool addILPOpts() override;
366   bool addPreISel() override;
367   void addMachineSSAOptimization() override;
368   void addPreRegAlloc() override;
369   void addPostRegAlloc() override;
370   void addPreEmitPass() override;
371   void addPreEmitPass2() override;
372   void addPreSched2() override;
373 
374   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
375 };
376 
377 class X86ExecutionDomainFix : public ExecutionDomainFix {
378 public:
379   static char ID;
380   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
381   StringRef getPassName() const override {
382     return "X86 Execution Dependency Fix";
383   }
384 };
385 char X86ExecutionDomainFix::ID;
386 
387 } // end anonymous namespace
388 
389 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
390   "X86 Execution Domain Fix", false, false)
391 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
392 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
393   "X86 Execution Domain Fix", false, false)
394 
395 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
396   return new X86PassConfig(*this, PM);
397 }
398 
399 void X86PassConfig::addIRPasses() {
400   addPass(createAtomicExpandPass());
401 
402   TargetPassConfig::addIRPasses();
403 
404   if (TM->getOptLevel() != CodeGenOpt::None) {
405     addPass(createInterleavedAccessPass());
406     addPass(createX86PartialReductionPass());
407   }
408 
409   // Add passes that handle indirect branch removal and insertion of a retpoline
410   // thunk. These will be a no-op unless a function subtarget has the retpoline
411   // feature enabled.
412   addPass(createIndirectBrExpandPass());
413 
414   // Add Control Flow Guard checks.
415   const Triple &TT = TM->getTargetTriple();
416   if (TT.isOSWindows()) {
417     if (TT.getArch() == Triple::x86_64) {
418       addPass(createCFGuardDispatchPass());
419     } else {
420       addPass(createCFGuardCheckPass());
421     }
422   }
423 }
424 
425 bool X86PassConfig::addInstSelector() {
426   // Install an instruction selector.
427   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
428 
429   // For ELF, cleanup any local-dynamic TLS accesses.
430   if (TM->getTargetTriple().isOSBinFormatELF() &&
431       getOptLevel() != CodeGenOpt::None)
432     addPass(createCleanupLocalDynamicTLSPass());
433 
434   addPass(createX86GlobalBaseRegPass());
435   return false;
436 }
437 
438 bool X86PassConfig::addIRTranslator() {
439   addPass(new IRTranslator());
440   return false;
441 }
442 
443 bool X86PassConfig::addLegalizeMachineIR() {
444   addPass(new Legalizer());
445   return false;
446 }
447 
448 bool X86PassConfig::addRegBankSelect() {
449   addPass(new RegBankSelect());
450   return false;
451 }
452 
453 bool X86PassConfig::addGlobalInstructionSelect() {
454   addPass(new InstructionSelect());
455   return false;
456 }
457 
458 bool X86PassConfig::addILPOpts() {
459   if (EnableCondBrFoldingPass)
460     addPass(createX86CondBrFolding());
461   addPass(&EarlyIfConverterID);
462   if (EnableMachineCombinerPass)
463     addPass(&MachineCombinerID);
464   addPass(createX86CmovConverterPass());
465   return true;
466 }
467 
468 bool X86PassConfig::addPreISel() {
469   // Only add this pass for 32-bit x86 Windows.
470   const Triple &TT = TM->getTargetTriple();
471   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
472     addPass(createX86WinEHStatePass());
473   return true;
474 }
475 
476 void X86PassConfig::addPreRegAlloc() {
477   if (getOptLevel() != CodeGenOpt::None) {
478     addPass(&LiveRangeShrinkID);
479     addPass(createX86FixupSetCC());
480     addPass(createX86OptimizeLEAs());
481     addPass(createX86CallFrameOptimization());
482     addPass(createX86AvoidStoreForwardingBlocks());
483   }
484 
485   addPass(createX86SpeculativeLoadHardeningPass());
486   addPass(createX86FlagsCopyLoweringPass());
487   addPass(createX86WinAllocaExpander());
488 }
489 void X86PassConfig::addMachineSSAOptimization() {
490   addPass(createX86DomainReassignmentPass());
491   TargetPassConfig::addMachineSSAOptimization();
492 }
493 
494 void X86PassConfig::addPostRegAlloc() {
495   addPass(createX86FloatingPointStackifierPass());
496 }
497 
498 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
499 
500 void X86PassConfig::addPreEmitPass() {
501   if (getOptLevel() != CodeGenOpt::None) {
502     addPass(new X86ExecutionDomainFix());
503     addPass(createBreakFalseDeps());
504   }
505 
506   addPass(createX86IndirectBranchTrackingPass());
507 
508   if (UseVZeroUpper)
509     addPass(createX86IssueVZeroUpperPass());
510 
511   if (getOptLevel() != CodeGenOpt::None) {
512     addPass(createX86FixupBWInsts());
513     addPass(createX86PadShortFunctions());
514     addPass(createX86FixupLEAs());
515     addPass(createX86EvexToVexInsts());
516   }
517   addPass(createX86DiscriminateMemOpsPass());
518   addPass(createX86InsertPrefetchPass());
519   addPass(createX86InsertX87waitPass());
520 }
521 
522 void X86PassConfig::addPreEmitPass2() {
523   const Triple &TT = TM->getTargetTriple();
524   const MCAsmInfo *MAI = TM->getMCAsmInfo();
525 
526   addPass(createX86RetpolineThunksPass());
527 
528   // Insert extra int3 instructions after trailing call instructions to avoid
529   // issues in the unwinder.
530   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
531     addPass(createX86AvoidTrailingCallPass());
532 
533   // Verify basic block incoming and outgoing cfa offset and register values and
534   // correct CFA calculation rule where needed by inserting appropriate CFI
535   // instructions.
536   if (!TT.isOSDarwin() &&
537       (!TT.isOSWindows() ||
538        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
539     addPass(createCFIInstrInserter());
540   // Identify valid longjmp targets for Windows Control Flow Guard.
541   if (TT.isOSWindows())
542     addPass(createCFGuardLongjmpPass());
543 }
544 
545 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
546   return getStandardCSEConfigForOpt(TM->getOptLevel());
547 }
548