1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86TargetObjectFile.h"
18 #include "X86TargetTransformInfo.h"
19 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
20 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LegacyPassManager.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/FormattedStream.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Target/TargetOptions.h"
29 using namespace llvm;
30 
31 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
32                                cl::desc("Enable the machine combiner pass"),
33                                cl::init(true), cl::Hidden);
34 
35 namespace llvm {
36 void initializeWinEHStatePassPass(PassRegistry &);
37 }
38 
39 extern "C" void LLVMInitializeX86Target() {
40   // Register the target.
41   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
42   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
43 
44   PassRegistry &PR = *PassRegistry::getPassRegistry();
45   initializeGlobalISel(PR);
46   initializeWinEHStatePassPass(PR);
47   initializeFixupBWInstPassPass(PR);
48 }
49 
50 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
51   if (TT.isOSBinFormatMachO()) {
52     if (TT.getArch() == Triple::x86_64)
53       return make_unique<X86_64MachoTargetObjectFile>();
54     return make_unique<TargetLoweringObjectFileMachO>();
55   }
56 
57   if (TT.isOSFreeBSD())
58     return make_unique<X86FreeBSDTargetObjectFile>();
59   if (TT.isOSLinux() || TT.isOSNaCl())
60     return make_unique<X86LinuxNaClTargetObjectFile>();
61   if (TT.isOSFuchsia())
62     return make_unique<X86FuchsiaTargetObjectFile>();
63   if (TT.isOSBinFormatELF())
64     return make_unique<X86ELFTargetObjectFile>();
65   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
66     return make_unique<X86WindowsTargetObjectFile>();
67   if (TT.isOSBinFormatCOFF())
68     return make_unique<TargetLoweringObjectFileCOFF>();
69   llvm_unreachable("unknown subtarget type");
70 }
71 
72 static std::string computeDataLayout(const Triple &TT) {
73   // X86 is little endian
74   std::string Ret = "e";
75 
76   Ret += DataLayout::getManglingComponent(TT);
77   // X86 and x32 have 32 bit pointers.
78   if ((TT.isArch64Bit() &&
79        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
80       !TT.isArch64Bit())
81     Ret += "-p:32:32";
82 
83   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
84   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
85     Ret += "-i64:64";
86   else if (TT.isOSIAMCU())
87     Ret += "-i64:32-f64:32";
88   else
89     Ret += "-f64:32:64";
90 
91   // Some ABIs align long double to 128 bits, others to 32.
92   if (TT.isOSNaCl() || TT.isOSIAMCU())
93     ; // No f80
94   else if (TT.isArch64Bit() || TT.isOSDarwin())
95     Ret += "-f80:128";
96   else
97     Ret += "-f80:32";
98 
99   if (TT.isOSIAMCU())
100     Ret += "-f128:32";
101 
102   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
103   if (TT.isArch64Bit())
104     Ret += "-n8:16:32:64";
105   else
106     Ret += "-n8:16:32";
107 
108   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
109   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
110     Ret += "-a:0:32-S32";
111   else
112     Ret += "-S128";
113 
114   return Ret;
115 }
116 
117 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
118                                            Optional<Reloc::Model> RM) {
119   bool is64Bit = TT.getArch() == Triple::x86_64;
120   if (!RM.hasValue()) {
121     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
122     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
123     // use static relocation model by default.
124     if (TT.isOSDarwin()) {
125       if (is64Bit)
126         return Reloc::PIC_;
127       return Reloc::DynamicNoPIC;
128     }
129     if (TT.isOSWindows() && is64Bit)
130       return Reloc::PIC_;
131     return Reloc::Static;
132   }
133 
134   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
135   // is defined as a model for code which may be used in static or dynamic
136   // executables but not necessarily a shared library. On X86-32 we just
137   // compile in -static mode, in x86-64 we use PIC.
138   if (*RM == Reloc::DynamicNoPIC) {
139     if (is64Bit)
140       return Reloc::PIC_;
141     if (!TT.isOSDarwin())
142       return Reloc::Static;
143   }
144 
145   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
146   // the Mach-O file format doesn't support it.
147   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
148     return Reloc::PIC_;
149 
150   return *RM;
151 }
152 
153 /// Create an X86 target.
154 ///
155 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
156                                    StringRef CPU, StringRef FS,
157                                    const TargetOptions &Options,
158                                    Optional<Reloc::Model> RM,
159                                    CodeModel::Model CM, CodeGenOpt::Level OL)
160     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
161                         getEffectiveRelocModel(TT, RM), CM, OL),
162       TLOF(createTLOF(getTargetTriple())) {
163   // Windows stack unwinder gets confused when execution flow "falls through"
164   // after a call to 'noreturn' function.
165   // To prevent that, we emit a trap for 'unreachable' IR instructions.
166   // (which on X86, happens to be the 'ud2' instruction)
167   // On PS4, the "return address" of a 'noreturn' call must still be within
168   // the calling function, and TrapUnreachable is an easy way to get that.
169   // The check here for 64-bit windows is a bit icky, but as we're unlikely
170   // to ever want to mix 32 and 64-bit windows code in a single module
171   // this should be fine.
172   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
173     this->Options.TrapUnreachable = true;
174 
175   initAsmInfo();
176 }
177 
178 X86TargetMachine::~X86TargetMachine() {}
179 
180 #ifdef LLVM_BUILD_GLOBAL_ISEL
181 namespace {
182 struct X86GISelActualAccessor : public GISelAccessor {
183   std::unique_ptr<CallLowering> CL;
184   X86GISelActualAccessor(CallLowering* CL): CL(CL) {}
185   const CallLowering *getCallLowering() const override {
186     return CL.get();
187   }
188   const InstructionSelector *getInstructionSelector() const override {
189     //TODO: Implement
190     return nullptr;
191   }
192   const class LegalizerInfo *getLegalizerInfo() const override {
193     //TODO: Implement
194     return nullptr;
195   }
196   const RegisterBankInfo *getRegBankInfo() const override {
197     //TODO: Implement
198     return nullptr;
199   }
200 };
201 } // End anonymous namespace.
202 #endif
203 const X86Subtarget *
204 X86TargetMachine::getSubtargetImpl(const Function &F) const {
205   Attribute CPUAttr = F.getFnAttribute("target-cpu");
206   Attribute FSAttr = F.getFnAttribute("target-features");
207 
208   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
209                       ? CPUAttr.getValueAsString()
210                       : (StringRef)TargetCPU;
211   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
212                      ? FSAttr.getValueAsString()
213                      : (StringRef)TargetFS;
214 
215   SmallString<512> Key;
216   Key.reserve(CPU.size() + FS.size());
217   Key += CPU;
218   Key += FS;
219 
220   // FIXME: This is related to the code below to reset the target options,
221   // we need to know whether or not the soft float flag is set on the
222   // function before we can generate a subtarget. We also need to use
223   // it as a key for the subtarget since that can be the only difference
224   // between two functions.
225   bool SoftFloat =
226       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
227   // If the soft float attribute is set on the function turn on the soft float
228   // subtarget feature.
229   if (SoftFloat)
230     Key += FS.empty() ? "+soft-float" : ",+soft-float";
231 
232   FS = Key.substr(CPU.size());
233 
234   auto &I = SubtargetMap[Key];
235   if (!I) {
236     // This needs to be done before we create a new subtarget since any
237     // creation will depend on the TM and the code generation flags on the
238     // function that reside in TargetOptions.
239     resetTargetOptions(F);
240     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
241                                         Options.StackAlignmentOverride);
242 #ifndef LLVM_BUILD_GLOBAL_ISEL
243     GISelAccessor *GISel = new GISelAccessor();
244 #else
245     X86GISelActualAccessor *GISel = new X86GISelActualAccessor(
246         new X86CallLowering(*I->getTargetLowering()));
247 #endif
248     I->setGISelAccessor(*GISel);
249   }
250   return I.get();
251 }
252 
253 //===----------------------------------------------------------------------===//
254 // Command line options for x86
255 //===----------------------------------------------------------------------===//
256 static cl::opt<bool>
257 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
258   cl::desc("Minimize AVX to SSE transition penalty"),
259   cl::init(true));
260 
261 //===----------------------------------------------------------------------===//
262 // X86 TTI query.
263 //===----------------------------------------------------------------------===//
264 
265 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
266   return TargetIRAnalysis([this](const Function &F) {
267     return TargetTransformInfo(X86TTIImpl(this, F));
268   });
269 }
270 
271 
272 //===----------------------------------------------------------------------===//
273 // Pass Pipeline Configuration
274 //===----------------------------------------------------------------------===//
275 
276 namespace {
277 /// X86 Code Generator Pass Configuration Options.
278 class X86PassConfig : public TargetPassConfig {
279 public:
280   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
281     : TargetPassConfig(TM, PM) {}
282 
283   X86TargetMachine &getX86TargetMachine() const {
284     return getTM<X86TargetMachine>();
285   }
286 
287   void addIRPasses() override;
288   bool addInstSelector() override;
289 #ifdef LLVM_BUILD_GLOBAL_ISEL
290   bool addIRTranslator() override;
291   bool addLegalizeMachineIR() override;
292   bool addRegBankSelect() override;
293   bool addGlobalInstructionSelect() override;
294 #endif
295 bool addILPOpts() override;
296   bool addPreISel() override;
297   void addPreRegAlloc() override;
298   void addPostRegAlloc() override;
299   void addPreEmitPass() override;
300   void addPreSched2() override;
301 };
302 } // namespace
303 
304 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
305   return new X86PassConfig(this, PM);
306 }
307 
308 void X86PassConfig::addIRPasses() {
309   addPass(createAtomicExpandPass(&getX86TargetMachine()));
310 
311   TargetPassConfig::addIRPasses();
312 
313   if (TM->getOptLevel() != CodeGenOpt::None)
314     addPass(createInterleavedAccessPass(TM));
315 }
316 
317 bool X86PassConfig::addInstSelector() {
318   // Install an instruction selector.
319   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
320 
321   // For ELF, cleanup any local-dynamic TLS accesses.
322   if (TM->getTargetTriple().isOSBinFormatELF() &&
323       getOptLevel() != CodeGenOpt::None)
324     addPass(createCleanupLocalDynamicTLSPass());
325 
326   addPass(createX86GlobalBaseRegPass());
327   return false;
328 }
329 
330 #ifdef LLVM_BUILD_GLOBAL_ISEL
331 bool X86PassConfig::addIRTranslator() {
332   addPass(new IRTranslator());
333   return false;
334 }
335 
336 bool X86PassConfig::addLegalizeMachineIR() {
337   //TODO: Implement
338   return false;
339 }
340 
341 bool X86PassConfig::addRegBankSelect() {
342   //TODO: Implement
343   return false;
344 }
345 
346 bool X86PassConfig::addGlobalInstructionSelect() {
347   //TODO: Implement
348   return false;
349 }
350 #endif
351 
352 bool X86PassConfig::addILPOpts() {
353   addPass(&EarlyIfConverterID);
354   if (EnableMachineCombinerPass)
355     addPass(&MachineCombinerID);
356   return true;
357 }
358 
359 bool X86PassConfig::addPreISel() {
360   // Only add this pass for 32-bit x86 Windows.
361   const Triple &TT = TM->getTargetTriple();
362   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
363     addPass(createX86WinEHStatePass());
364   return true;
365 }
366 
367 void X86PassConfig::addPreRegAlloc() {
368   if (getOptLevel() != CodeGenOpt::None) {
369     addPass(createX86FixupSetCC());
370     addPass(createX86OptimizeLEAs());
371     addPass(createX86CallFrameOptimization());
372   }
373 
374   addPass(createX86WinAllocaExpander());
375 }
376 
377 void X86PassConfig::addPostRegAlloc() {
378   addPass(createX86FloatingPointStackifierPass());
379 }
380 
381 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
382 
383 void X86PassConfig::addPreEmitPass() {
384   if (getOptLevel() != CodeGenOpt::None)
385     addPass(createExecutionDependencyFixPass(&X86::VR128XRegClass));
386 
387   if (UseVZeroUpper)
388     addPass(createX86IssueVZeroUpperPass());
389 
390   if (getOptLevel() != CodeGenOpt::None) {
391     addPass(createX86FixupBWInsts());
392     addPass(createX86PadShortFunctions());
393     addPass(createX86FixupLEAs());
394   }
395 }
396