1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Support/TargetRegistry.h"
23 using namespace llvm;
24 
25 extern "C" void LLVMInitializeX86Target() {
26   // Register the target.
27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
29 }
30 
31 void X86_32TargetMachine::anchor() { }
32 
33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34                                          StringRef CPU, StringRef FS,
35                                          const TargetOptions &Options,
36                                          Reloc::Model RM, CodeModel::Model CM,
37                                          CodeGenOpt::Level OL)
38   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39     DL(getSubtargetImpl()->isTargetDarwin() ?
40                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
41                "n8:16:32-S128" :
42                (getSubtargetImpl()->isTargetCygMing() ||
43                 getSubtargetImpl()->isTargetWindows()) ?
44                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
45                "n8:16:32-S32" :
46                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
47                "n8:16:32-S128"),
48     InstrInfo(*this),
49     TSInfo(*this),
50     TLInfo(*this),
51     JITInfo(*this),
52     STTI(&TLInfo), VTTI(&TLInfo) {
53 }
54 
55 void X86_64TargetMachine::anchor() { }
56 
57 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
58                                          StringRef CPU, StringRef FS,
59                                          const TargetOptions &Options,
60                                          Reloc::Model RM, CodeModel::Model CM,
61                                          CodeGenOpt::Level OL)
62   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
63     DL("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
64                "n8:16:32:64-S128"),
65     InstrInfo(*this),
66     TSInfo(*this),
67     TLInfo(*this),
68     JITInfo(*this),
69     STTI(&TLInfo), VTTI(&TLInfo){
70 }
71 
72 /// X86TargetMachine ctor - Create an X86 target.
73 ///
74 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
75                                    StringRef CPU, StringRef FS,
76                                    const TargetOptions &Options,
77                                    Reloc::Model RM, CodeModel::Model CM,
78                                    CodeGenOpt::Level OL,
79                                    bool is64Bit)
80   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
81     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
82     FrameLowering(*this, Subtarget),
83     InstrItins(Subtarget.getInstrItineraryData()){
84   // Determine the PICStyle based on the target selected.
85   if (getRelocationModel() == Reloc::Static) {
86     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
87     Subtarget.setPICStyle(PICStyles::None);
88   } else if (Subtarget.is64Bit()) {
89     // PIC in 64 bit mode is always rip-rel.
90     Subtarget.setPICStyle(PICStyles::RIPRel);
91   } else if (Subtarget.isTargetCygMing()) {
92     Subtarget.setPICStyle(PICStyles::None);
93   } else if (Subtarget.isTargetDarwin()) {
94     if (getRelocationModel() == Reloc::PIC_)
95       Subtarget.setPICStyle(PICStyles::StubPIC);
96     else {
97       assert(getRelocationModel() == Reloc::DynamicNoPIC);
98       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
99     }
100   } else if (Subtarget.isTargetELF()) {
101     Subtarget.setPICStyle(PICStyles::GOT);
102   }
103 
104   // default to hard float ABI
105   if (Options.FloatABIType == FloatABI::Default)
106     this->Options.FloatABIType = FloatABI::Hard;
107 }
108 
109 //===----------------------------------------------------------------------===//
110 // Command line options for x86
111 //===----------------------------------------------------------------------===//
112 static cl::opt<bool>
113 UseVZeroUpper("x86-use-vzeroupper",
114   cl::desc("Minimize AVX to SSE transition penalty"),
115   cl::init(true));
116 
117 // Temporary option to control early if-conversion for x86 while adding machine
118 // models.
119 static cl::opt<bool>
120 X86EarlyIfConv("x86-early-ifcvt",
121 	       cl::desc("Enable early if-conversion on X86"));
122 
123 //===----------------------------------------------------------------------===//
124 // Pass Pipeline Configuration
125 //===----------------------------------------------------------------------===//
126 
127 namespace {
128 /// X86 Code Generator Pass Configuration Options.
129 class X86PassConfig : public TargetPassConfig {
130 public:
131   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
132     : TargetPassConfig(TM, PM) {}
133 
134   X86TargetMachine &getX86TargetMachine() const {
135     return getTM<X86TargetMachine>();
136   }
137 
138   const X86Subtarget &getX86Subtarget() const {
139     return *getX86TargetMachine().getSubtargetImpl();
140   }
141 
142   virtual bool addInstSelector();
143   virtual bool addPreRegAlloc();
144   virtual bool addPostRegAlloc();
145   virtual bool addPreEmitPass();
146 };
147 } // namespace
148 
149 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
150   X86PassConfig *PC = new X86PassConfig(this, PM);
151 
152   if (X86EarlyIfConv && Subtarget.hasCMov())
153     PC->enablePass(&EarlyIfConverterID);
154 
155   return PC;
156 }
157 
158 bool X86PassConfig::addInstSelector() {
159   // Install an instruction selector.
160   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
161 
162   // For ELF, cleanup any local-dynamic TLS accesses.
163   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
164     addPass(createCleanupLocalDynamicTLSPass());
165 
166   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
167   if (!getX86Subtarget().is64Bit())
168     addPass(createGlobalBaseRegPass());
169 
170   return false;
171 }
172 
173 bool X86PassConfig::addPreRegAlloc() {
174   return false;  // -print-machineinstr shouldn't print after this.
175 }
176 
177 bool X86PassConfig::addPostRegAlloc() {
178   addPass(createX86FloatingPointStackifierPass());
179   return true;  // -print-machineinstr should print after this.
180 }
181 
182 bool X86PassConfig::addPreEmitPass() {
183   bool ShouldPrint = false;
184   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
185     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
186     ShouldPrint = true;
187   }
188 
189   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
190     addPass(createX86IssueVZeroUpperPass());
191     ShouldPrint = true;
192   }
193 
194   return ShouldPrint;
195 }
196 
197 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
198                                       JITCodeEmitter &JCE) {
199   PM.add(createX86JITCodeEmitterPass(*this, JCE));
200 
201   return false;
202 }
203