1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #ifdef LLVM_BUILD_GLOBAL_ISEL
19 #include "X86RegisterBankInfo.h"
20 #endif
21 #include "X86MacroFusion.h"
22 #include "X86Subtarget.h"
23 #include "X86TargetMachine.h"
24 #include "X86TargetObjectFile.h"
25 #include "X86TargetTransformInfo.h"
26 #include "llvm/ADT/Optional.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/Analysis/TargetTransformInfo.h"
32 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
33 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
34 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
35 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MachineScheduler.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/Pass.h"
44 #include "llvm/Support/CodeGen.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 namespace llvm {
60 
61 void initializeWinEHStatePassPass(PassRegistry &);
62 
63 } // end namespace llvm
64 
65 extern "C" void LLVMInitializeX86Target() {
66   // Register the target.
67   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
68   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
69 
70   PassRegistry &PR = *PassRegistry::getPassRegistry();
71   initializeGlobalISel(PR);
72   initializeWinEHStatePassPass(PR);
73   initializeFixupBWInstPassPass(PR);
74   initializeEvexToVexInstPassPass(PR);
75 }
76 
77 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
78   if (TT.isOSBinFormatMachO()) {
79     if (TT.getArch() == Triple::x86_64)
80       return llvm::make_unique<X86_64MachoTargetObjectFile>();
81     return llvm::make_unique<TargetLoweringObjectFileMachO>();
82   }
83 
84   if (TT.isOSFreeBSD())
85     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
86   if (TT.isOSLinux() || TT.isOSNaCl())
87     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
88   if (TT.isOSFuchsia())
89     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
90   if (TT.isOSBinFormatELF())
91     return llvm::make_unique<X86ELFTargetObjectFile>();
92   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
93     return llvm::make_unique<X86WindowsTargetObjectFile>();
94   if (TT.isOSBinFormatCOFF())
95     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
96   llvm_unreachable("unknown subtarget type");
97 }
98 
99 static std::string computeDataLayout(const Triple &TT) {
100   // X86 is little endian
101   std::string Ret = "e";
102 
103   Ret += DataLayout::getManglingComponent(TT);
104   // X86 and x32 have 32 bit pointers.
105   if ((TT.isArch64Bit() &&
106        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
107       !TT.isArch64Bit())
108     Ret += "-p:32:32";
109 
110   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
111   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
112     Ret += "-i64:64";
113   else if (TT.isOSIAMCU())
114     Ret += "-i64:32-f64:32";
115   else
116     Ret += "-f64:32:64";
117 
118   // Some ABIs align long double to 128 bits, others to 32.
119   if (TT.isOSNaCl() || TT.isOSIAMCU())
120     ; // No f80
121   else if (TT.isArch64Bit() || TT.isOSDarwin())
122     Ret += "-f80:128";
123   else
124     Ret += "-f80:32";
125 
126   if (TT.isOSIAMCU())
127     Ret += "-f128:32";
128 
129   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
130   if (TT.isArch64Bit())
131     Ret += "-n8:16:32:64";
132   else
133     Ret += "-n8:16:32";
134 
135   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
136   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
137     Ret += "-a:0:32-S32";
138   else
139     Ret += "-S128";
140 
141   return Ret;
142 }
143 
144 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
145                                            Optional<Reloc::Model> RM) {
146   bool is64Bit = TT.getArch() == Triple::x86_64;
147   if (!RM.hasValue()) {
148     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
149     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
150     // use static relocation model by default.
151     if (TT.isOSDarwin()) {
152       if (is64Bit)
153         return Reloc::PIC_;
154       return Reloc::DynamicNoPIC;
155     }
156     if (TT.isOSWindows() && is64Bit)
157       return Reloc::PIC_;
158     return Reloc::Static;
159   }
160 
161   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
162   // is defined as a model for code which may be used in static or dynamic
163   // executables but not necessarily a shared library. On X86-32 we just
164   // compile in -static mode, in x86-64 we use PIC.
165   if (*RM == Reloc::DynamicNoPIC) {
166     if (is64Bit)
167       return Reloc::PIC_;
168     if (!TT.isOSDarwin())
169       return Reloc::Static;
170   }
171 
172   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
173   // the Mach-O file format doesn't support it.
174   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
175     return Reloc::PIC_;
176 
177   return *RM;
178 }
179 
180 /// Create an X86 target.
181 ///
182 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
183                                    StringRef CPU, StringRef FS,
184                                    const TargetOptions &Options,
185                                    Optional<Reloc::Model> RM,
186                                    CodeModel::Model CM, CodeGenOpt::Level OL)
187     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
188                         getEffectiveRelocModel(TT, RM), CM, OL),
189       TLOF(createTLOF(getTargetTriple())) {
190   // Windows stack unwinder gets confused when execution flow "falls through"
191   // after a call to 'noreturn' function.
192   // To prevent that, we emit a trap for 'unreachable' IR instructions.
193   // (which on X86, happens to be the 'ud2' instruction)
194   // On PS4, the "return address" of a 'noreturn' call must still be within
195   // the calling function, and TrapUnreachable is an easy way to get that.
196   // The check here for 64-bit windows is a bit icky, but as we're unlikely
197   // to ever want to mix 32 and 64-bit windows code in a single module
198   // this should be fine.
199   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
200     this->Options.TrapUnreachable = true;
201 
202   initAsmInfo();
203 }
204 
205 X86TargetMachine::~X86TargetMachine() = default;
206 
207 #ifdef LLVM_BUILD_GLOBAL_ISEL
208 namespace {
209 
210 struct X86GISelActualAccessor : public GISelAccessor {
211   std::unique_ptr<CallLowering> CallLoweringInfo;
212   std::unique_ptr<LegalizerInfo> Legalizer;
213   std::unique_ptr<RegisterBankInfo> RegBankInfo;
214 
215   const CallLowering *getCallLowering() const override {
216     return CallLoweringInfo.get();
217   }
218 
219   const InstructionSelector *getInstructionSelector() const override {
220     //TODO: Implement
221     return nullptr;
222   }
223 
224   const LegalizerInfo *getLegalizerInfo() const override {
225     return Legalizer.get();
226   }
227 
228   const RegisterBankInfo *getRegBankInfo() const override {
229     return RegBankInfo.get();
230   }
231 };
232 
233 } // end anonymous namespace
234 #endif
235 
236 const X86Subtarget *
237 X86TargetMachine::getSubtargetImpl(const Function &F) const {
238   Attribute CPUAttr = F.getFnAttribute("target-cpu");
239   Attribute FSAttr = F.getFnAttribute("target-features");
240 
241   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
242                       ? CPUAttr.getValueAsString()
243                       : (StringRef)TargetCPU;
244   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
245                      ? FSAttr.getValueAsString()
246                      : (StringRef)TargetFS;
247 
248   SmallString<512> Key;
249   Key.reserve(CPU.size() + FS.size());
250   Key += CPU;
251   Key += FS;
252 
253   // FIXME: This is related to the code below to reset the target options,
254   // we need to know whether or not the soft float flag is set on the
255   // function before we can generate a subtarget. We also need to use
256   // it as a key for the subtarget since that can be the only difference
257   // between two functions.
258   bool SoftFloat =
259       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
260   // If the soft float attribute is set on the function turn on the soft float
261   // subtarget feature.
262   if (SoftFloat)
263     Key += FS.empty() ? "+soft-float" : ",+soft-float";
264 
265   FS = Key.substr(CPU.size());
266 
267   auto &I = SubtargetMap[Key];
268   if (!I) {
269     // This needs to be done before we create a new subtarget since any
270     // creation will depend on the TM and the code generation flags on the
271     // function that reside in TargetOptions.
272     resetTargetOptions(F);
273     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
274                                         Options.StackAlignmentOverride);
275 #ifndef LLVM_BUILD_GLOBAL_ISEL
276     GISelAccessor *GISel = new GISelAccessor();
277 #else
278     X86GISelActualAccessor *GISel = new X86GISelActualAccessor();
279 
280     GISel->CallLoweringInfo.reset(new X86CallLowering(*I->getTargetLowering()));
281     GISel->Legalizer.reset(new X86LegalizerInfo(*I));
282 
283     auto *RBI = new X86RegisterBankInfo(*I->getRegisterInfo());
284     GISel->RegBankInfo.reset(RBI);
285 
286 #endif
287     I->setGISelAccessor(*GISel);
288   }
289   return I.get();
290 }
291 
292 //===----------------------------------------------------------------------===//
293 // Command line options for x86
294 //===----------------------------------------------------------------------===//
295 static cl::opt<bool>
296 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
297   cl::desc("Minimize AVX to SSE transition penalty"),
298   cl::init(true));
299 
300 //===----------------------------------------------------------------------===//
301 // X86 TTI query.
302 //===----------------------------------------------------------------------===//
303 
304 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
305   return TargetIRAnalysis([this](const Function &F) {
306     return TargetTransformInfo(X86TTIImpl(this, F));
307   });
308 }
309 
310 //===----------------------------------------------------------------------===//
311 // Pass Pipeline Configuration
312 //===----------------------------------------------------------------------===//
313 
314 namespace {
315 
316 /// X86 Code Generator Pass Configuration Options.
317 class X86PassConfig : public TargetPassConfig {
318 public:
319   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
320     : TargetPassConfig(TM, PM) {}
321 
322   X86TargetMachine &getX86TargetMachine() const {
323     return getTM<X86TargetMachine>();
324   }
325 
326   ScheduleDAGInstrs *
327   createMachineScheduler(MachineSchedContext *C) const override {
328     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
329     DAG->addMutation(createX86MacroFusionDAGMutation());
330     return DAG;
331   }
332 
333   void addIRPasses() override;
334   bool addInstSelector() override;
335 #ifdef LLVM_BUILD_GLOBAL_ISEL
336   bool addIRTranslator() override;
337   bool addLegalizeMachineIR() override;
338   bool addRegBankSelect() override;
339   bool addGlobalInstructionSelect() override;
340 #endif
341   bool addILPOpts() override;
342   bool addPreISel() override;
343   void addPreRegAlloc() override;
344   void addPostRegAlloc() override;
345   void addPreEmitPass() override;
346   void addPreSched2() override;
347 };
348 
349 } // end anonymous namespace
350 
351 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
352   return new X86PassConfig(this, PM);
353 }
354 
355 void X86PassConfig::addIRPasses() {
356   addPass(createAtomicExpandPass(&getX86TargetMachine()));
357 
358   TargetPassConfig::addIRPasses();
359 
360   if (TM->getOptLevel() != CodeGenOpt::None)
361     addPass(createInterleavedAccessPass(TM));
362 }
363 
364 bool X86PassConfig::addInstSelector() {
365   // Install an instruction selector.
366   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
367 
368   // For ELF, cleanup any local-dynamic TLS accesses.
369   if (TM->getTargetTriple().isOSBinFormatELF() &&
370       getOptLevel() != CodeGenOpt::None)
371     addPass(createCleanupLocalDynamicTLSPass());
372 
373   addPass(createX86GlobalBaseRegPass());
374   return false;
375 }
376 
377 #ifdef LLVM_BUILD_GLOBAL_ISEL
378 bool X86PassConfig::addIRTranslator() {
379   addPass(new IRTranslator());
380   return false;
381 }
382 
383 bool X86PassConfig::addLegalizeMachineIR() {
384   addPass(new Legalizer());
385   return false;
386 }
387 
388 bool X86PassConfig::addRegBankSelect() {
389   addPass(new RegBankSelect());
390   return false;
391 }
392 
393 bool X86PassConfig::addGlobalInstructionSelect() {
394   //TODO: Implement
395   return false;
396 }
397 #endif
398 
399 bool X86PassConfig::addILPOpts() {
400   addPass(&EarlyIfConverterID);
401   if (EnableMachineCombinerPass)
402     addPass(&MachineCombinerID);
403   return true;
404 }
405 
406 bool X86PassConfig::addPreISel() {
407   // Only add this pass for 32-bit x86 Windows.
408   const Triple &TT = TM->getTargetTriple();
409   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
410     addPass(createX86WinEHStatePass());
411   return true;
412 }
413 
414 void X86PassConfig::addPreRegAlloc() {
415   if (getOptLevel() != CodeGenOpt::None) {
416     addPass(createX86FixupSetCC());
417     addPass(createX86OptimizeLEAs());
418     addPass(createX86CallFrameOptimization());
419   }
420 
421   addPass(createX86WinAllocaExpander());
422 }
423 
424 void X86PassConfig::addPostRegAlloc() {
425   addPass(createX86FloatingPointStackifierPass());
426 }
427 
428 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
429 
430 void X86PassConfig::addPreEmitPass() {
431   if (getOptLevel() != CodeGenOpt::None)
432     addPass(createExecutionDependencyFixPass(&X86::VR128XRegClass));
433 
434   if (UseVZeroUpper)
435     addPass(createX86IssueVZeroUpperPass());
436 
437   if (getOptLevel() != CodeGenOpt::None) {
438     addPass(createX86FixupBWInsts());
439     addPass(createX86PadShortFunctions());
440     addPass(createX86FixupLEAs());
441     addPass(createX86EvexToVexInsts());
442   }
443 }
444