1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54                                cl::desc("Enable the machine combiner pass"),
55                                cl::init(true), cl::Hidden);
56 
57 namespace llvm {
58 
59 void initializeWinEHStatePassPass(PassRegistry &);
60 void initializeFixupLEAPassPass(PassRegistry &);
61 void initializeShadowCallStackPass(PassRegistry &);
62 void initializeX86CallFrameOptimizationPass(PassRegistry &);
63 void initializeX86CmovConverterPassPass(PassRegistry &);
64 void initializeX86ExecutionDomainFixPass(PassRegistry &);
65 void initializeX86DomainReassignmentPass(PassRegistry &);
66 void initializeX86AvoidSFBPassPass(PassRegistry &);
67 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
68 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
69 
70 } // end namespace llvm
71 
72 extern "C" void LLVMInitializeX86Target() {
73   // Register the target.
74   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
75   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
76 
77   PassRegistry &PR = *PassRegistry::getPassRegistry();
78   initializeGlobalISel(PR);
79   initializeWinEHStatePassPass(PR);
80   initializeFixupBWInstPassPass(PR);
81   initializeEvexToVexInstPassPass(PR);
82   initializeFixupLEAPassPass(PR);
83   initializeShadowCallStackPass(PR);
84   initializeX86CallFrameOptimizationPass(PR);
85   initializeX86CmovConverterPassPass(PR);
86   initializeX86ExecutionDomainFixPass(PR);
87   initializeX86DomainReassignmentPass(PR);
88   initializeX86AvoidSFBPassPass(PR);
89   initializeX86SpeculativeLoadHardeningPassPass(PR);
90   initializeX86FlagsCopyLoweringPassPass(PR);
91 }
92 
93 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
94   if (TT.isOSBinFormatMachO()) {
95     if (TT.getArch() == Triple::x86_64)
96       return llvm::make_unique<X86_64MachoTargetObjectFile>();
97     return llvm::make_unique<TargetLoweringObjectFileMachO>();
98   }
99 
100   if (TT.isOSFreeBSD())
101     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
102   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
103     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
104   if (TT.isOSSolaris())
105     return llvm::make_unique<X86SolarisTargetObjectFile>();
106   if (TT.isOSFuchsia())
107     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
108   if (TT.isOSBinFormatELF())
109     return llvm::make_unique<X86ELFTargetObjectFile>();
110   if (TT.isOSBinFormatCOFF())
111     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
112   llvm_unreachable("unknown subtarget type");
113 }
114 
115 static std::string computeDataLayout(const Triple &TT) {
116   // X86 is little endian
117   std::string Ret = "e";
118 
119   Ret += DataLayout::getManglingComponent(TT);
120   // X86 and x32 have 32 bit pointers.
121   if ((TT.isArch64Bit() &&
122        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
123       !TT.isArch64Bit())
124     Ret += "-p:32:32";
125 
126   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
127   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
128     Ret += "-i64:64";
129   else if (TT.isOSIAMCU())
130     Ret += "-i64:32-f64:32";
131   else
132     Ret += "-f64:32:64";
133 
134   // Some ABIs align long double to 128 bits, others to 32.
135   if (TT.isOSNaCl() || TT.isOSIAMCU())
136     ; // No f80
137   else if (TT.isArch64Bit() || TT.isOSDarwin())
138     Ret += "-f80:128";
139   else
140     Ret += "-f80:32";
141 
142   if (TT.isOSIAMCU())
143     Ret += "-f128:32";
144 
145   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
146   if (TT.isArch64Bit())
147     Ret += "-n8:16:32:64";
148   else
149     Ret += "-n8:16:32";
150 
151   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
152   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
153     Ret += "-a:0:32-S32";
154   else
155     Ret += "-S128";
156 
157   return Ret;
158 }
159 
160 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
161                                            bool JIT,
162                                            Optional<Reloc::Model> RM) {
163   bool is64Bit = TT.getArch() == Triple::x86_64;
164   if (!RM.hasValue()) {
165     // JIT codegen should use static relocations by default, since it's
166     // typically executed in process and not relocatable.
167     if (JIT)
168       return Reloc::Static;
169 
170     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
171     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
172     // use static relocation model by default.
173     if (TT.isOSDarwin()) {
174       if (is64Bit)
175         return Reloc::PIC_;
176       return Reloc::DynamicNoPIC;
177     }
178     if (TT.isOSWindows() && is64Bit)
179       return Reloc::PIC_;
180     return Reloc::Static;
181   }
182 
183   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
184   // is defined as a model for code which may be used in static or dynamic
185   // executables but not necessarily a shared library. On X86-32 we just
186   // compile in -static mode, in x86-64 we use PIC.
187   if (*RM == Reloc::DynamicNoPIC) {
188     if (is64Bit)
189       return Reloc::PIC_;
190     if (!TT.isOSDarwin())
191       return Reloc::Static;
192   }
193 
194   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
195   // the Mach-O file format doesn't support it.
196   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
197     return Reloc::PIC_;
198 
199   return *RM;
200 }
201 
202 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
203                                               bool JIT, bool Is64Bit) {
204   if (CM)
205     return *CM;
206   if (JIT)
207     return Is64Bit ? CodeModel::Large : CodeModel::Small;
208   return CodeModel::Small;
209 }
210 
211 /// Create an X86 target.
212 ///
213 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
214                                    StringRef CPU, StringRef FS,
215                                    const TargetOptions &Options,
216                                    Optional<Reloc::Model> RM,
217                                    Optional<CodeModel::Model> CM,
218                                    CodeGenOpt::Level OL, bool JIT)
219     : LLVMTargetMachine(
220           T, computeDataLayout(TT), TT, CPU, FS, Options,
221           getEffectiveRelocModel(TT, JIT, RM),
222           getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
223       TLOF(createTLOF(getTargetTriple())) {
224   // Windows stack unwinder gets confused when execution flow "falls through"
225   // after a call to 'noreturn' function.
226   // To prevent that, we emit a trap for 'unreachable' IR instructions.
227   // (which on X86, happens to be the 'ud2' instruction)
228   // On PS4, the "return address" of a 'noreturn' call must still be within
229   // the calling function, and TrapUnreachable is an easy way to get that.
230   // The check here for 64-bit windows is a bit icky, but as we're unlikely
231   // to ever want to mix 32 and 64-bit windows code in a single module
232   // this should be fine.
233   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
234       TT.isOSBinFormatMachO()) {
235     this->Options.TrapUnreachable = true;
236     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
237   }
238 
239   // Outlining is available for x86-64.
240   if (TT.getArch() == Triple::x86_64)
241     setMachineOutliner(true);
242 
243   initAsmInfo();
244 }
245 
246 X86TargetMachine::~X86TargetMachine() = default;
247 
248 const X86Subtarget *
249 X86TargetMachine::getSubtargetImpl(const Function &F) const {
250   Attribute CPUAttr = F.getFnAttribute("target-cpu");
251   Attribute FSAttr = F.getFnAttribute("target-features");
252 
253   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
254                       ? CPUAttr.getValueAsString()
255                       : (StringRef)TargetCPU;
256   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
257                      ? FSAttr.getValueAsString()
258                      : (StringRef)TargetFS;
259 
260   SmallString<512> Key;
261   Key.reserve(CPU.size() + FS.size());
262   Key += CPU;
263   Key += FS;
264 
265   // FIXME: This is related to the code below to reset the target options,
266   // we need to know whether or not the soft float flag is set on the
267   // function before we can generate a subtarget. We also need to use
268   // it as a key for the subtarget since that can be the only difference
269   // between two functions.
270   bool SoftFloat =
271       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
272   // If the soft float attribute is set on the function turn on the soft float
273   // subtarget feature.
274   if (SoftFloat)
275     Key += FS.empty() ? "+soft-float" : ",+soft-float";
276 
277   // Keep track of the key width after all features are added so we can extract
278   // the feature string out later.
279   unsigned CPUFSWidth = Key.size();
280 
281   // Extract prefer-vector-width attribute.
282   unsigned PreferVectorWidthOverride = 0;
283   if (F.hasFnAttribute("prefer-vector-width")) {
284     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
285     unsigned Width;
286     if (!Val.getAsInteger(0, Width)) {
287       Key += ",prefer-vector-width=";
288       Key += Val;
289       PreferVectorWidthOverride = Width;
290     }
291   }
292 
293   // Extract required-vector-width attribute.
294   unsigned RequiredVectorWidth = UINT32_MAX;
295   if (F.hasFnAttribute("required-vector-width")) {
296     StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
297     unsigned Width;
298     if (!Val.getAsInteger(0, Width)) {
299       Key += ",required-vector-width=";
300       Key += Val;
301       RequiredVectorWidth = Width;
302     }
303   }
304 
305   // Extracted here so that we make sure there is backing for the StringRef. If
306   // we assigned earlier, its possible the SmallString reallocated leaving a
307   // dangling StringRef.
308   FS = Key.slice(CPU.size(), CPUFSWidth);
309 
310   auto &I = SubtargetMap[Key];
311   if (!I) {
312     // This needs to be done before we create a new subtarget since any
313     // creation will depend on the TM and the code generation flags on the
314     // function that reside in TargetOptions.
315     resetTargetOptions(F);
316     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
317                                         Options.StackAlignmentOverride,
318                                         PreferVectorWidthOverride,
319                                         RequiredVectorWidth);
320   }
321   return I.get();
322 }
323 
324 //===----------------------------------------------------------------------===//
325 // Command line options for x86
326 //===----------------------------------------------------------------------===//
327 static cl::opt<bool>
328 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
329   cl::desc("Minimize AVX to SSE transition penalty"),
330   cl::init(true));
331 
332 //===----------------------------------------------------------------------===//
333 // X86 TTI query.
334 //===----------------------------------------------------------------------===//
335 
336 TargetTransformInfo
337 X86TargetMachine::getTargetTransformInfo(const Function &F) {
338   return TargetTransformInfo(X86TTIImpl(this, F));
339 }
340 
341 //===----------------------------------------------------------------------===//
342 // Pass Pipeline Configuration
343 //===----------------------------------------------------------------------===//
344 
345 namespace {
346 
347 /// X86 Code Generator Pass Configuration Options.
348 class X86PassConfig : public TargetPassConfig {
349 public:
350   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
351     : TargetPassConfig(TM, PM) {}
352 
353   X86TargetMachine &getX86TargetMachine() const {
354     return getTM<X86TargetMachine>();
355   }
356 
357   ScheduleDAGInstrs *
358   createMachineScheduler(MachineSchedContext *C) const override {
359     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
360     DAG->addMutation(createX86MacroFusionDAGMutation());
361     return DAG;
362   }
363 
364   void addIRPasses() override;
365   bool addInstSelector() override;
366   bool addIRTranslator() override;
367   bool addLegalizeMachineIR() override;
368   bool addRegBankSelect() override;
369   bool addGlobalInstructionSelect() override;
370   bool addILPOpts() override;
371   bool addPreISel() override;
372   void addMachineSSAOptimization() override;
373   void addPreRegAlloc() override;
374   void addPostRegAlloc() override;
375   void addPreEmitPass() override;
376   void addPreEmitPass2() override;
377   void addPreSched2() override;
378 };
379 
380 class X86ExecutionDomainFix : public ExecutionDomainFix {
381 public:
382   static char ID;
383   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
384   StringRef getPassName() const override {
385     return "X86 Execution Dependency Fix";
386   }
387 };
388 char X86ExecutionDomainFix::ID;
389 
390 } // end anonymous namespace
391 
392 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
393   "X86 Execution Domain Fix", false, false)
394 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
395 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
396   "X86 Execution Domain Fix", false, false)
397 
398 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
399   return new X86PassConfig(*this, PM);
400 }
401 
402 void X86PassConfig::addIRPasses() {
403   addPass(createAtomicExpandPass());
404 
405   TargetPassConfig::addIRPasses();
406 
407   if (TM->getOptLevel() != CodeGenOpt::None)
408     addPass(createInterleavedAccessPass());
409 
410   // Add passes that handle indirect branch removal and insertion of a retpoline
411   // thunk. These will be a no-op unless a function subtarget has the retpoline
412   // feature enabled.
413   addPass(createIndirectBrExpandPass());
414 }
415 
416 bool X86PassConfig::addInstSelector() {
417   // Install an instruction selector.
418   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
419 
420   // For ELF, cleanup any local-dynamic TLS accesses.
421   if (TM->getTargetTriple().isOSBinFormatELF() &&
422       getOptLevel() != CodeGenOpt::None)
423     addPass(createCleanupLocalDynamicTLSPass());
424 
425   addPass(createX86GlobalBaseRegPass());
426   return false;
427 }
428 
429 bool X86PassConfig::addIRTranslator() {
430   addPass(new IRTranslator());
431   return false;
432 }
433 
434 bool X86PassConfig::addLegalizeMachineIR() {
435   addPass(new Legalizer());
436   return false;
437 }
438 
439 bool X86PassConfig::addRegBankSelect() {
440   addPass(new RegBankSelect());
441   return false;
442 }
443 
444 bool X86PassConfig::addGlobalInstructionSelect() {
445   addPass(new InstructionSelect());
446   return false;
447 }
448 
449 bool X86PassConfig::addILPOpts() {
450   addPass(&EarlyIfConverterID);
451   if (EnableMachineCombinerPass)
452     addPass(&MachineCombinerID);
453   addPass(createX86CmovConverterPass());
454   return true;
455 }
456 
457 bool X86PassConfig::addPreISel() {
458   // Only add this pass for 32-bit x86 Windows.
459   const Triple &TT = TM->getTargetTriple();
460   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
461     addPass(createX86WinEHStatePass());
462   return true;
463 }
464 
465 void X86PassConfig::addPreRegAlloc() {
466   if (getOptLevel() != CodeGenOpt::None) {
467     addPass(&LiveRangeShrinkID);
468     addPass(createX86FixupSetCC());
469     addPass(createX86OptimizeLEAs());
470     addPass(createX86CallFrameOptimization());
471     addPass(createX86AvoidStoreForwardingBlocks());
472   }
473 
474   addPass(createX86SpeculativeLoadHardeningPass());
475   addPass(createX86FlagsCopyLoweringPass());
476   addPass(createX86WinAllocaExpander());
477 }
478 void X86PassConfig::addMachineSSAOptimization() {
479   addPass(createX86DomainReassignmentPass());
480   TargetPassConfig::addMachineSSAOptimization();
481 }
482 
483 void X86PassConfig::addPostRegAlloc() {
484   addPass(createX86FloatingPointStackifierPass());
485 }
486 
487 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
488 
489 void X86PassConfig::addPreEmitPass() {
490   if (getOptLevel() != CodeGenOpt::None) {
491     addPass(new X86ExecutionDomainFix());
492     addPass(createBreakFalseDeps());
493   }
494 
495   addPass(createShadowCallStackPass());
496   addPass(createX86IndirectBranchTrackingPass());
497 
498   if (UseVZeroUpper)
499     addPass(createX86IssueVZeroUpperPass());
500 
501   if (getOptLevel() != CodeGenOpt::None) {
502     addPass(createX86FixupBWInsts());
503     addPass(createX86PadShortFunctions());
504     addPass(createX86FixupLEAs());
505     addPass(createX86EvexToVexInsts());
506   }
507 }
508 
509 void X86PassConfig::addPreEmitPass2() {
510   addPass(createX86RetpolineThunksPass());
511   // Verify basic block incoming and outgoing cfa offset and register values and
512   // correct CFA calculation rule where needed by inserting appropriate CFI
513   // instructions.
514   const Triple &TT = TM->getTargetTriple();
515   if (!TT.isOSDarwin() && !TT.isOSWindows())
516     addPass(createCFIInstrInserter());
517 }
518