1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
31 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
35 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MachineScheduler.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58                                cl::desc("Enable the machine combiner pass"),
59                                cl::init(true), cl::Hidden);
60 
61 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
62   // Register the target.
63   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
64   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
65 
66   PassRegistry &PR = *PassRegistry::getPassRegistry();
67   initializeX86LowerAMXIntrinsicsLegacyPassPass(PR);
68   initializeX86LowerAMXTypeLegacyPassPass(PR);
69   initializeX86PreAMXConfigPassPass(PR);
70   initializeGlobalISel(PR);
71   initializeWinEHStatePassPass(PR);
72   initializeFixupBWInstPassPass(PR);
73   initializeEvexToVexInstPassPass(PR);
74   initializeFixupLEAPassPass(PR);
75   initializeFPSPass(PR);
76   initializeX86FixupSetCCPassPass(PR);
77   initializeX86CallFrameOptimizationPass(PR);
78   initializeX86CmovConverterPassPass(PR);
79   initializeX86TileConfigPass(PR);
80   initializeX86FastTileConfigPass(PR);
81   initializeX86LowerTileCopyPass(PR);
82   initializeX86ExpandPseudoPass(PR);
83   initializeX86ExecutionDomainFixPass(PR);
84   initializeX86DomainReassignmentPass(PR);
85   initializeX86AvoidSFBPassPass(PR);
86   initializeX86AvoidTrailingCallPassPass(PR);
87   initializeX86SpeculativeLoadHardeningPassPass(PR);
88   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
89   initializeX86FlagsCopyLoweringPassPass(PR);
90   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
91   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
92   initializeX86OptimizeLEAPassPass(PR);
93   initializeX86PartialReductionPass(PR);
94   initializePseudoProbeInserterPass(PR);
95 }
96 
97 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
98   if (TT.isOSBinFormatMachO()) {
99     if (TT.getArch() == Triple::x86_64)
100       return std::make_unique<X86_64MachoTargetObjectFile>();
101     return std::make_unique<TargetLoweringObjectFileMachO>();
102   }
103 
104   if (TT.isOSBinFormatCOFF())
105     return std::make_unique<TargetLoweringObjectFileCOFF>();
106   return std::make_unique<X86ELFTargetObjectFile>();
107 }
108 
109 static std::string computeDataLayout(const Triple &TT) {
110   // X86 is little endian
111   std::string Ret = "e";
112 
113   Ret += DataLayout::getManglingComponent(TT);
114   // X86 and x32 have 32 bit pointers.
115   if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
116     Ret += "-p:32:32";
117 
118   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
119   Ret += "-p270:32:32-p271:32:32-p272:64:64";
120 
121   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
122   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
123     Ret += "-i64:64";
124   else if (TT.isOSIAMCU())
125     Ret += "-i64:32-f64:32";
126   else
127     Ret += "-f64:32:64";
128 
129   // Some ABIs align long double to 128 bits, others to 32.
130   if (TT.isOSNaCl() || TT.isOSIAMCU())
131     ; // No f80
132   else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
133     Ret += "-f80:128";
134   else
135     Ret += "-f80:32";
136 
137   if (TT.isOSIAMCU())
138     Ret += "-f128:32";
139 
140   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
141   if (TT.isArch64Bit())
142     Ret += "-n8:16:32:64";
143   else
144     Ret += "-n8:16:32";
145 
146   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
147   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
148     Ret += "-a:0:32-S32";
149   else
150     Ret += "-S128";
151 
152   return Ret;
153 }
154 
155 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
156                                            bool JIT,
157                                            Optional<Reloc::Model> RM) {
158   bool is64Bit = TT.getArch() == Triple::x86_64;
159   if (!RM.hasValue()) {
160     // JIT codegen should use static relocations by default, since it's
161     // typically executed in process and not relocatable.
162     if (JIT)
163       return Reloc::Static;
164 
165     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
166     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
167     // use static relocation model by default.
168     if (TT.isOSDarwin()) {
169       if (is64Bit)
170         return Reloc::PIC_;
171       return Reloc::DynamicNoPIC;
172     }
173     if (TT.isOSWindows() && is64Bit)
174       return Reloc::PIC_;
175     return Reloc::Static;
176   }
177 
178   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
179   // is defined as a model for code which may be used in static or dynamic
180   // executables but not necessarily a shared library. On X86-32 we just
181   // compile in -static mode, in x86-64 we use PIC.
182   if (*RM == Reloc::DynamicNoPIC) {
183     if (is64Bit)
184       return Reloc::PIC_;
185     if (!TT.isOSDarwin())
186       return Reloc::Static;
187   }
188 
189   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
190   // the Mach-O file format doesn't support it.
191   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
192     return Reloc::PIC_;
193 
194   return *RM;
195 }
196 
197 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
198                                                  bool JIT, bool Is64Bit) {
199   if (CM) {
200     if (*CM == CodeModel::Tiny)
201       report_fatal_error("Target does not support the tiny CodeModel", false);
202     return *CM;
203   }
204   if (JIT)
205     return Is64Bit ? CodeModel::Large : CodeModel::Small;
206   return CodeModel::Small;
207 }
208 
209 /// Create an X86 target.
210 ///
211 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
212                                    StringRef CPU, StringRef FS,
213                                    const TargetOptions &Options,
214                                    Optional<Reloc::Model> RM,
215                                    Optional<CodeModel::Model> CM,
216                                    CodeGenOpt::Level OL, bool JIT)
217     : LLVMTargetMachine(
218           T, computeDataLayout(TT), TT, CPU, FS, Options,
219           getEffectiveRelocModel(TT, JIT, RM),
220           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
221           OL),
222       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
223   // On PS4, the "return address" of a 'noreturn' call must still be within
224   // the calling function, and TrapUnreachable is an easy way to get that.
225   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
226     this->Options.TrapUnreachable = true;
227     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
228   }
229 
230   setMachineOutliner(true);
231 
232   // x86 supports the debug entry values.
233   setSupportsDebugEntryValues(true);
234 
235   initAsmInfo();
236 }
237 
238 X86TargetMachine::~X86TargetMachine() = default;
239 
240 const X86Subtarget *
241 X86TargetMachine::getSubtargetImpl(const Function &F) const {
242   Attribute CPUAttr = F.getFnAttribute("target-cpu");
243   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
244   Attribute FSAttr = F.getFnAttribute("target-features");
245 
246   StringRef CPU =
247       CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
248   StringRef TuneCPU =
249       TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
250   StringRef FS =
251       FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
252 
253   SmallString<512> Key;
254   // The additions here are ordered so that the definitely short strings are
255   // added first so we won't exceed the small size. We append the
256   // much longer FS string at the end so that we only heap allocate at most
257   // one time.
258 
259   // Extract prefer-vector-width attribute.
260   unsigned PreferVectorWidthOverride = 0;
261   Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
262   if (PreferVecWidthAttr.isValid()) {
263     StringRef Val = PreferVecWidthAttr.getValueAsString();
264     unsigned Width;
265     if (!Val.getAsInteger(0, Width)) {
266       Key += 'p';
267       Key += Val;
268       PreferVectorWidthOverride = Width;
269     }
270   }
271 
272   // Extract min-legal-vector-width attribute.
273   unsigned RequiredVectorWidth = UINT32_MAX;
274   Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
275   if (MinLegalVecWidthAttr.isValid()) {
276     StringRef Val = MinLegalVecWidthAttr.getValueAsString();
277     unsigned Width;
278     if (!Val.getAsInteger(0, Width)) {
279       Key += 'm';
280       Key += Val;
281       RequiredVectorWidth = Width;
282     }
283   }
284 
285   // Add CPU to the Key.
286   Key += CPU;
287 
288   // Add tune CPU to the Key.
289   Key += TuneCPU;
290 
291   // Keep track of the start of the feature portion of the string.
292   unsigned FSStart = Key.size();
293 
294   // FIXME: This is related to the code below to reset the target options,
295   // we need to know whether or not the soft float flag is set on the
296   // function before we can generate a subtarget. We also need to use
297   // it as a key for the subtarget since that can be the only difference
298   // between two functions.
299   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
300   // If the soft float attribute is set on the function turn on the soft float
301   // subtarget feature.
302   if (SoftFloat)
303     Key += FS.empty() ? "+soft-float" : "+soft-float,";
304 
305   Key += FS;
306 
307   // We may have added +soft-float to the features so move the StringRef to
308   // point to the full string in the Key.
309   FS = Key.substr(FSStart);
310 
311   auto &I = SubtargetMap[Key];
312   if (!I) {
313     // This needs to be done before we create a new subtarget since any
314     // creation will depend on the TM and the code generation flags on the
315     // function that reside in TargetOptions.
316     resetTargetOptions(F);
317     I = std::make_unique<X86Subtarget>(
318         TargetTriple, CPU, TuneCPU, FS, *this,
319         MaybeAlign(F.getParent()->getOverrideStackAlignment()),
320         PreferVectorWidthOverride, RequiredVectorWidth);
321   }
322   return I.get();
323 }
324 
325 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
326                                            unsigned DestAS) const {
327   assert(SrcAS != DestAS && "Expected different address spaces!");
328   if (getPointerSize(SrcAS) != getPointerSize(DestAS))
329     return false;
330   return SrcAS < 256 && DestAS < 256;
331 }
332 
333 //===----------------------------------------------------------------------===//
334 // X86 TTI query.
335 //===----------------------------------------------------------------------===//
336 
337 TargetTransformInfo
338 X86TargetMachine::getTargetTransformInfo(const Function &F) const {
339   return TargetTransformInfo(X86TTIImpl(this, F));
340 }
341 
342 //===----------------------------------------------------------------------===//
343 // Pass Pipeline Configuration
344 //===----------------------------------------------------------------------===//
345 
346 namespace {
347 
348 /// X86 Code Generator Pass Configuration Options.
349 class X86PassConfig : public TargetPassConfig {
350 public:
351   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
352     : TargetPassConfig(TM, PM) {}
353 
354   X86TargetMachine &getX86TargetMachine() const {
355     return getTM<X86TargetMachine>();
356   }
357 
358   ScheduleDAGInstrs *
359   createMachineScheduler(MachineSchedContext *C) const override {
360     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
361     DAG->addMutation(createX86MacroFusionDAGMutation());
362     return DAG;
363   }
364 
365   ScheduleDAGInstrs *
366   createPostMachineScheduler(MachineSchedContext *C) const override {
367     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
368     DAG->addMutation(createX86MacroFusionDAGMutation());
369     return DAG;
370   }
371 
372   void addIRPasses() override;
373   bool addInstSelector() override;
374   bool addIRTranslator() override;
375   bool addLegalizeMachineIR() override;
376   bool addRegBankSelect() override;
377   bool addGlobalInstructionSelect() override;
378   bool addILPOpts() override;
379   bool addPreISel() override;
380   void addMachineSSAOptimization() override;
381   void addPreRegAlloc() override;
382   bool addPostFastRegAllocRewrite() override;
383   void addPostRegAlloc() override;
384   void addPreEmitPass() override;
385   void addPreEmitPass2() override;
386   void addPreSched2() override;
387   bool addPreRewrite() override;
388 
389   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
390 };
391 
392 class X86ExecutionDomainFix : public ExecutionDomainFix {
393 public:
394   static char ID;
395   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
396   StringRef getPassName() const override {
397     return "X86 Execution Dependency Fix";
398   }
399 };
400 char X86ExecutionDomainFix::ID;
401 
402 } // end anonymous namespace
403 
404 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
405   "X86 Execution Domain Fix", false, false)
406 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
407 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
408   "X86 Execution Domain Fix", false, false)
409 
410 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
411   return new X86PassConfig(*this, PM);
412 }
413 
414 void X86PassConfig::addIRPasses() {
415   addPass(createAtomicExpandPass());
416 
417   // We add both pass anyway and when these two passes run, we skip the pass
418   // based on the option level and option attribute.
419   addPass(createX86LowerAMXIntrinsicsPass());
420   addPass(createX86LowerAMXTypePass());
421 
422   if (TM->getOptLevel() == CodeGenOpt::None)
423     addPass(createX86PreAMXConfigPass());
424 
425   TargetPassConfig::addIRPasses();
426 
427   if (TM->getOptLevel() != CodeGenOpt::None) {
428     addPass(createInterleavedAccessPass());
429     addPass(createX86PartialReductionPass());
430   }
431 
432   // Add passes that handle indirect branch removal and insertion of a retpoline
433   // thunk. These will be a no-op unless a function subtarget has the retpoline
434   // feature enabled.
435   addPass(createIndirectBrExpandPass());
436 
437   // Add Control Flow Guard checks.
438   const Triple &TT = TM->getTargetTriple();
439   if (TT.isOSWindows()) {
440     if (TT.getArch() == Triple::x86_64) {
441       addPass(createCFGuardDispatchPass());
442     } else {
443       addPass(createCFGuardCheckPass());
444     }
445   }
446 
447   if (TM->Options.JMCInstrument)
448     addPass(createJMCInstrumenterPass());
449 }
450 
451 bool X86PassConfig::addInstSelector() {
452   // Install an instruction selector.
453   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
454 
455   // For ELF, cleanup any local-dynamic TLS accesses.
456   if (TM->getTargetTriple().isOSBinFormatELF() &&
457       getOptLevel() != CodeGenOpt::None)
458     addPass(createCleanupLocalDynamicTLSPass());
459 
460   addPass(createX86GlobalBaseRegPass());
461   return false;
462 }
463 
464 bool X86PassConfig::addIRTranslator() {
465   addPass(new IRTranslator(getOptLevel()));
466   return false;
467 }
468 
469 bool X86PassConfig::addLegalizeMachineIR() {
470   addPass(new Legalizer());
471   return false;
472 }
473 
474 bool X86PassConfig::addRegBankSelect() {
475   addPass(new RegBankSelect());
476   return false;
477 }
478 
479 bool X86PassConfig::addGlobalInstructionSelect() {
480   addPass(new InstructionSelect(getOptLevel()));
481   return false;
482 }
483 
484 bool X86PassConfig::addILPOpts() {
485   addPass(&EarlyIfConverterID);
486   if (EnableMachineCombinerPass)
487     addPass(&MachineCombinerID);
488   addPass(createX86CmovConverterPass());
489   return true;
490 }
491 
492 bool X86PassConfig::addPreISel() {
493   // Only add this pass for 32-bit x86 Windows.
494   const Triple &TT = TM->getTargetTriple();
495   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
496     addPass(createX86WinEHStatePass());
497   return true;
498 }
499 
500 void X86PassConfig::addPreRegAlloc() {
501   if (getOptLevel() != CodeGenOpt::None) {
502     addPass(&LiveRangeShrinkID);
503     addPass(createX86FixupSetCC());
504     addPass(createX86OptimizeLEAs());
505     addPass(createX86CallFrameOptimization());
506     addPass(createX86AvoidStoreForwardingBlocks());
507   }
508 
509   addPass(createX86SpeculativeLoadHardeningPass());
510   addPass(createX86FlagsCopyLoweringPass());
511   addPass(createX86DynAllocaExpander());
512 
513   if (getOptLevel() != CodeGenOpt::None) {
514     addPass(createX86PreTileConfigPass());
515   }
516 }
517 
518 void X86PassConfig::addMachineSSAOptimization() {
519   addPass(createX86DomainReassignmentPass());
520   TargetPassConfig::addMachineSSAOptimization();
521 }
522 
523 void X86PassConfig::addPostRegAlloc() {
524   addPass(createX86LowerTileCopyPass());
525   addPass(createX86FloatingPointStackifierPass());
526   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
527   // to using the Speculative Execution Side Effect Suppression pass for
528   // mitigation. This is to prevent slow downs due to
529   // analyses needed by the LVIHardening pass when compiling at -O0.
530   if (getOptLevel() != CodeGenOpt::None)
531     addPass(createX86LoadValueInjectionLoadHardeningPass());
532 }
533 
534 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
535 
536 void X86PassConfig::addPreEmitPass() {
537   if (getOptLevel() != CodeGenOpt::None) {
538     addPass(new X86ExecutionDomainFix());
539     addPass(createBreakFalseDeps());
540   }
541 
542   addPass(createX86IndirectBranchTrackingPass());
543 
544   addPass(createX86IssueVZeroUpperPass());
545 
546   if (getOptLevel() != CodeGenOpt::None) {
547     addPass(createX86FixupBWInsts());
548     addPass(createX86PadShortFunctions());
549     addPass(createX86FixupLEAs());
550   }
551   addPass(createX86EvexToVexInsts());
552   addPass(createX86DiscriminateMemOpsPass());
553   addPass(createX86InsertPrefetchPass());
554   addPass(createX86InsertX87waitPass());
555 }
556 
557 void X86PassConfig::addPreEmitPass2() {
558   const Triple &TT = TM->getTargetTriple();
559   const MCAsmInfo *MAI = TM->getMCAsmInfo();
560 
561   // The X86 Speculative Execution Pass must run after all control
562   // flow graph modifying passes. As a result it was listed to run right before
563   // the X86 Retpoline Thunks pass. The reason it must run after control flow
564   // graph modifications is that the model of LFENCE in LLVM has to be updated
565   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
566   // placement of this pass was hand checked to ensure that the subsequent
567   // passes don't move the code around the LFENCEs in a way that will hurt the
568   // correctness of this pass. This placement has been shown to work based on
569   // hand inspection of the codegen output.
570   addPass(createX86SpeculativeExecutionSideEffectSuppression());
571   addPass(createX86IndirectThunksPass());
572 
573   // Insert extra int3 instructions after trailing call instructions to avoid
574   // issues in the unwinder.
575   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
576     addPass(createX86AvoidTrailingCallPass());
577 
578   // Verify basic block incoming and outgoing cfa offset and register values and
579   // correct CFA calculation rule where needed by inserting appropriate CFI
580   // instructions.
581   if (!TT.isOSDarwin() &&
582       (!TT.isOSWindows() ||
583        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
584     addPass(createCFIInstrInserter());
585 
586   if (TT.isOSWindows()) {
587     // Identify valid longjmp targets for Windows Control Flow Guard.
588     addPass(createCFGuardLongjmpPass());
589     // Identify valid eh continuation targets for Windows EHCont Guard.
590     addPass(createEHContGuardCatchretPass());
591   }
592   addPass(createX86LoadValueInjectionRetHardeningPass());
593 
594   // Insert pseudo probe annotation for callsite profiling
595   addPass(createPseudoProbeInserter());
596 
597   // On Darwin platforms, BLR_RVMARKER pseudo instructions are lowered to
598   // bundles.
599   if (TT.isOSDarwin())
600     addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
601       // Only run bundle expansion if there are relevant ObjC runtime functions
602       // present in the module.
603       const Function &F = MF.getFunction();
604       const Module *M = F.getParent();
605       return M->getFunction("objc_retainAutoreleasedReturnValue") ||
606              M->getFunction("objc_unsafeClaimAutoreleasedReturnValue");
607     }));
608 }
609 
610 bool X86PassConfig::addPostFastRegAllocRewrite() {
611   addPass(createX86FastTileConfigPass());
612   return true;
613 }
614 
615 bool X86PassConfig::addPreRewrite() {
616   addPass(createX86TileConfigPass());
617   return true;
618 }
619 
620 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
621   return getStandardCSEConfigForOpt(TM->getOptLevel());
622 }
623