1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
60                                cl::desc("Enable the conditional branch "
61                                         "folding pass"),
62                                cl::init(false), cl::Hidden);
63 
64 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
65   // Register the target.
66   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
67   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
68 
69   PassRegistry &PR = *PassRegistry::getPassRegistry();
70   initializeGlobalISel(PR);
71   initializeWinEHStatePassPass(PR);
72   initializeFixupBWInstPassPass(PR);
73   initializeEvexToVexInstPassPass(PR);
74   initializeFixupLEAPassPass(PR);
75   initializeFPSPass(PR);
76   initializeX86FixupSetCCPassPass(PR);
77   initializeX86CallFrameOptimizationPass(PR);
78   initializeX86CmovConverterPassPass(PR);
79   initializeX86ExpandPseudoPass(PR);
80   initializeX86ExecutionDomainFixPass(PR);
81   initializeX86DomainReassignmentPass(PR);
82   initializeX86AvoidSFBPassPass(PR);
83   initializeX86AvoidTrailingCallPassPass(PR);
84   initializeX86SpeculativeLoadHardeningPassPass(PR);
85   initializeX86FlagsCopyLoweringPassPass(PR);
86   initializeX86CondBrFoldingPassPass(PR);
87   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
88   initializeX86OptimizeLEAPassPass(PR);
89   initializeX86PartialReductionPass(PR);
90 }
91 
92 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
93   if (TT.isOSBinFormatMachO()) {
94     if (TT.getArch() == Triple::x86_64)
95       return std::make_unique<X86_64MachoTargetObjectFile>();
96     return std::make_unique<TargetLoweringObjectFileMachO>();
97   }
98 
99   if (TT.isOSBinFormatCOFF())
100     return std::make_unique<TargetLoweringObjectFileCOFF>();
101   return std::make_unique<X86ELFTargetObjectFile>();
102 }
103 
104 static std::string computeDataLayout(const Triple &TT) {
105   // X86 is little endian
106   std::string Ret = "e";
107 
108   Ret += DataLayout::getManglingComponent(TT);
109   // X86 and x32 have 32 bit pointers.
110   if ((TT.isArch64Bit() &&
111        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
112       !TT.isArch64Bit())
113     Ret += "-p:32:32";
114 
115   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
116   Ret += "-p270:32:32-p271:32:32-p272:64:64";
117 
118   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
119   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
120     Ret += "-i64:64";
121   else if (TT.isOSIAMCU())
122     Ret += "-i64:32-f64:32";
123   else
124     Ret += "-f64:32:64";
125 
126   // Some ABIs align long double to 128 bits, others to 32.
127   if (TT.isOSNaCl() || TT.isOSIAMCU())
128     ; // No f80
129   else if (TT.isArch64Bit() || TT.isOSDarwin())
130     Ret += "-f80:128";
131   else
132     Ret += "-f80:32";
133 
134   if (TT.isOSIAMCU())
135     Ret += "-f128:32";
136 
137   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
138   if (TT.isArch64Bit())
139     Ret += "-n8:16:32:64";
140   else
141     Ret += "-n8:16:32";
142 
143   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
144   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
145     Ret += "-a:0:32-S32";
146   else
147     Ret += "-S128";
148 
149   return Ret;
150 }
151 
152 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
153                                            bool JIT,
154                                            Optional<Reloc::Model> RM) {
155   bool is64Bit = TT.getArch() == Triple::x86_64;
156   if (!RM.hasValue()) {
157     // JIT codegen should use static relocations by default, since it's
158     // typically executed in process and not relocatable.
159     if (JIT)
160       return Reloc::Static;
161 
162     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
163     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
164     // use static relocation model by default.
165     if (TT.isOSDarwin()) {
166       if (is64Bit)
167         return Reloc::PIC_;
168       return Reloc::DynamicNoPIC;
169     }
170     if (TT.isOSWindows() && is64Bit)
171       return Reloc::PIC_;
172     return Reloc::Static;
173   }
174 
175   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
176   // is defined as a model for code which may be used in static or dynamic
177   // executables but not necessarily a shared library. On X86-32 we just
178   // compile in -static mode, in x86-64 we use PIC.
179   if (*RM == Reloc::DynamicNoPIC) {
180     if (is64Bit)
181       return Reloc::PIC_;
182     if (!TT.isOSDarwin())
183       return Reloc::Static;
184   }
185 
186   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
187   // the Mach-O file format doesn't support it.
188   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
189     return Reloc::PIC_;
190 
191   return *RM;
192 }
193 
194 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
195                                                  bool JIT, bool Is64Bit) {
196   if (CM) {
197     if (*CM == CodeModel::Tiny)
198       report_fatal_error("Target does not support the tiny CodeModel", false);
199     return *CM;
200   }
201   if (JIT)
202     return Is64Bit ? CodeModel::Large : CodeModel::Small;
203   return CodeModel::Small;
204 }
205 
206 /// Create an X86 target.
207 ///
208 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
209                                    StringRef CPU, StringRef FS,
210                                    const TargetOptions &Options,
211                                    Optional<Reloc::Model> RM,
212                                    Optional<CodeModel::Model> CM,
213                                    CodeGenOpt::Level OL, bool JIT)
214     : LLVMTargetMachine(
215           T, computeDataLayout(TT), TT, CPU, FS, Options,
216           getEffectiveRelocModel(TT, JIT, RM),
217           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
218           OL),
219       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
220   // On PS4, the "return address" of a 'noreturn' call must still be within
221   // the calling function, and TrapUnreachable is an easy way to get that.
222   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
223     this->Options.TrapUnreachable = true;
224     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
225   }
226 
227   setMachineOutliner(true);
228 
229   // x86 supports the debug entry values.
230   setSupportsDebugEntryValues(true);
231 
232   initAsmInfo();
233 }
234 
235 X86TargetMachine::~X86TargetMachine() = default;
236 
237 const X86Subtarget *
238 X86TargetMachine::getSubtargetImpl(const Function &F) const {
239   Attribute CPUAttr = F.getFnAttribute("target-cpu");
240   Attribute FSAttr = F.getFnAttribute("target-features");
241 
242   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
243                       ? CPUAttr.getValueAsString()
244                       : (StringRef)TargetCPU;
245   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
246                      ? FSAttr.getValueAsString()
247                      : (StringRef)TargetFS;
248 
249   SmallString<512> Key;
250   Key.reserve(CPU.size() + FS.size());
251   Key += CPU;
252   Key += FS;
253 
254   // FIXME: This is related to the code below to reset the target options,
255   // we need to know whether or not the soft float flag is set on the
256   // function before we can generate a subtarget. We also need to use
257   // it as a key for the subtarget since that can be the only difference
258   // between two functions.
259   bool SoftFloat =
260       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
261   // If the soft float attribute is set on the function turn on the soft float
262   // subtarget feature.
263   if (SoftFloat)
264     Key += FS.empty() ? "+soft-float" : ",+soft-float";
265 
266   // Keep track of the key width after all features are added so we can extract
267   // the feature string out later.
268   unsigned CPUFSWidth = Key.size();
269 
270   // Extract prefer-vector-width attribute.
271   unsigned PreferVectorWidthOverride = 0;
272   if (F.hasFnAttribute("prefer-vector-width")) {
273     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
274     unsigned Width;
275     if (!Val.getAsInteger(0, Width)) {
276       Key += ",prefer-vector-width=";
277       Key += Val;
278       PreferVectorWidthOverride = Width;
279     }
280   }
281 
282   // Extract min-legal-vector-width attribute.
283   unsigned RequiredVectorWidth = UINT32_MAX;
284   if (F.hasFnAttribute("min-legal-vector-width")) {
285     StringRef Val =
286         F.getFnAttribute("min-legal-vector-width").getValueAsString();
287     unsigned Width;
288     if (!Val.getAsInteger(0, Width)) {
289       Key += ",min-legal-vector-width=";
290       Key += Val;
291       RequiredVectorWidth = Width;
292     }
293   }
294 
295   // Extracted here so that we make sure there is backing for the StringRef. If
296   // we assigned earlier, its possible the SmallString reallocated leaving a
297   // dangling StringRef.
298   FS = Key.slice(CPU.size(), CPUFSWidth);
299 
300   auto &I = SubtargetMap[Key];
301   if (!I) {
302     // This needs to be done before we create a new subtarget since any
303     // creation will depend on the TM and the code generation flags on the
304     // function that reside in TargetOptions.
305     resetTargetOptions(F);
306     I = std::make_unique<X86Subtarget>(
307         TargetTriple, CPU, FS, *this,
308         MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
309         RequiredVectorWidth);
310   }
311   return I.get();
312 }
313 
314 //===----------------------------------------------------------------------===//
315 // Command line options for x86
316 //===----------------------------------------------------------------------===//
317 static cl::opt<bool>
318 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
319   cl::desc("Minimize AVX to SSE transition penalty"),
320   cl::init(true));
321 
322 //===----------------------------------------------------------------------===//
323 // X86 TTI query.
324 //===----------------------------------------------------------------------===//
325 
326 TargetTransformInfo
327 X86TargetMachine::getTargetTransformInfo(const Function &F) {
328   return TargetTransformInfo(X86TTIImpl(this, F));
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // Pass Pipeline Configuration
333 //===----------------------------------------------------------------------===//
334 
335 namespace {
336 
337 /// X86 Code Generator Pass Configuration Options.
338 class X86PassConfig : public TargetPassConfig {
339 public:
340   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
341     : TargetPassConfig(TM, PM) {}
342 
343   X86TargetMachine &getX86TargetMachine() const {
344     return getTM<X86TargetMachine>();
345   }
346 
347   ScheduleDAGInstrs *
348   createMachineScheduler(MachineSchedContext *C) const override {
349     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
350     DAG->addMutation(createX86MacroFusionDAGMutation());
351     return DAG;
352   }
353 
354   ScheduleDAGInstrs *
355   createPostMachineScheduler(MachineSchedContext *C) const override {
356     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
357     DAG->addMutation(createX86MacroFusionDAGMutation());
358     return DAG;
359   }
360 
361   void addIRPasses() override;
362   bool addInstSelector() override;
363   bool addIRTranslator() override;
364   bool addLegalizeMachineIR() override;
365   bool addRegBankSelect() override;
366   bool addGlobalInstructionSelect() override;
367   bool addILPOpts() override;
368   bool addPreISel() override;
369   void addMachineSSAOptimization() override;
370   void addPreRegAlloc() override;
371   void addPostRegAlloc() override;
372   void addPreEmitPass() override;
373   void addPreEmitPass2() override;
374   void addPreSched2() override;
375 
376   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
377 };
378 
379 class X86ExecutionDomainFix : public ExecutionDomainFix {
380 public:
381   static char ID;
382   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
383   StringRef getPassName() const override {
384     return "X86 Execution Dependency Fix";
385   }
386 };
387 char X86ExecutionDomainFix::ID;
388 
389 } // end anonymous namespace
390 
391 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
392   "X86 Execution Domain Fix", false, false)
393 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
394 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
395   "X86 Execution Domain Fix", false, false)
396 
397 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
398   return new X86PassConfig(*this, PM);
399 }
400 
401 void X86PassConfig::addIRPasses() {
402   addPass(createAtomicExpandPass());
403 
404   TargetPassConfig::addIRPasses();
405 
406   if (TM->getOptLevel() != CodeGenOpt::None) {
407     addPass(createInterleavedAccessPass());
408     addPass(createX86PartialReductionPass());
409   }
410 
411   // Add passes that handle indirect branch removal and insertion of a retpoline
412   // thunk. These will be a no-op unless a function subtarget has the retpoline
413   // feature enabled.
414   addPass(createIndirectBrExpandPass());
415 
416   // Add Control Flow Guard checks.
417   const Triple &TT = TM->getTargetTriple();
418   if (TT.isOSWindows()) {
419     if (TT.getArch() == Triple::x86_64) {
420       addPass(createCFGuardDispatchPass());
421     } else {
422       addPass(createCFGuardCheckPass());
423     }
424   }
425 }
426 
427 bool X86PassConfig::addInstSelector() {
428   // Install an instruction selector.
429   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
430 
431   // For ELF, cleanup any local-dynamic TLS accesses.
432   if (TM->getTargetTriple().isOSBinFormatELF() &&
433       getOptLevel() != CodeGenOpt::None)
434     addPass(createCleanupLocalDynamicTLSPass());
435 
436   addPass(createX86GlobalBaseRegPass());
437   return false;
438 }
439 
440 bool X86PassConfig::addIRTranslator() {
441   addPass(new IRTranslator());
442   return false;
443 }
444 
445 bool X86PassConfig::addLegalizeMachineIR() {
446   addPass(new Legalizer());
447   return false;
448 }
449 
450 bool X86PassConfig::addRegBankSelect() {
451   addPass(new RegBankSelect());
452   return false;
453 }
454 
455 bool X86PassConfig::addGlobalInstructionSelect() {
456   addPass(new InstructionSelect());
457   return false;
458 }
459 
460 bool X86PassConfig::addILPOpts() {
461   if (EnableCondBrFoldingPass)
462     addPass(createX86CondBrFolding());
463   addPass(&EarlyIfConverterID);
464   if (EnableMachineCombinerPass)
465     addPass(&MachineCombinerID);
466   addPass(createX86CmovConverterPass());
467   return true;
468 }
469 
470 bool X86PassConfig::addPreISel() {
471   // Only add this pass for 32-bit x86 Windows.
472   const Triple &TT = TM->getTargetTriple();
473   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
474     addPass(createX86WinEHStatePass());
475   return true;
476 }
477 
478 void X86PassConfig::addPreRegAlloc() {
479   if (getOptLevel() != CodeGenOpt::None) {
480     addPass(&LiveRangeShrinkID);
481     addPass(createX86FixupSetCC());
482     addPass(createX86OptimizeLEAs());
483     addPass(createX86CallFrameOptimization());
484     addPass(createX86AvoidStoreForwardingBlocks());
485   }
486 
487   addPass(createX86SpeculativeLoadHardeningPass());
488   addPass(createX86FlagsCopyLoweringPass());
489   addPass(createX86WinAllocaExpander());
490 }
491 void X86PassConfig::addMachineSSAOptimization() {
492   addPass(createX86DomainReassignmentPass());
493   TargetPassConfig::addMachineSSAOptimization();
494 }
495 
496 void X86PassConfig::addPostRegAlloc() {
497   addPass(createX86FloatingPointStackifierPass());
498 }
499 
500 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
501 
502 void X86PassConfig::addPreEmitPass() {
503   if (getOptLevel() != CodeGenOpt::None) {
504     addPass(new X86ExecutionDomainFix());
505     addPass(createBreakFalseDeps());
506   }
507 
508   addPass(createX86IndirectBranchTrackingPass());
509 
510   if (UseVZeroUpper)
511     addPass(createX86IssueVZeroUpperPass());
512 
513   if (getOptLevel() != CodeGenOpt::None) {
514     addPass(createX86FixupBWInsts());
515     addPass(createX86PadShortFunctions());
516     addPass(createX86FixupLEAs());
517     addPass(createX86EvexToVexInsts());
518   }
519   addPass(createX86DiscriminateMemOpsPass());
520   addPass(createX86InsertPrefetchPass());
521   addPass(createX86InsertX87waitPass());
522 }
523 
524 void X86PassConfig::addPreEmitPass2() {
525   const Triple &TT = TM->getTargetTriple();
526   const MCAsmInfo *MAI = TM->getMCAsmInfo();
527 
528   addPass(createX86IndirectThunksPass());
529 
530   // Insert extra int3 instructions after trailing call instructions to avoid
531   // issues in the unwinder.
532   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
533     addPass(createX86AvoidTrailingCallPass());
534 
535   // Verify basic block incoming and outgoing cfa offset and register values and
536   // correct CFA calculation rule where needed by inserting appropriate CFI
537   // instructions.
538   if (!TT.isOSDarwin() &&
539       (!TT.isOSWindows() ||
540        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
541     addPass(createCFIInstrInserter());
542   // Identify valid longjmp targets for Windows Control Flow Guard.
543   if (TT.isOSWindows())
544     addPass(createCFGuardLongjmpPass());
545   addPass(createX86LoadValueInjectionRetHardeningPass());
546 }
547 
548 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
549   return getStandardCSEConfigForOpt(TM->getOptLevel());
550 }
551