1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 extern "C" void LLVMInitializeX86Target() {
26   // Register the target.
27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
29 }
30 
31 void X86_32TargetMachine::anchor() { }
32 
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34   // X86 is little endian
35   std::string Ret = "e";
36 
37   // X86 and x32 have 32 bit pointers.
38   if (ST.isTarget64BitILP32() || !ST.is64Bit())
39     Ret += "-p:32:32";
40 
41   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42   if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
43       ST.isTargetNaCl())
44     Ret += "-i64:64";
45   else
46     Ret += "-f64:32:64";
47 
48   // Some ABIs align long double to 128 bits, others to 32.
49   if (ST.isTargetNaCl())
50     ; // No f80
51   else if (ST.is64Bit() || ST.isTargetDarwin())
52     Ret += "-f80:128";
53   else
54     Ret += "-f80:32";
55 
56   // Objects on the stack ore aligned to 64 bits.
57   if (ST.is64Bit())
58     Ret += "-s:64";
59 
60   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
61   if (ST.is64Bit())
62     Ret += "-n8:16:32:64";
63   else
64     Ret += "-n8:16:32";
65 
66   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
67   if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
68     Ret += "-S32";
69   else
70     Ret += "-S128";
71 
72   return Ret;
73 }
74 
75 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
76                                          StringRef CPU, StringRef FS,
77                                          const TargetOptions &Options,
78                                          Reloc::Model RM, CodeModel::Model CM,
79                                          CodeGenOpt::Level OL)
80   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
81     DL(computeDataLayout(*getSubtargetImpl())),
82     InstrInfo(*this),
83     TLInfo(*this),
84     TSInfo(*this),
85     JITInfo(*this) {
86   initAsmInfo();
87 }
88 
89 void X86_64TargetMachine::anchor() { }
90 
91 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
92                                          StringRef CPU, StringRef FS,
93                                          const TargetOptions &Options,
94                                          Reloc::Model RM, CodeModel::Model CM,
95                                          CodeGenOpt::Level OL)
96   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
97     // The x32 ABI dictates the ILP32 programming model for x64.
98     DL(computeDataLayout(*getSubtargetImpl())),
99     InstrInfo(*this),
100     TLInfo(*this),
101     TSInfo(*this),
102     JITInfo(*this) {
103   initAsmInfo();
104 }
105 
106 /// X86TargetMachine ctor - Create an X86 target.
107 ///
108 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
109                                    StringRef CPU, StringRef FS,
110                                    const TargetOptions &Options,
111                                    Reloc::Model RM, CodeModel::Model CM,
112                                    CodeGenOpt::Level OL,
113                                    bool is64Bit)
114   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
115     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
116     FrameLowering(*this, Subtarget),
117     InstrItins(Subtarget.getInstrItineraryData()){
118   // Determine the PICStyle based on the target selected.
119   if (getRelocationModel() == Reloc::Static) {
120     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
121     Subtarget.setPICStyle(PICStyles::None);
122   } else if (Subtarget.is64Bit()) {
123     // PIC in 64 bit mode is always rip-rel.
124     Subtarget.setPICStyle(PICStyles::RIPRel);
125   } else if (Subtarget.isTargetCOFF()) {
126     Subtarget.setPICStyle(PICStyles::None);
127   } else if (Subtarget.isTargetDarwin()) {
128     if (getRelocationModel() == Reloc::PIC_)
129       Subtarget.setPICStyle(PICStyles::StubPIC);
130     else {
131       assert(getRelocationModel() == Reloc::DynamicNoPIC);
132       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
133     }
134   } else if (Subtarget.isTargetELF()) {
135     Subtarget.setPICStyle(PICStyles::GOT);
136   }
137 
138   // default to hard float ABI
139   if (Options.FloatABIType == FloatABI::Default)
140     this->Options.FloatABIType = FloatABI::Hard;
141 }
142 
143 //===----------------------------------------------------------------------===//
144 // Command line options for x86
145 //===----------------------------------------------------------------------===//
146 static cl::opt<bool>
147 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
148   cl::desc("Minimize AVX to SSE transition penalty"),
149   cl::init(true));
150 
151 // Temporary option to control early if-conversion for x86 while adding machine
152 // models.
153 static cl::opt<bool>
154 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
155 	       cl::desc("Enable early if-conversion on X86"));
156 
157 //===----------------------------------------------------------------------===//
158 // X86 Analysis Pass Setup
159 //===----------------------------------------------------------------------===//
160 
161 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
162   // Add first the target-independent BasicTTI pass, then our X86 pass. This
163   // allows the X86 pass to delegate to the target independent layer when
164   // appropriate.
165   PM.add(createBasicTargetTransformInfoPass(this));
166   PM.add(createX86TargetTransformInfoPass(this));
167 }
168 
169 
170 //===----------------------------------------------------------------------===//
171 // Pass Pipeline Configuration
172 //===----------------------------------------------------------------------===//
173 
174 namespace {
175 /// X86 Code Generator Pass Configuration Options.
176 class X86PassConfig : public TargetPassConfig {
177 public:
178   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
179     : TargetPassConfig(TM, PM) {}
180 
181   X86TargetMachine &getX86TargetMachine() const {
182     return getTM<X86TargetMachine>();
183   }
184 
185   const X86Subtarget &getX86Subtarget() const {
186     return *getX86TargetMachine().getSubtargetImpl();
187   }
188 
189   virtual bool addInstSelector();
190   virtual bool addILPOpts();
191   virtual bool addPreRegAlloc();
192   virtual bool addPostRegAlloc();
193   virtual bool addPreEmitPass();
194 };
195 } // namespace
196 
197 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
198   return new X86PassConfig(this, PM);
199 }
200 
201 bool X86PassConfig::addInstSelector() {
202   // Install an instruction selector.
203   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
204 
205   // For ELF, cleanup any local-dynamic TLS accesses.
206   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
207     addPass(createCleanupLocalDynamicTLSPass());
208 
209   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
210   if (!getX86Subtarget().is64Bit())
211     addPass(createGlobalBaseRegPass());
212 
213   return false;
214 }
215 
216 bool X86PassConfig::addILPOpts() {
217   if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
218     addPass(&EarlyIfConverterID);
219     return true;
220   }
221   return false;
222 }
223 
224 bool X86PassConfig::addPreRegAlloc() {
225   return false;  // -print-machineinstr shouldn't print after this.
226 }
227 
228 bool X86PassConfig::addPostRegAlloc() {
229   addPass(createX86FloatingPointStackifierPass());
230   return true;  // -print-machineinstr should print after this.
231 }
232 
233 bool X86PassConfig::addPreEmitPass() {
234   bool ShouldPrint = false;
235   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
236     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
237     ShouldPrint = true;
238   }
239 
240   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
241     addPass(createX86IssueVZeroUpperPass());
242     ShouldPrint = true;
243   }
244 
245   if (getOptLevel() != CodeGenOpt::None &&
246       getX86Subtarget().padShortFunctions()) {
247     addPass(createX86PadShortFunctions());
248     ShouldPrint = true;
249   }
250   if (getOptLevel() != CodeGenOpt::None &&
251       getX86Subtarget().LEAusesAG()){
252     addPass(createX86FixupLEAs());
253     ShouldPrint = true;
254   }
255 
256   return ShouldPrint;
257 }
258 
259 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
260                                       JITCodeEmitter &JCE) {
261   PM.add(createX86JITCodeEmitterPass(*this, JCE));
262 
263   return false;
264 }
265