1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86TargetObjectFile.h"
18 #include "X86TargetTransformInfo.h"
19 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
20 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
21 #include "llvm/CodeGen/MachineScheduler.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/TargetPassConfig.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Target/TargetOptions.h"
30 using namespace llvm;
31 
32 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
33                                cl::desc("Enable the machine combiner pass"),
34                                cl::init(true), cl::Hidden);
35 
36 namespace llvm {
37 void initializeWinEHStatePassPass(PassRegistry &);
38 }
39 
40 extern "C" void LLVMInitializeX86Target() {
41   // Register the target.
42   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
43   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
44 
45   PassRegistry &PR = *PassRegistry::getPassRegistry();
46   initializeGlobalISel(PR);
47   initializeWinEHStatePassPass(PR);
48   initializeFixupBWInstPassPass(PR);
49   initializeEvexToVexInstPassPass(PR);
50 }
51 
52 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
53   if (TT.isOSBinFormatMachO()) {
54     if (TT.getArch() == Triple::x86_64)
55       return make_unique<X86_64MachoTargetObjectFile>();
56     return make_unique<TargetLoweringObjectFileMachO>();
57   }
58 
59   if (TT.isOSFreeBSD())
60     return make_unique<X86FreeBSDTargetObjectFile>();
61   if (TT.isOSLinux() || TT.isOSNaCl())
62     return make_unique<X86LinuxNaClTargetObjectFile>();
63   if (TT.isOSFuchsia())
64     return make_unique<X86FuchsiaTargetObjectFile>();
65   if (TT.isOSBinFormatELF())
66     return make_unique<X86ELFTargetObjectFile>();
67   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
68     return make_unique<X86WindowsTargetObjectFile>();
69   if (TT.isOSBinFormatCOFF())
70     return make_unique<TargetLoweringObjectFileCOFF>();
71   llvm_unreachable("unknown subtarget type");
72 }
73 
74 static std::string computeDataLayout(const Triple &TT) {
75   // X86 is little endian
76   std::string Ret = "e";
77 
78   Ret += DataLayout::getManglingComponent(TT);
79   // X86 and x32 have 32 bit pointers.
80   if ((TT.isArch64Bit() &&
81        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
82       !TT.isArch64Bit())
83     Ret += "-p:32:32";
84 
85   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
86   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
87     Ret += "-i64:64";
88   else if (TT.isOSIAMCU())
89     Ret += "-i64:32-f64:32";
90   else
91     Ret += "-f64:32:64";
92 
93   // Some ABIs align long double to 128 bits, others to 32.
94   if (TT.isOSNaCl() || TT.isOSIAMCU())
95     ; // No f80
96   else if (TT.isArch64Bit() || TT.isOSDarwin())
97     Ret += "-f80:128";
98   else
99     Ret += "-f80:32";
100 
101   if (TT.isOSIAMCU())
102     Ret += "-f128:32";
103 
104   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
105   if (TT.isArch64Bit())
106     Ret += "-n8:16:32:64";
107   else
108     Ret += "-n8:16:32";
109 
110   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
111   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
112     Ret += "-a:0:32-S32";
113   else
114     Ret += "-S128";
115 
116   return Ret;
117 }
118 
119 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
120                                            Optional<Reloc::Model> RM) {
121   bool is64Bit = TT.getArch() == Triple::x86_64;
122   if (!RM.hasValue()) {
123     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
124     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
125     // use static relocation model by default.
126     if (TT.isOSDarwin()) {
127       if (is64Bit)
128         return Reloc::PIC_;
129       return Reloc::DynamicNoPIC;
130     }
131     if (TT.isOSWindows() && is64Bit)
132       return Reloc::PIC_;
133     return Reloc::Static;
134   }
135 
136   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
137   // is defined as a model for code which may be used in static or dynamic
138   // executables but not necessarily a shared library. On X86-32 we just
139   // compile in -static mode, in x86-64 we use PIC.
140   if (*RM == Reloc::DynamicNoPIC) {
141     if (is64Bit)
142       return Reloc::PIC_;
143     if (!TT.isOSDarwin())
144       return Reloc::Static;
145   }
146 
147   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
148   // the Mach-O file format doesn't support it.
149   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
150     return Reloc::PIC_;
151 
152   return *RM;
153 }
154 
155 /// Create an X86 target.
156 ///
157 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
158                                    StringRef CPU, StringRef FS,
159                                    const TargetOptions &Options,
160                                    Optional<Reloc::Model> RM,
161                                    CodeModel::Model CM, CodeGenOpt::Level OL)
162     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
163                         getEffectiveRelocModel(TT, RM), CM, OL),
164       TLOF(createTLOF(getTargetTriple())) {
165   // Windows stack unwinder gets confused when execution flow "falls through"
166   // after a call to 'noreturn' function.
167   // To prevent that, we emit a trap for 'unreachable' IR instructions.
168   // (which on X86, happens to be the 'ud2' instruction)
169   // On PS4, the "return address" of a 'noreturn' call must still be within
170   // the calling function, and TrapUnreachable is an easy way to get that.
171   // The check here for 64-bit windows is a bit icky, but as we're unlikely
172   // to ever want to mix 32 and 64-bit windows code in a single module
173   // this should be fine.
174   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
175     this->Options.TrapUnreachable = true;
176 
177   initAsmInfo();
178 }
179 
180 X86TargetMachine::~X86TargetMachine() {}
181 
182 #ifdef LLVM_BUILD_GLOBAL_ISEL
183 namespace {
184 struct X86GISelActualAccessor : public GISelAccessor {
185   std::unique_ptr<CallLowering> CL;
186   X86GISelActualAccessor(CallLowering* CL): CL(CL) {}
187   const CallLowering *getCallLowering() const override {
188     return CL.get();
189   }
190   const InstructionSelector *getInstructionSelector() const override {
191     //TODO: Implement
192     return nullptr;
193   }
194   const LegalizerInfo *getLegalizerInfo() const override {
195     //TODO: Implement
196     return nullptr;
197   }
198   const RegisterBankInfo *getRegBankInfo() const override {
199     //TODO: Implement
200     return nullptr;
201   }
202 };
203 } // End anonymous namespace.
204 #endif
205 const X86Subtarget *
206 X86TargetMachine::getSubtargetImpl(const Function &F) const {
207   Attribute CPUAttr = F.getFnAttribute("target-cpu");
208   Attribute FSAttr = F.getFnAttribute("target-features");
209 
210   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
211                       ? CPUAttr.getValueAsString()
212                       : (StringRef)TargetCPU;
213   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
214                      ? FSAttr.getValueAsString()
215                      : (StringRef)TargetFS;
216 
217   SmallString<512> Key;
218   Key.reserve(CPU.size() + FS.size());
219   Key += CPU;
220   Key += FS;
221 
222   // FIXME: This is related to the code below to reset the target options,
223   // we need to know whether or not the soft float flag is set on the
224   // function before we can generate a subtarget. We also need to use
225   // it as a key for the subtarget since that can be the only difference
226   // between two functions.
227   bool SoftFloat =
228       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
229   // If the soft float attribute is set on the function turn on the soft float
230   // subtarget feature.
231   if (SoftFloat)
232     Key += FS.empty() ? "+soft-float" : ",+soft-float";
233 
234   FS = Key.substr(CPU.size());
235 
236   auto &I = SubtargetMap[Key];
237   if (!I) {
238     // This needs to be done before we create a new subtarget since any
239     // creation will depend on the TM and the code generation flags on the
240     // function that reside in TargetOptions.
241     resetTargetOptions(F);
242     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
243                                         Options.StackAlignmentOverride);
244 #ifndef LLVM_BUILD_GLOBAL_ISEL
245     GISelAccessor *GISel = new GISelAccessor();
246 #else
247     X86GISelActualAccessor *GISel = new X86GISelActualAccessor(
248         new X86CallLowering(*I->getTargetLowering()));
249 #endif
250     I->setGISelAccessor(*GISel);
251   }
252   return I.get();
253 }
254 
255 //===----------------------------------------------------------------------===//
256 // Command line options for x86
257 //===----------------------------------------------------------------------===//
258 static cl::opt<bool>
259 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
260   cl::desc("Minimize AVX to SSE transition penalty"),
261   cl::init(true));
262 
263 //===----------------------------------------------------------------------===//
264 // X86 TTI query.
265 //===----------------------------------------------------------------------===//
266 
267 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
268   return TargetIRAnalysis([this](const Function &F) {
269     return TargetTransformInfo(X86TTIImpl(this, F));
270   });
271 }
272 
273 
274 //===----------------------------------------------------------------------===//
275 // Pass Pipeline Configuration
276 //===----------------------------------------------------------------------===//
277 
278 namespace {
279 /// X86 Code Generator Pass Configuration Options.
280 class X86PassConfig : public TargetPassConfig {
281 public:
282   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
283     : TargetPassConfig(TM, PM) {}
284 
285   X86TargetMachine &getX86TargetMachine() const {
286     return getTM<X86TargetMachine>();
287   }
288 
289   ScheduleDAGInstrs *
290   createMachineScheduler(MachineSchedContext *C) const override {
291     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
292     DAG->addMutation(createMacroFusionDAGMutation(DAG->TII));
293     return DAG;
294   }
295 
296   void addIRPasses() override;
297   bool addInstSelector() override;
298 #ifdef LLVM_BUILD_GLOBAL_ISEL
299   bool addIRTranslator() override;
300   bool addLegalizeMachineIR() override;
301   bool addRegBankSelect() override;
302   bool addGlobalInstructionSelect() override;
303 #endif
304 bool addILPOpts() override;
305   bool addPreISel() override;
306   void addPreRegAlloc() override;
307   void addPostRegAlloc() override;
308   void addPreEmitPass() override;
309   void addPreSched2() override;
310 };
311 } // namespace
312 
313 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
314   return new X86PassConfig(this, PM);
315 }
316 
317 void X86PassConfig::addIRPasses() {
318   addPass(createAtomicExpandPass(&getX86TargetMachine()));
319 
320   TargetPassConfig::addIRPasses();
321 
322   if (TM->getOptLevel() != CodeGenOpt::None)
323     addPass(createInterleavedAccessPass(TM));
324 }
325 
326 bool X86PassConfig::addInstSelector() {
327   // Install an instruction selector.
328   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
329 
330   // For ELF, cleanup any local-dynamic TLS accesses.
331   if (TM->getTargetTriple().isOSBinFormatELF() &&
332       getOptLevel() != CodeGenOpt::None)
333     addPass(createCleanupLocalDynamicTLSPass());
334 
335   addPass(createX86GlobalBaseRegPass());
336   return false;
337 }
338 
339 #ifdef LLVM_BUILD_GLOBAL_ISEL
340 bool X86PassConfig::addIRTranslator() {
341   addPass(new IRTranslator());
342   return false;
343 }
344 
345 bool X86PassConfig::addLegalizeMachineIR() {
346   //TODO: Implement
347   return false;
348 }
349 
350 bool X86PassConfig::addRegBankSelect() {
351   //TODO: Implement
352   return false;
353 }
354 
355 bool X86PassConfig::addGlobalInstructionSelect() {
356   //TODO: Implement
357   return false;
358 }
359 #endif
360 
361 bool X86PassConfig::addILPOpts() {
362   addPass(&EarlyIfConverterID);
363   if (EnableMachineCombinerPass)
364     addPass(&MachineCombinerID);
365   return true;
366 }
367 
368 bool X86PassConfig::addPreISel() {
369   // Only add this pass for 32-bit x86 Windows.
370   const Triple &TT = TM->getTargetTriple();
371   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
372     addPass(createX86WinEHStatePass());
373   return true;
374 }
375 
376 void X86PassConfig::addPreRegAlloc() {
377   if (getOptLevel() != CodeGenOpt::None) {
378     addPass(createX86FixupSetCC());
379     addPass(createX86OptimizeLEAs());
380     addPass(createX86CallFrameOptimization());
381   }
382 
383   addPass(createX86WinAllocaExpander());
384 }
385 
386 void X86PassConfig::addPostRegAlloc() {
387   addPass(createX86FloatingPointStackifierPass());
388 }
389 
390 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
391 
392 void X86PassConfig::addPreEmitPass() {
393   if (getOptLevel() != CodeGenOpt::None)
394     addPass(createExecutionDependencyFixPass(&X86::VR128XRegClass));
395 
396   if (UseVZeroUpper)
397     addPass(createX86IssueVZeroUpperPass());
398 
399   if (getOptLevel() != CodeGenOpt::None) {
400     addPass(createX86FixupBWInsts());
401     addPass(createX86PadShortFunctions());
402     addPass(createX86FixupLEAs());
403     addPass(createX86EvexToVexInsts());
404   }
405 }
406