1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
31 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
35 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MachineScheduler.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58                                cl::desc("Enable the machine combiner pass"),
59                                cl::init(true), cl::Hidden);
60 
61 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
62   // Register the target.
63   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
64   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
65 
66   PassRegistry &PR = *PassRegistry::getPassRegistry();
67   initializeX86LowerAMXIntrinsicsLegacyPassPass(PR);
68   initializeX86LowerAMXTypeLegacyPassPass(PR);
69   initializeX86PreAMXConfigPassPass(PR);
70   initializeX86PreTileConfigPass(PR);
71   initializeGlobalISel(PR);
72   initializeWinEHStatePassPass(PR);
73   initializeFixupBWInstPassPass(PR);
74   initializeEvexToVexInstPassPass(PR);
75   initializeFixupLEAPassPass(PR);
76   initializeFPSPass(PR);
77   initializeX86FixupSetCCPassPass(PR);
78   initializeX86CallFrameOptimizationPass(PR);
79   initializeX86CmovConverterPassPass(PR);
80   initializeX86TileConfigPass(PR);
81   initializeX86FastTileConfigPass(PR);
82   initializeX86LowerTileCopyPass(PR);
83   initializeX86ExpandPseudoPass(PR);
84   initializeX86ExecutionDomainFixPass(PR);
85   initializeX86DomainReassignmentPass(PR);
86   initializeX86AvoidSFBPassPass(PR);
87   initializeX86AvoidTrailingCallPassPass(PR);
88   initializeX86SpeculativeLoadHardeningPassPass(PR);
89   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
90   initializeX86FlagsCopyLoweringPassPass(PR);
91   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
92   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
93   initializeX86OptimizeLEAPassPass(PR);
94   initializeX86PartialReductionPass(PR);
95   initializePseudoProbeInserterPass(PR);
96 }
97 
98 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
99   if (TT.isOSBinFormatMachO()) {
100     if (TT.getArch() == Triple::x86_64)
101       return std::make_unique<X86_64MachoTargetObjectFile>();
102     return std::make_unique<TargetLoweringObjectFileMachO>();
103   }
104 
105   if (TT.isOSBinFormatCOFF())
106     return std::make_unique<TargetLoweringObjectFileCOFF>();
107   return std::make_unique<X86ELFTargetObjectFile>();
108 }
109 
110 static std::string computeDataLayout(const Triple &TT) {
111   // X86 is little endian
112   std::string Ret = "e";
113 
114   Ret += DataLayout::getManglingComponent(TT);
115   // X86 and x32 have 32 bit pointers.
116   if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
117     Ret += "-p:32:32";
118 
119   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
120   Ret += "-p270:32:32-p271:32:32-p272:64:64";
121 
122   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
123   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
124     Ret += "-i64:64";
125   else if (TT.isOSIAMCU())
126     Ret += "-i64:32-f64:32";
127   else
128     Ret += "-f64:32:64";
129 
130   // Some ABIs align long double to 128 bits, others to 32.
131   if (TT.isOSNaCl() || TT.isOSIAMCU())
132     ; // No f80
133   else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
134     Ret += "-f80:128";
135   else
136     Ret += "-f80:32";
137 
138   if (TT.isOSIAMCU())
139     Ret += "-f128:32";
140 
141   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
142   if (TT.isArch64Bit())
143     Ret += "-n8:16:32:64";
144   else
145     Ret += "-n8:16:32";
146 
147   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
148   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
149     Ret += "-a:0:32-S32";
150   else
151     Ret += "-S128";
152 
153   return Ret;
154 }
155 
156 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
157                                            bool JIT,
158                                            Optional<Reloc::Model> RM) {
159   bool is64Bit = TT.getArch() == Triple::x86_64;
160   if (!RM.hasValue()) {
161     // JIT codegen should use static relocations by default, since it's
162     // typically executed in process and not relocatable.
163     if (JIT)
164       return Reloc::Static;
165 
166     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
167     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
168     // use static relocation model by default.
169     if (TT.isOSDarwin()) {
170       if (is64Bit)
171         return Reloc::PIC_;
172       return Reloc::DynamicNoPIC;
173     }
174     if (TT.isOSWindows() && is64Bit)
175       return Reloc::PIC_;
176     return Reloc::Static;
177   }
178 
179   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
180   // is defined as a model for code which may be used in static or dynamic
181   // executables but not necessarily a shared library. On X86-32 we just
182   // compile in -static mode, in x86-64 we use PIC.
183   if (*RM == Reloc::DynamicNoPIC) {
184     if (is64Bit)
185       return Reloc::PIC_;
186     if (!TT.isOSDarwin())
187       return Reloc::Static;
188   }
189 
190   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
191   // the Mach-O file format doesn't support it.
192   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
193     return Reloc::PIC_;
194 
195   return *RM;
196 }
197 
198 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
199                                                  bool JIT, bool Is64Bit) {
200   if (CM) {
201     if (*CM == CodeModel::Tiny)
202       report_fatal_error("Target does not support the tiny CodeModel", false);
203     return *CM;
204   }
205   if (JIT)
206     return Is64Bit ? CodeModel::Large : CodeModel::Small;
207   return CodeModel::Small;
208 }
209 
210 /// Create an X86 target.
211 ///
212 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
213                                    StringRef CPU, StringRef FS,
214                                    const TargetOptions &Options,
215                                    Optional<Reloc::Model> RM,
216                                    Optional<CodeModel::Model> CM,
217                                    CodeGenOpt::Level OL, bool JIT)
218     : LLVMTargetMachine(
219           T, computeDataLayout(TT), TT, CPU, FS, Options,
220           getEffectiveRelocModel(TT, JIT, RM),
221           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
222           OL),
223       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
224   // On PS4, the "return address" of a 'noreturn' call must still be within
225   // the calling function, and TrapUnreachable is an easy way to get that.
226   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
227     this->Options.TrapUnreachable = true;
228     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
229   }
230 
231   setMachineOutliner(true);
232 
233   // x86 supports the debug entry values.
234   setSupportsDebugEntryValues(true);
235 
236   initAsmInfo();
237 }
238 
239 X86TargetMachine::~X86TargetMachine() = default;
240 
241 const X86Subtarget *
242 X86TargetMachine::getSubtargetImpl(const Function &F) const {
243   Attribute CPUAttr = F.getFnAttribute("target-cpu");
244   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
245   Attribute FSAttr = F.getFnAttribute("target-features");
246 
247   StringRef CPU =
248       CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
249   StringRef TuneCPU =
250       TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
251   StringRef FS =
252       FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
253 
254   SmallString<512> Key;
255   // The additions here are ordered so that the definitely short strings are
256   // added first so we won't exceed the small size. We append the
257   // much longer FS string at the end so that we only heap allocate at most
258   // one time.
259 
260   // Extract prefer-vector-width attribute.
261   unsigned PreferVectorWidthOverride = 0;
262   Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
263   if (PreferVecWidthAttr.isValid()) {
264     StringRef Val = PreferVecWidthAttr.getValueAsString();
265     unsigned Width;
266     if (!Val.getAsInteger(0, Width)) {
267       Key += 'p';
268       Key += Val;
269       PreferVectorWidthOverride = Width;
270     }
271   }
272 
273   // Extract min-legal-vector-width attribute.
274   unsigned RequiredVectorWidth = UINT32_MAX;
275   Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
276   if (MinLegalVecWidthAttr.isValid()) {
277     StringRef Val = MinLegalVecWidthAttr.getValueAsString();
278     unsigned Width;
279     if (!Val.getAsInteger(0, Width)) {
280       Key += 'm';
281       Key += Val;
282       RequiredVectorWidth = Width;
283     }
284   }
285 
286   // Add CPU to the Key.
287   Key += CPU;
288 
289   // Add tune CPU to the Key.
290   Key += TuneCPU;
291 
292   // Keep track of the start of the feature portion of the string.
293   unsigned FSStart = Key.size();
294 
295   // FIXME: This is related to the code below to reset the target options,
296   // we need to know whether or not the soft float flag is set on the
297   // function before we can generate a subtarget. We also need to use
298   // it as a key for the subtarget since that can be the only difference
299   // between two functions.
300   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
301   // If the soft float attribute is set on the function turn on the soft float
302   // subtarget feature.
303   if (SoftFloat)
304     Key += FS.empty() ? "+soft-float" : "+soft-float,";
305 
306   Key += FS;
307 
308   // We may have added +soft-float to the features so move the StringRef to
309   // point to the full string in the Key.
310   FS = Key.substr(FSStart);
311 
312   auto &I = SubtargetMap[Key];
313   if (!I) {
314     // This needs to be done before we create a new subtarget since any
315     // creation will depend on the TM and the code generation flags on the
316     // function that reside in TargetOptions.
317     resetTargetOptions(F);
318     I = std::make_unique<X86Subtarget>(
319         TargetTriple, CPU, TuneCPU, FS, *this,
320         MaybeAlign(F.getParent()->getOverrideStackAlignment()),
321         PreferVectorWidthOverride, RequiredVectorWidth);
322   }
323   return I.get();
324 }
325 
326 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
327                                            unsigned DestAS) const {
328   assert(SrcAS != DestAS && "Expected different address spaces!");
329   if (getPointerSize(SrcAS) != getPointerSize(DestAS))
330     return false;
331   return SrcAS < 256 && DestAS < 256;
332 }
333 
334 //===----------------------------------------------------------------------===//
335 // X86 TTI query.
336 //===----------------------------------------------------------------------===//
337 
338 TargetTransformInfo
339 X86TargetMachine::getTargetTransformInfo(const Function &F) const {
340   return TargetTransformInfo(X86TTIImpl(this, F));
341 }
342 
343 //===----------------------------------------------------------------------===//
344 // Pass Pipeline Configuration
345 //===----------------------------------------------------------------------===//
346 
347 namespace {
348 
349 /// X86 Code Generator Pass Configuration Options.
350 class X86PassConfig : public TargetPassConfig {
351 public:
352   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
353     : TargetPassConfig(TM, PM) {}
354 
355   X86TargetMachine &getX86TargetMachine() const {
356     return getTM<X86TargetMachine>();
357   }
358 
359   ScheduleDAGInstrs *
360   createMachineScheduler(MachineSchedContext *C) const override {
361     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
362     DAG->addMutation(createX86MacroFusionDAGMutation());
363     return DAG;
364   }
365 
366   ScheduleDAGInstrs *
367   createPostMachineScheduler(MachineSchedContext *C) const override {
368     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
369     DAG->addMutation(createX86MacroFusionDAGMutation());
370     return DAG;
371   }
372 
373   void addIRPasses() override;
374   bool addInstSelector() override;
375   bool addIRTranslator() override;
376   bool addLegalizeMachineIR() override;
377   bool addRegBankSelect() override;
378   bool addGlobalInstructionSelect() override;
379   bool addILPOpts() override;
380   bool addPreISel() override;
381   void addMachineSSAOptimization() override;
382   void addPreRegAlloc() override;
383   bool addPostFastRegAllocRewrite() override;
384   void addPostRegAlloc() override;
385   void addPreEmitPass() override;
386   void addPreEmitPass2() override;
387   void addPreSched2() override;
388   bool addPreRewrite() override;
389 
390   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
391 };
392 
393 class X86ExecutionDomainFix : public ExecutionDomainFix {
394 public:
395   static char ID;
396   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
397   StringRef getPassName() const override {
398     return "X86 Execution Dependency Fix";
399   }
400 };
401 char X86ExecutionDomainFix::ID;
402 
403 } // end anonymous namespace
404 
405 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
406   "X86 Execution Domain Fix", false, false)
407 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
408 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
409   "X86 Execution Domain Fix", false, false)
410 
411 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
412   return new X86PassConfig(*this, PM);
413 }
414 
415 void X86PassConfig::addIRPasses() {
416   addPass(createAtomicExpandPass());
417 
418   // We add both pass anyway and when these two passes run, we skip the pass
419   // based on the option level and option attribute.
420   addPass(createX86LowerAMXIntrinsicsPass());
421   addPass(createX86LowerAMXTypePass());
422 
423   if (TM->getOptLevel() == CodeGenOpt::None)
424     addPass(createX86PreAMXConfigPass());
425 
426   TargetPassConfig::addIRPasses();
427 
428   if (TM->getOptLevel() != CodeGenOpt::None) {
429     addPass(createInterleavedAccessPass());
430     addPass(createX86PartialReductionPass());
431   }
432 
433   // Add passes that handle indirect branch removal and insertion of a retpoline
434   // thunk. These will be a no-op unless a function subtarget has the retpoline
435   // feature enabled.
436   addPass(createIndirectBrExpandPass());
437 
438   // Add Control Flow Guard checks.
439   const Triple &TT = TM->getTargetTriple();
440   if (TT.isOSWindows()) {
441     if (TT.getArch() == Triple::x86_64) {
442       addPass(createCFGuardDispatchPass());
443     } else {
444       addPass(createCFGuardCheckPass());
445     }
446   }
447 
448   if (TM->Options.JMCInstrument)
449     addPass(createJMCInstrumenterPass());
450 }
451 
452 bool X86PassConfig::addInstSelector() {
453   // Install an instruction selector.
454   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
455 
456   // For ELF, cleanup any local-dynamic TLS accesses.
457   if (TM->getTargetTriple().isOSBinFormatELF() &&
458       getOptLevel() != CodeGenOpt::None)
459     addPass(createCleanupLocalDynamicTLSPass());
460 
461   addPass(createX86GlobalBaseRegPass());
462   return false;
463 }
464 
465 bool X86PassConfig::addIRTranslator() {
466   addPass(new IRTranslator(getOptLevel()));
467   return false;
468 }
469 
470 bool X86PassConfig::addLegalizeMachineIR() {
471   addPass(new Legalizer());
472   return false;
473 }
474 
475 bool X86PassConfig::addRegBankSelect() {
476   addPass(new RegBankSelect());
477   return false;
478 }
479 
480 bool X86PassConfig::addGlobalInstructionSelect() {
481   addPass(new InstructionSelect(getOptLevel()));
482   return false;
483 }
484 
485 bool X86PassConfig::addILPOpts() {
486   addPass(&EarlyIfConverterID);
487   if (EnableMachineCombinerPass)
488     addPass(&MachineCombinerID);
489   addPass(createX86CmovConverterPass());
490   return true;
491 }
492 
493 bool X86PassConfig::addPreISel() {
494   // Only add this pass for 32-bit x86 Windows.
495   const Triple &TT = TM->getTargetTriple();
496   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
497     addPass(createX86WinEHStatePass());
498   return true;
499 }
500 
501 void X86PassConfig::addPreRegAlloc() {
502   if (getOptLevel() != CodeGenOpt::None) {
503     addPass(&LiveRangeShrinkID);
504     addPass(createX86FixupSetCC());
505     addPass(createX86OptimizeLEAs());
506     addPass(createX86CallFrameOptimization());
507     addPass(createX86AvoidStoreForwardingBlocks());
508   }
509 
510   addPass(createX86SpeculativeLoadHardeningPass());
511   addPass(createX86FlagsCopyLoweringPass());
512   addPass(createX86DynAllocaExpander());
513 
514   if (getOptLevel() != CodeGenOpt::None) {
515     addPass(createX86PreTileConfigPass());
516   }
517 }
518 
519 void X86PassConfig::addMachineSSAOptimization() {
520   addPass(createX86DomainReassignmentPass());
521   TargetPassConfig::addMachineSSAOptimization();
522 }
523 
524 void X86PassConfig::addPostRegAlloc() {
525   addPass(createX86LowerTileCopyPass());
526   addPass(createX86FloatingPointStackifierPass());
527   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
528   // to using the Speculative Execution Side Effect Suppression pass for
529   // mitigation. This is to prevent slow downs due to
530   // analyses needed by the LVIHardening pass when compiling at -O0.
531   if (getOptLevel() != CodeGenOpt::None)
532     addPass(createX86LoadValueInjectionLoadHardeningPass());
533 }
534 
535 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
536 
537 void X86PassConfig::addPreEmitPass() {
538   if (getOptLevel() != CodeGenOpt::None) {
539     addPass(new X86ExecutionDomainFix());
540     addPass(createBreakFalseDeps());
541   }
542 
543   addPass(createX86IndirectBranchTrackingPass());
544 
545   addPass(createX86IssueVZeroUpperPass());
546 
547   if (getOptLevel() != CodeGenOpt::None) {
548     addPass(createX86FixupBWInsts());
549     addPass(createX86PadShortFunctions());
550     addPass(createX86FixupLEAs());
551   }
552   addPass(createX86EvexToVexInsts());
553   addPass(createX86DiscriminateMemOpsPass());
554   addPass(createX86InsertPrefetchPass());
555   addPass(createX86InsertX87waitPass());
556 }
557 
558 void X86PassConfig::addPreEmitPass2() {
559   const Triple &TT = TM->getTargetTriple();
560   const MCAsmInfo *MAI = TM->getMCAsmInfo();
561 
562   // The X86 Speculative Execution Pass must run after all control
563   // flow graph modifying passes. As a result it was listed to run right before
564   // the X86 Retpoline Thunks pass. The reason it must run after control flow
565   // graph modifications is that the model of LFENCE in LLVM has to be updated
566   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
567   // placement of this pass was hand checked to ensure that the subsequent
568   // passes don't move the code around the LFENCEs in a way that will hurt the
569   // correctness of this pass. This placement has been shown to work based on
570   // hand inspection of the codegen output.
571   addPass(createX86SpeculativeExecutionSideEffectSuppression());
572   addPass(createX86IndirectThunksPass());
573 
574   // Insert extra int3 instructions after trailing call instructions to avoid
575   // issues in the unwinder.
576   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
577     addPass(createX86AvoidTrailingCallPass());
578 
579   // Verify basic block incoming and outgoing cfa offset and register values and
580   // correct CFA calculation rule where needed by inserting appropriate CFI
581   // instructions.
582   if (!TT.isOSDarwin() &&
583       (!TT.isOSWindows() ||
584        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
585     addPass(createCFIInstrInserter());
586 
587   if (TT.isOSWindows()) {
588     // Identify valid longjmp targets for Windows Control Flow Guard.
589     addPass(createCFGuardLongjmpPass());
590     // Identify valid eh continuation targets for Windows EHCont Guard.
591     addPass(createEHContGuardCatchretPass());
592   }
593   addPass(createX86LoadValueInjectionRetHardeningPass());
594 
595   // Insert pseudo probe annotation for callsite profiling
596   addPass(createPseudoProbeInserter());
597 
598   // On Darwin platforms, BLR_RVMARKER pseudo instructions are lowered to
599   // bundles.
600   if (TT.isOSDarwin())
601     addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
602       // Only run bundle expansion if there are relevant ObjC runtime functions
603       // present in the module.
604       const Function &F = MF.getFunction();
605       const Module *M = F.getParent();
606       return M->getFunction("objc_retainAutoreleasedReturnValue") ||
607              M->getFunction("objc_unsafeClaimAutoreleasedReturnValue");
608     }));
609 }
610 
611 bool X86PassConfig::addPostFastRegAllocRewrite() {
612   addPass(createX86FastTileConfigPass());
613   return true;
614 }
615 
616 bool X86PassConfig::addPreRewrite() {
617   addPass(createX86TileConfigPass());
618   return true;
619 }
620 
621 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
622   return getStandardCSEConfigForOpt(TM->getOptLevel());
623 }
624