1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 using namespace llvm;
26 
27 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
28                                cl::desc("Enable the machine combiner pass"),
29                                cl::init(true), cl::Hidden);
30 
31 namespace llvm {
32 void initializeWinEHStatePassPass(PassRegistry &);
33 }
34 
35 extern "C" void LLVMInitializeX86Target() {
36   // Register the target.
37   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
38   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
39 
40   PassRegistry &PR = *PassRegistry::getPassRegistry();
41   initializeWinEHStatePassPass(PR);
42 }
43 
44 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
45   if (TT.isOSBinFormatMachO()) {
46     if (TT.getArch() == Triple::x86_64)
47       return make_unique<X86_64MachoTargetObjectFile>();
48     return make_unique<TargetLoweringObjectFileMachO>();
49   }
50 
51   if (TT.isOSLinux() || TT.isOSNaCl())
52     return make_unique<X86LinuxNaClTargetObjectFile>();
53   if (TT.isOSBinFormatELF())
54     return make_unique<X86ELFTargetObjectFile>();
55   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
56     return make_unique<X86WindowsTargetObjectFile>();
57   if (TT.isOSBinFormatCOFF())
58     return make_unique<TargetLoweringObjectFileCOFF>();
59   llvm_unreachable("unknown subtarget type");
60 }
61 
62 static std::string computeDataLayout(const Triple &TT) {
63   // X86 is little endian
64   std::string Ret = "e";
65 
66   Ret += DataLayout::getManglingComponent(TT);
67   // X86 and x32 have 32 bit pointers.
68   if ((TT.isArch64Bit() &&
69        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
70       !TT.isArch64Bit())
71     Ret += "-p:32:32";
72 
73   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
74   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
75     Ret += "-i64:64";
76   else
77     Ret += "-f64:32:64";
78 
79   // Some ABIs align long double to 128 bits, others to 32.
80   if (TT.isOSNaCl())
81     ; // No f80
82   else if (TT.isArch64Bit() || TT.isOSDarwin())
83     Ret += "-f80:128";
84   else
85     Ret += "-f80:32";
86 
87   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
88   if (TT.isArch64Bit())
89     Ret += "-n8:16:32:64";
90   else
91     Ret += "-n8:16:32";
92 
93   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
94   if (!TT.isArch64Bit() && TT.isOSWindows())
95     Ret += "-a:0:32-S32";
96   else
97     Ret += "-S128";
98 
99   return Ret;
100 }
101 
102 /// X86TargetMachine ctor - Create an X86 target.
103 ///
104 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
105                                    StringRef CPU, StringRef FS,
106                                    const TargetOptions &Options,
107                                    Reloc::Model RM, CodeModel::Model CM,
108                                    CodeGenOpt::Level OL)
109     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
110                         OL),
111       TLOF(createTLOF(getTargetTriple())),
112       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
113   // By default (and when -ffast-math is on), enable estimate codegen for
114   // everything except scalar division. By default, use 1 refinement step for
115   // all operations. Defaults may be overridden by using command-line options.
116   // Scalar division estimates are disabled because they break too much
117   // real-world code. These defaults match GCC behavior.
118   this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
119   this->Options.Reciprocals.setDefaults("divf", false, 1);
120   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
121   this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
122 
123   initAsmInfo();
124 }
125 
126 X86TargetMachine::~X86TargetMachine() {}
127 
128 const X86Subtarget *
129 X86TargetMachine::getSubtargetImpl(const Function &F) const {
130   Attribute CPUAttr = F.getFnAttribute("target-cpu");
131   Attribute FSAttr = F.getFnAttribute("target-features");
132 
133   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
134                         ? CPUAttr.getValueAsString().str()
135                         : TargetCPU;
136   std::string FS = !FSAttr.hasAttribute(Attribute::None)
137                        ? FSAttr.getValueAsString().str()
138                        : TargetFS;
139 
140   // FIXME: This is related to the code below to reset the target options,
141   // we need to know whether or not the soft float flag is set on the
142   // function before we can generate a subtarget. We also need to use
143   // it as a key for the subtarget since that can be the only difference
144   // between two functions.
145   bool SoftFloat =
146       F.hasFnAttribute("use-soft-float") &&
147       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
148   // If the soft float attribute is set on the function turn on the soft float
149   // subtarget feature.
150   if (SoftFloat)
151     FS += FS.empty() ? "+soft-float" : ",+soft-float";
152 
153   auto &I = SubtargetMap[CPU + FS];
154   if (!I) {
155     // This needs to be done before we create a new subtarget since any
156     // creation will depend on the TM and the code generation flags on the
157     // function that reside in TargetOptions.
158     resetTargetOptions(F);
159     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
160                                         Options.StackAlignmentOverride);
161   }
162   return I.get();
163 }
164 
165 //===----------------------------------------------------------------------===//
166 // Command line options for x86
167 //===----------------------------------------------------------------------===//
168 static cl::opt<bool>
169 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
170   cl::desc("Minimize AVX to SSE transition penalty"),
171   cl::init(true));
172 
173 //===----------------------------------------------------------------------===//
174 // X86 TTI query.
175 //===----------------------------------------------------------------------===//
176 
177 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
178   return TargetIRAnalysis([this](const Function &F) {
179     return TargetTransformInfo(X86TTIImpl(this, F));
180   });
181 }
182 
183 
184 //===----------------------------------------------------------------------===//
185 // Pass Pipeline Configuration
186 //===----------------------------------------------------------------------===//
187 
188 namespace {
189 /// X86 Code Generator Pass Configuration Options.
190 class X86PassConfig : public TargetPassConfig {
191 public:
192   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
193     : TargetPassConfig(TM, PM) {}
194 
195   X86TargetMachine &getX86TargetMachine() const {
196     return getTM<X86TargetMachine>();
197   }
198 
199   void addIRPasses() override;
200   bool addInstSelector() override;
201   bool addILPOpts() override;
202   bool addPreISel() override;
203   void addPreRegAlloc() override;
204   void addPostRegAlloc() override;
205   void addPreEmitPass() override;
206   void addPreSched2() override;
207 };
208 } // namespace
209 
210 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
211   return new X86PassConfig(this, PM);
212 }
213 
214 void X86PassConfig::addIRPasses() {
215   addPass(createAtomicExpandPass(&getX86TargetMachine()));
216 
217   TargetPassConfig::addIRPasses();
218 }
219 
220 bool X86PassConfig::addInstSelector() {
221   // Install an instruction selector.
222   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
223 
224   // For ELF, cleanup any local-dynamic TLS accesses.
225   if (TM->getTargetTriple().isOSBinFormatELF() &&
226       getOptLevel() != CodeGenOpt::None)
227     addPass(createCleanupLocalDynamicTLSPass());
228 
229   addPass(createX86GlobalBaseRegPass());
230 
231   return false;
232 }
233 
234 bool X86PassConfig::addILPOpts() {
235   addPass(&EarlyIfConverterID);
236   if (EnableMachineCombinerPass)
237     addPass(&MachineCombinerID);
238   return true;
239 }
240 
241 bool X86PassConfig::addPreISel() {
242   // Only add this pass for 32-bit x86 Windows.
243   const Triple &TT = TM->getTargetTriple();
244   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
245     addPass(createX86WinEHStatePass());
246   return true;
247 }
248 
249 void X86PassConfig::addPreRegAlloc() {
250   addPass(createX86CallFrameOptimization());
251 }
252 
253 void X86PassConfig::addPostRegAlloc() {
254   addPass(createX86FloatingPointStackifierPass());
255 }
256 
257 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
258 
259 void X86PassConfig::addPreEmitPass() {
260   if (getOptLevel() != CodeGenOpt::None)
261     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
262 
263   if (UseVZeroUpper)
264     addPass(createX86IssueVZeroUpperPass());
265 
266   if (getOptLevel() != CodeGenOpt::None) {
267     addPass(createX86PadShortFunctions());
268     addPass(createX86FixupLEAs());
269   }
270 }
271