1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54                                cl::desc("Enable the machine combiner pass"),
55                                cl::init(true), cl::Hidden);
56 
57 namespace llvm {
58 
59 void initializeWinEHStatePassPass(PassRegistry &);
60 void initializeFixupLEAPassPass(PassRegistry &);
61 void initializeShadowCallStackPass(PassRegistry &);
62 void initializeX86CallFrameOptimizationPass(PassRegistry &);
63 void initializeX86CmovConverterPassPass(PassRegistry &);
64 void initializeX86ExecutionDomainFixPass(PassRegistry &);
65 void initializeX86DomainReassignmentPass(PassRegistry &);
66 void initializeX86AvoidSFBPassPass(PassRegistry &);
67 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
68 
69 } // end namespace llvm
70 
71 extern "C" void LLVMInitializeX86Target() {
72   // Register the target.
73   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
74   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
75 
76   PassRegistry &PR = *PassRegistry::getPassRegistry();
77   initializeGlobalISel(PR);
78   initializeWinEHStatePassPass(PR);
79   initializeFixupBWInstPassPass(PR);
80   initializeEvexToVexInstPassPass(PR);
81   initializeFixupLEAPassPass(PR);
82   initializeShadowCallStackPass(PR);
83   initializeX86CallFrameOptimizationPass(PR);
84   initializeX86CmovConverterPassPass(PR);
85   initializeX86ExecutionDomainFixPass(PR);
86   initializeX86DomainReassignmentPass(PR);
87   initializeX86AvoidSFBPassPass(PR);
88   initializeX86FlagsCopyLoweringPassPass(PR);
89 }
90 
91 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
92   if (TT.isOSBinFormatMachO()) {
93     if (TT.getArch() == Triple::x86_64)
94       return llvm::make_unique<X86_64MachoTargetObjectFile>();
95     return llvm::make_unique<TargetLoweringObjectFileMachO>();
96   }
97 
98   if (TT.isOSFreeBSD())
99     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
100   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
101     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
102   if (TT.isOSSolaris())
103     return llvm::make_unique<X86SolarisTargetObjectFile>();
104   if (TT.isOSFuchsia())
105     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
106   if (TT.isOSBinFormatELF())
107     return llvm::make_unique<X86ELFTargetObjectFile>();
108   if (TT.isOSBinFormatCOFF())
109     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
110   llvm_unreachable("unknown subtarget type");
111 }
112 
113 static std::string computeDataLayout(const Triple &TT) {
114   // X86 is little endian
115   std::string Ret = "e";
116 
117   Ret += DataLayout::getManglingComponent(TT);
118   // X86 and x32 have 32 bit pointers.
119   if ((TT.isArch64Bit() &&
120        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
121       !TT.isArch64Bit())
122     Ret += "-p:32:32";
123 
124   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
125   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
126     Ret += "-i64:64";
127   else if (TT.isOSIAMCU())
128     Ret += "-i64:32-f64:32";
129   else
130     Ret += "-f64:32:64";
131 
132   // Some ABIs align long double to 128 bits, others to 32.
133   if (TT.isOSNaCl() || TT.isOSIAMCU())
134     ; // No f80
135   else if (TT.isArch64Bit() || TT.isOSDarwin())
136     Ret += "-f80:128";
137   else
138     Ret += "-f80:32";
139 
140   if (TT.isOSIAMCU())
141     Ret += "-f128:32";
142 
143   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
144   if (TT.isArch64Bit())
145     Ret += "-n8:16:32:64";
146   else
147     Ret += "-n8:16:32";
148 
149   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
150   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
151     Ret += "-a:0:32-S32";
152   else
153     Ret += "-S128";
154 
155   return Ret;
156 }
157 
158 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
159                                            Optional<Reloc::Model> RM) {
160   bool is64Bit = TT.getArch() == Triple::x86_64;
161   if (!RM.hasValue()) {
162     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
163     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
164     // use static relocation model by default.
165     if (TT.isOSDarwin()) {
166       if (is64Bit)
167         return Reloc::PIC_;
168       return Reloc::DynamicNoPIC;
169     }
170     if (TT.isOSWindows() && is64Bit)
171       return Reloc::PIC_;
172     return Reloc::Static;
173   }
174 
175   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
176   // is defined as a model for code which may be used in static or dynamic
177   // executables but not necessarily a shared library. On X86-32 we just
178   // compile in -static mode, in x86-64 we use PIC.
179   if (*RM == Reloc::DynamicNoPIC) {
180     if (is64Bit)
181       return Reloc::PIC_;
182     if (!TT.isOSDarwin())
183       return Reloc::Static;
184   }
185 
186   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
187   // the Mach-O file format doesn't support it.
188   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
189     return Reloc::PIC_;
190 
191   return *RM;
192 }
193 
194 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
195                                               bool JIT, bool Is64Bit) {
196   if (CM)
197     return *CM;
198   if (JIT)
199     return Is64Bit ? CodeModel::Large : CodeModel::Small;
200   return CodeModel::Small;
201 }
202 
203 /// Create an X86 target.
204 ///
205 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
206                                    StringRef CPU, StringRef FS,
207                                    const TargetOptions &Options,
208                                    Optional<Reloc::Model> RM,
209                                    Optional<CodeModel::Model> CM,
210                                    CodeGenOpt::Level OL, bool JIT)
211     : LLVMTargetMachine(
212           T, computeDataLayout(TT), TT, CPU, FS, Options,
213           getEffectiveRelocModel(TT, RM),
214           getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
215       TLOF(createTLOF(getTargetTriple())) {
216   // Windows stack unwinder gets confused when execution flow "falls through"
217   // after a call to 'noreturn' function.
218   // To prevent that, we emit a trap for 'unreachable' IR instructions.
219   // (which on X86, happens to be the 'ud2' instruction)
220   // On PS4, the "return address" of a 'noreturn' call must still be within
221   // the calling function, and TrapUnreachable is an easy way to get that.
222   // The check here for 64-bit windows is a bit icky, but as we're unlikely
223   // to ever want to mix 32 and 64-bit windows code in a single module
224   // this should be fine.
225   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
226       TT.isOSBinFormatMachO())
227     this->Options.TrapUnreachable = true;
228 
229   initAsmInfo();
230 }
231 
232 X86TargetMachine::~X86TargetMachine() = default;
233 
234 const X86Subtarget *
235 X86TargetMachine::getSubtargetImpl(const Function &F) const {
236   Attribute CPUAttr = F.getFnAttribute("target-cpu");
237   Attribute FSAttr = F.getFnAttribute("target-features");
238 
239   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
240                       ? CPUAttr.getValueAsString()
241                       : (StringRef)TargetCPU;
242   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
243                      ? FSAttr.getValueAsString()
244                      : (StringRef)TargetFS;
245 
246   SmallString<512> Key;
247   Key.reserve(CPU.size() + FS.size());
248   Key += CPU;
249   Key += FS;
250 
251   // FIXME: This is related to the code below to reset the target options,
252   // we need to know whether or not the soft float flag is set on the
253   // function before we can generate a subtarget. We also need to use
254   // it as a key for the subtarget since that can be the only difference
255   // between two functions.
256   bool SoftFloat =
257       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
258   // If the soft float attribute is set on the function turn on the soft float
259   // subtarget feature.
260   if (SoftFloat)
261     Key += FS.empty() ? "+soft-float" : ",+soft-float";
262 
263   // Keep track of the key width after all features are added so we can extract
264   // the feature string out later.
265   unsigned CPUFSWidth = Key.size();
266 
267   // Extract prefer-vector-width attribute.
268   unsigned PreferVectorWidthOverride = 0;
269   if (F.hasFnAttribute("prefer-vector-width")) {
270     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
271     unsigned Width;
272     if (!Val.getAsInteger(0, Width)) {
273       Key += ",prefer-vector-width=";
274       Key += Val;
275       PreferVectorWidthOverride = Width;
276     }
277   }
278 
279   // Extract required-vector-width attribute.
280   unsigned RequiredVectorWidth = UINT32_MAX;
281   if (F.hasFnAttribute("required-vector-width")) {
282     StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
283     unsigned Width;
284     if (!Val.getAsInteger(0, Width)) {
285       Key += ",required-vector-width=";
286       Key += Val;
287       RequiredVectorWidth = Width;
288     }
289   }
290 
291   // Extracted here so that we make sure there is backing for the StringRef. If
292   // we assigned earlier, its possible the SmallString reallocated leaving a
293   // dangling StringRef.
294   FS = Key.slice(CPU.size(), CPUFSWidth);
295 
296   auto &I = SubtargetMap[Key];
297   if (!I) {
298     // This needs to be done before we create a new subtarget since any
299     // creation will depend on the TM and the code generation flags on the
300     // function that reside in TargetOptions.
301     resetTargetOptions(F);
302     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
303                                         Options.StackAlignmentOverride,
304                                         PreferVectorWidthOverride,
305                                         RequiredVectorWidth);
306   }
307   return I.get();
308 }
309 
310 //===----------------------------------------------------------------------===//
311 // Command line options for x86
312 //===----------------------------------------------------------------------===//
313 static cl::opt<bool>
314 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
315   cl::desc("Minimize AVX to SSE transition penalty"),
316   cl::init(true));
317 
318 //===----------------------------------------------------------------------===//
319 // X86 TTI query.
320 //===----------------------------------------------------------------------===//
321 
322 TargetTransformInfo
323 X86TargetMachine::getTargetTransformInfo(const Function &F) {
324   return TargetTransformInfo(X86TTIImpl(this, F));
325 }
326 
327 //===----------------------------------------------------------------------===//
328 // Pass Pipeline Configuration
329 //===----------------------------------------------------------------------===//
330 
331 namespace {
332 
333 /// X86 Code Generator Pass Configuration Options.
334 class X86PassConfig : public TargetPassConfig {
335 public:
336   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
337     : TargetPassConfig(TM, PM) {}
338 
339   X86TargetMachine &getX86TargetMachine() const {
340     return getTM<X86TargetMachine>();
341   }
342 
343   ScheduleDAGInstrs *
344   createMachineScheduler(MachineSchedContext *C) const override {
345     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
346     DAG->addMutation(createX86MacroFusionDAGMutation());
347     return DAG;
348   }
349 
350   void addIRPasses() override;
351   bool addInstSelector() override;
352   bool addIRTranslator() override;
353   bool addLegalizeMachineIR() override;
354   bool addRegBankSelect() override;
355   bool addGlobalInstructionSelect() override;
356   bool addILPOpts() override;
357   bool addPreISel() override;
358   void addMachineSSAOptimization() override;
359   void addPreRegAlloc() override;
360   void addPostRegAlloc() override;
361   void addPreEmitPass() override;
362   void addPreEmitPass2() override;
363   void addPreSched2() override;
364 };
365 
366 class X86ExecutionDomainFix : public ExecutionDomainFix {
367 public:
368   static char ID;
369   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
370   StringRef getPassName() const override {
371     return "X86 Execution Dependency Fix";
372   }
373 };
374 char X86ExecutionDomainFix::ID;
375 
376 } // end anonymous namespace
377 
378 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
379   "X86 Execution Domain Fix", false, false)
380 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
381 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
382   "X86 Execution Domain Fix", false, false)
383 
384 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
385   return new X86PassConfig(*this, PM);
386 }
387 
388 void X86PassConfig::addIRPasses() {
389   addPass(createAtomicExpandPass());
390 
391   TargetPassConfig::addIRPasses();
392 
393   if (TM->getOptLevel() != CodeGenOpt::None)
394     addPass(createInterleavedAccessPass());
395 
396   // Add passes that handle indirect branch removal and insertion of a retpoline
397   // thunk. These will be a no-op unless a function subtarget has the retpoline
398   // feature enabled.
399   addPass(createIndirectBrExpandPass());
400 }
401 
402 bool X86PassConfig::addInstSelector() {
403   // Install an instruction selector.
404   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
405 
406   // For ELF, cleanup any local-dynamic TLS accesses.
407   if (TM->getTargetTriple().isOSBinFormatELF() &&
408       getOptLevel() != CodeGenOpt::None)
409     addPass(createCleanupLocalDynamicTLSPass());
410 
411   addPass(createX86GlobalBaseRegPass());
412   return false;
413 }
414 
415 bool X86PassConfig::addIRTranslator() {
416   addPass(new IRTranslator());
417   return false;
418 }
419 
420 bool X86PassConfig::addLegalizeMachineIR() {
421   addPass(new Legalizer());
422   return false;
423 }
424 
425 bool X86PassConfig::addRegBankSelect() {
426   addPass(new RegBankSelect());
427   return false;
428 }
429 
430 bool X86PassConfig::addGlobalInstructionSelect() {
431   addPass(new InstructionSelect());
432   return false;
433 }
434 
435 bool X86PassConfig::addILPOpts() {
436   addPass(&EarlyIfConverterID);
437   if (EnableMachineCombinerPass)
438     addPass(&MachineCombinerID);
439   addPass(createX86CmovConverterPass());
440   return true;
441 }
442 
443 bool X86PassConfig::addPreISel() {
444   // Only add this pass for 32-bit x86 Windows.
445   const Triple &TT = TM->getTargetTriple();
446   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
447     addPass(createX86WinEHStatePass());
448   return true;
449 }
450 
451 void X86PassConfig::addPreRegAlloc() {
452   if (getOptLevel() != CodeGenOpt::None) {
453     addPass(&LiveRangeShrinkID);
454     addPass(createX86FixupSetCC());
455     addPass(createX86OptimizeLEAs());
456     addPass(createX86CallFrameOptimization());
457     addPass(createX86AvoidStoreForwardingBlocks());
458   }
459 
460   addPass(createX86FlagsCopyLoweringPass());
461   addPass(createX86WinAllocaExpander());
462 }
463 void X86PassConfig::addMachineSSAOptimization() {
464   addPass(createX86DomainReassignmentPass());
465   TargetPassConfig::addMachineSSAOptimization();
466 }
467 
468 void X86PassConfig::addPostRegAlloc() {
469   addPass(createX86FloatingPointStackifierPass());
470 }
471 
472 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
473 
474 void X86PassConfig::addPreEmitPass() {
475   if (getOptLevel() != CodeGenOpt::None) {
476     addPass(new X86ExecutionDomainFix());
477     addPass(createBreakFalseDeps());
478   }
479 
480   addPass(createShadowCallStackPass());
481   addPass(createX86IndirectBranchTrackingPass());
482 
483   if (UseVZeroUpper)
484     addPass(createX86IssueVZeroUpperPass());
485 
486   if (getOptLevel() != CodeGenOpt::None) {
487     addPass(createX86FixupBWInsts());
488     addPass(createX86PadShortFunctions());
489     addPass(createX86FixupLEAs());
490     addPass(createX86EvexToVexInsts());
491   }
492 }
493 
494 void X86PassConfig::addPreEmitPass2() {
495   addPass(createX86RetpolineThunksPass());
496   // Verify basic block incoming and outgoing cfa offset and register values and
497   // correct CFA calculation rule where needed by inserting appropriate CFI
498   // instructions.
499   const Triple &TT = TM->getTargetTriple();
500   if (!TT.isOSDarwin() && !TT.isOSWindows())
501     addPass(createCFIInstrInserter());
502 }
503