1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CSEInfo.h"
31 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
32 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
33 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
34 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
35 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
36 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
37 #include "llvm/CodeGen/MachineScheduler.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/TargetPassConfig.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
51 #include "llvm/Transforms/CFGuard.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58                                cl::desc("Enable the machine combiner pass"),
59                                cl::init(true), cl::Hidden);
60 
61 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
62   // Register the target.
63   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
64   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
65 
66   PassRegistry &PR = *PassRegistry::getPassRegistry();
67   initializeX86LowerAMXIntrinsicsLegacyPassPass(PR);
68   initializeX86LowerAMXTypeLegacyPassPass(PR);
69   initializeX86PreAMXConfigPassPass(PR);
70   initializeX86PreTileConfigPass(PR);
71   initializeGlobalISel(PR);
72   initializeWinEHStatePassPass(PR);
73   initializeFixupBWInstPassPass(PR);
74   initializeEvexToVexInstPassPass(PR);
75   initializeFixupLEAPassPass(PR);
76   initializeFPSPass(PR);
77   initializeX86FixupSetCCPassPass(PR);
78   initializeX86CallFrameOptimizationPass(PR);
79   initializeX86CmovConverterPassPass(PR);
80   initializeX86TileConfigPass(PR);
81   initializeX86FastPreTileConfigPass(PR);
82   initializeX86FastTileConfigPass(PR);
83   initializeX86LowerTileCopyPass(PR);
84   initializeX86ExpandPseudoPass(PR);
85   initializeX86ExecutionDomainFixPass(PR);
86   initializeX86DomainReassignmentPass(PR);
87   initializeX86AvoidSFBPassPass(PR);
88   initializeX86AvoidTrailingCallPassPass(PR);
89   initializeX86SpeculativeLoadHardeningPassPass(PR);
90   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
91   initializeX86FlagsCopyLoweringPassPass(PR);
92   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
93   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
94   initializeX86OptimizeLEAPassPass(PR);
95   initializeX86PartialReductionPass(PR);
96   initializePseudoProbeInserterPass(PR);
97 }
98 
99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100   if (TT.isOSBinFormatMachO()) {
101     if (TT.getArch() == Triple::x86_64)
102       return std::make_unique<X86_64MachoTargetObjectFile>();
103     return std::make_unique<TargetLoweringObjectFileMachO>();
104   }
105 
106   if (TT.isOSBinFormatCOFF())
107     return std::make_unique<TargetLoweringObjectFileCOFF>();
108   return std::make_unique<X86ELFTargetObjectFile>();
109 }
110 
111 static std::string computeDataLayout(const Triple &TT) {
112   // X86 is little endian
113   std::string Ret = "e";
114 
115   Ret += DataLayout::getManglingComponent(TT);
116   // X86 and x32 have 32 bit pointers.
117   if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
118     Ret += "-p:32:32";
119 
120   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
121   Ret += "-p270:32:32-p271:32:32-p272:64:64";
122 
123   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
124   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
125     Ret += "-i64:64";
126   else if (TT.isOSIAMCU())
127     Ret += "-i64:32-f64:32";
128   else
129     Ret += "-f64:32:64";
130 
131   // Some ABIs align long double to 128 bits, others to 32.
132   if (TT.isOSNaCl() || TT.isOSIAMCU())
133     ; // No f80
134   else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
135     Ret += "-f80:128";
136   else
137     Ret += "-f80:32";
138 
139   if (TT.isOSIAMCU())
140     Ret += "-f128:32";
141 
142   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
143   if (TT.isArch64Bit())
144     Ret += "-n8:16:32:64";
145   else
146     Ret += "-n8:16:32";
147 
148   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
149   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
150     Ret += "-a:0:32-S32";
151   else
152     Ret += "-S128";
153 
154   return Ret;
155 }
156 
157 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
158                                            bool JIT,
159                                            Optional<Reloc::Model> RM) {
160   bool is64Bit = TT.getArch() == Triple::x86_64;
161   if (!RM.hasValue()) {
162     // JIT codegen should use static relocations by default, since it's
163     // typically executed in process and not relocatable.
164     if (JIT)
165       return Reloc::Static;
166 
167     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
168     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
169     // use static relocation model by default.
170     if (TT.isOSDarwin()) {
171       if (is64Bit)
172         return Reloc::PIC_;
173       return Reloc::DynamicNoPIC;
174     }
175     if (TT.isOSWindows() && is64Bit)
176       return Reloc::PIC_;
177     return Reloc::Static;
178   }
179 
180   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
181   // is defined as a model for code which may be used in static or dynamic
182   // executables but not necessarily a shared library. On X86-32 we just
183   // compile in -static mode, in x86-64 we use PIC.
184   if (*RM == Reloc::DynamicNoPIC) {
185     if (is64Bit)
186       return Reloc::PIC_;
187     if (!TT.isOSDarwin())
188       return Reloc::Static;
189   }
190 
191   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
192   // the Mach-O file format doesn't support it.
193   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
194     return Reloc::PIC_;
195 
196   return *RM;
197 }
198 
199 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
200                                                  bool JIT, bool Is64Bit) {
201   if (CM) {
202     if (*CM == CodeModel::Tiny)
203       report_fatal_error("Target does not support the tiny CodeModel", false);
204     return *CM;
205   }
206   if (JIT)
207     return Is64Bit ? CodeModel::Large : CodeModel::Small;
208   return CodeModel::Small;
209 }
210 
211 /// Create an X86 target.
212 ///
213 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
214                                    StringRef CPU, StringRef FS,
215                                    const TargetOptions &Options,
216                                    Optional<Reloc::Model> RM,
217                                    Optional<CodeModel::Model> CM,
218                                    CodeGenOpt::Level OL, bool JIT)
219     : LLVMTargetMachine(
220           T, computeDataLayout(TT), TT, CPU, FS, Options,
221           getEffectiveRelocModel(TT, JIT, RM),
222           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
223           OL),
224       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
225   // On PS4, the "return address" of a 'noreturn' call must still be within
226   // the calling function, and TrapUnreachable is an easy way to get that.
227   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
228     this->Options.TrapUnreachable = true;
229     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
230   }
231 
232   setMachineOutliner(true);
233 
234   // x86 supports the debug entry values.
235   setSupportsDebugEntryValues(true);
236 
237   initAsmInfo();
238 }
239 
240 X86TargetMachine::~X86TargetMachine() = default;
241 
242 const X86Subtarget *
243 X86TargetMachine::getSubtargetImpl(const Function &F) const {
244   Attribute CPUAttr = F.getFnAttribute("target-cpu");
245   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
246   Attribute FSAttr = F.getFnAttribute("target-features");
247 
248   StringRef CPU =
249       CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
250   StringRef TuneCPU =
251       TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
252   StringRef FS =
253       FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
254 
255   SmallString<512> Key;
256   // The additions here are ordered so that the definitely short strings are
257   // added first so we won't exceed the small size. We append the
258   // much longer FS string at the end so that we only heap allocate at most
259   // one time.
260 
261   // Extract prefer-vector-width attribute.
262   unsigned PreferVectorWidthOverride = 0;
263   Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
264   if (PreferVecWidthAttr.isValid()) {
265     StringRef Val = PreferVecWidthAttr.getValueAsString();
266     unsigned Width;
267     if (!Val.getAsInteger(0, Width)) {
268       Key += 'p';
269       Key += Val;
270       PreferVectorWidthOverride = Width;
271     }
272   }
273 
274   // Extract min-legal-vector-width attribute.
275   unsigned RequiredVectorWidth = UINT32_MAX;
276   Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
277   if (MinLegalVecWidthAttr.isValid()) {
278     StringRef Val = MinLegalVecWidthAttr.getValueAsString();
279     unsigned Width;
280     if (!Val.getAsInteger(0, Width)) {
281       Key += 'm';
282       Key += Val;
283       RequiredVectorWidth = Width;
284     }
285   }
286 
287   // Add CPU to the Key.
288   Key += CPU;
289 
290   // Add tune CPU to the Key.
291   Key += TuneCPU;
292 
293   // Keep track of the start of the feature portion of the string.
294   unsigned FSStart = Key.size();
295 
296   // FIXME: This is related to the code below to reset the target options,
297   // we need to know whether or not the soft float flag is set on the
298   // function before we can generate a subtarget. We also need to use
299   // it as a key for the subtarget since that can be the only difference
300   // between two functions.
301   bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
302   // If the soft float attribute is set on the function turn on the soft float
303   // subtarget feature.
304   if (SoftFloat)
305     Key += FS.empty() ? "+soft-float" : "+soft-float,";
306 
307   Key += FS;
308 
309   // We may have added +soft-float to the features so move the StringRef to
310   // point to the full string in the Key.
311   FS = Key.substr(FSStart);
312 
313   auto &I = SubtargetMap[Key];
314   if (!I) {
315     // This needs to be done before we create a new subtarget since any
316     // creation will depend on the TM and the code generation flags on the
317     // function that reside in TargetOptions.
318     resetTargetOptions(F);
319     I = std::make_unique<X86Subtarget>(
320         TargetTriple, CPU, TuneCPU, FS, *this,
321         MaybeAlign(F.getParent()->getOverrideStackAlignment()),
322         PreferVectorWidthOverride, RequiredVectorWidth);
323   }
324   return I.get();
325 }
326 
327 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
328                                            unsigned DestAS) const {
329   assert(SrcAS != DestAS && "Expected different address spaces!");
330   if (getPointerSize(SrcAS) != getPointerSize(DestAS))
331     return false;
332   return SrcAS < 256 && DestAS < 256;
333 }
334 
335 //===----------------------------------------------------------------------===//
336 // X86 TTI query.
337 //===----------------------------------------------------------------------===//
338 
339 TargetTransformInfo
340 X86TargetMachine::getTargetTransformInfo(const Function &F) const {
341   return TargetTransformInfo(X86TTIImpl(this, F));
342 }
343 
344 //===----------------------------------------------------------------------===//
345 // Pass Pipeline Configuration
346 //===----------------------------------------------------------------------===//
347 
348 namespace {
349 
350 /// X86 Code Generator Pass Configuration Options.
351 class X86PassConfig : public TargetPassConfig {
352 public:
353   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
354     : TargetPassConfig(TM, PM) {}
355 
356   X86TargetMachine &getX86TargetMachine() const {
357     return getTM<X86TargetMachine>();
358   }
359 
360   ScheduleDAGInstrs *
361   createMachineScheduler(MachineSchedContext *C) const override {
362     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
363     DAG->addMutation(createX86MacroFusionDAGMutation());
364     return DAG;
365   }
366 
367   ScheduleDAGInstrs *
368   createPostMachineScheduler(MachineSchedContext *C) const override {
369     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
370     DAG->addMutation(createX86MacroFusionDAGMutation());
371     return DAG;
372   }
373 
374   void addIRPasses() override;
375   bool addInstSelector() override;
376   bool addIRTranslator() override;
377   bool addLegalizeMachineIR() override;
378   bool addRegBankSelect() override;
379   bool addGlobalInstructionSelect() override;
380   bool addILPOpts() override;
381   bool addPreISel() override;
382   void addMachineSSAOptimization() override;
383   void addPreRegAlloc() override;
384   bool addPostFastRegAllocRewrite() override;
385   void addPostRegAlloc() override;
386   void addPreEmitPass() override;
387   void addPreEmitPass2() override;
388   void addPreSched2() override;
389   bool addPreRewrite() override;
390 
391   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
392 };
393 
394 class X86ExecutionDomainFix : public ExecutionDomainFix {
395 public:
396   static char ID;
397   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
398   StringRef getPassName() const override {
399     return "X86 Execution Dependency Fix";
400   }
401 };
402 char X86ExecutionDomainFix::ID;
403 
404 } // end anonymous namespace
405 
406 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
407   "X86 Execution Domain Fix", false, false)
408 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
409 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
410   "X86 Execution Domain Fix", false, false)
411 
412 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
413   return new X86PassConfig(*this, PM);
414 }
415 
416 void X86PassConfig::addIRPasses() {
417   addPass(createAtomicExpandPass());
418 
419   // We add both pass anyway and when these two passes run, we skip the pass
420   // based on the option level and option attribute.
421   addPass(createX86LowerAMXIntrinsicsPass());
422   addPass(createX86LowerAMXTypePass());
423 
424   TargetPassConfig::addIRPasses();
425 
426   if (TM->getOptLevel() != CodeGenOpt::None) {
427     addPass(createInterleavedAccessPass());
428     addPass(createX86PartialReductionPass());
429   }
430 
431   // Add passes that handle indirect branch removal and insertion of a retpoline
432   // thunk. These will be a no-op unless a function subtarget has the retpoline
433   // feature enabled.
434   addPass(createIndirectBrExpandPass());
435 
436   // Add Control Flow Guard checks.
437   const Triple &TT = TM->getTargetTriple();
438   if (TT.isOSWindows()) {
439     if (TT.getArch() == Triple::x86_64) {
440       addPass(createCFGuardDispatchPass());
441     } else {
442       addPass(createCFGuardCheckPass());
443     }
444   }
445 
446   if (TM->Options.JMCInstrument)
447     addPass(createJMCInstrumenterPass());
448 }
449 
450 bool X86PassConfig::addInstSelector() {
451   // Install an instruction selector.
452   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
453 
454   // For ELF, cleanup any local-dynamic TLS accesses.
455   if (TM->getTargetTriple().isOSBinFormatELF() &&
456       getOptLevel() != CodeGenOpt::None)
457     addPass(createCleanupLocalDynamicTLSPass());
458 
459   addPass(createX86GlobalBaseRegPass());
460   return false;
461 }
462 
463 bool X86PassConfig::addIRTranslator() {
464   addPass(new IRTranslator(getOptLevel()));
465   return false;
466 }
467 
468 bool X86PassConfig::addLegalizeMachineIR() {
469   addPass(new Legalizer());
470   return false;
471 }
472 
473 bool X86PassConfig::addRegBankSelect() {
474   addPass(new RegBankSelect());
475   return false;
476 }
477 
478 bool X86PassConfig::addGlobalInstructionSelect() {
479   addPass(new InstructionSelect(getOptLevel()));
480   return false;
481 }
482 
483 bool X86PassConfig::addILPOpts() {
484   addPass(&EarlyIfConverterID);
485   if (EnableMachineCombinerPass)
486     addPass(&MachineCombinerID);
487   addPass(createX86CmovConverterPass());
488   return true;
489 }
490 
491 bool X86PassConfig::addPreISel() {
492   // Only add this pass for 32-bit x86 Windows.
493   const Triple &TT = TM->getTargetTriple();
494   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
495     addPass(createX86WinEHStatePass());
496   return true;
497 }
498 
499 void X86PassConfig::addPreRegAlloc() {
500   if (getOptLevel() != CodeGenOpt::None) {
501     addPass(&LiveRangeShrinkID);
502     addPass(createX86FixupSetCC());
503     addPass(createX86OptimizeLEAs());
504     addPass(createX86CallFrameOptimization());
505     addPass(createX86AvoidStoreForwardingBlocks());
506   }
507 
508   addPass(createX86SpeculativeLoadHardeningPass());
509   addPass(createX86FlagsCopyLoweringPass());
510   addPass(createX86DynAllocaExpander());
511 
512   if (getOptLevel() != CodeGenOpt::None)
513     addPass(createX86PreTileConfigPass());
514   else
515     addPass(createX86FastPreTileConfigPass());
516 }
517 
518 void X86PassConfig::addMachineSSAOptimization() {
519   addPass(createX86DomainReassignmentPass());
520   TargetPassConfig::addMachineSSAOptimization();
521 }
522 
523 void X86PassConfig::addPostRegAlloc() {
524   addPass(createX86LowerTileCopyPass());
525   addPass(createX86FloatingPointStackifierPass());
526   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
527   // to using the Speculative Execution Side Effect Suppression pass for
528   // mitigation. This is to prevent slow downs due to
529   // analyses needed by the LVIHardening pass when compiling at -O0.
530   if (getOptLevel() != CodeGenOpt::None)
531     addPass(createX86LoadValueInjectionLoadHardeningPass());
532 }
533 
534 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
535 
536 void X86PassConfig::addPreEmitPass() {
537   if (getOptLevel() != CodeGenOpt::None) {
538     addPass(new X86ExecutionDomainFix());
539     addPass(createBreakFalseDeps());
540   }
541 
542   addPass(createX86IndirectBranchTrackingPass());
543 
544   addPass(createX86IssueVZeroUpperPass());
545 
546   if (getOptLevel() != CodeGenOpt::None) {
547     addPass(createX86FixupBWInsts());
548     addPass(createX86PadShortFunctions());
549     addPass(createX86FixupLEAs());
550   }
551   addPass(createX86EvexToVexInsts());
552   addPass(createX86DiscriminateMemOpsPass());
553   addPass(createX86InsertPrefetchPass());
554   addPass(createX86InsertX87waitPass());
555 }
556 
557 void X86PassConfig::addPreEmitPass2() {
558   const Triple &TT = TM->getTargetTriple();
559   const MCAsmInfo *MAI = TM->getMCAsmInfo();
560 
561   // The X86 Speculative Execution Pass must run after all control
562   // flow graph modifying passes. As a result it was listed to run right before
563   // the X86 Retpoline Thunks pass. The reason it must run after control flow
564   // graph modifications is that the model of LFENCE in LLVM has to be updated
565   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
566   // placement of this pass was hand checked to ensure that the subsequent
567   // passes don't move the code around the LFENCEs in a way that will hurt the
568   // correctness of this pass. This placement has been shown to work based on
569   // hand inspection of the codegen output.
570   addPass(createX86SpeculativeExecutionSideEffectSuppression());
571   addPass(createX86IndirectThunksPass());
572 
573   // Insert extra int3 instructions after trailing call instructions to avoid
574   // issues in the unwinder.
575   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
576     addPass(createX86AvoidTrailingCallPass());
577 
578   // Verify basic block incoming and outgoing cfa offset and register values and
579   // correct CFA calculation rule where needed by inserting appropriate CFI
580   // instructions.
581   if (!TT.isOSDarwin() &&
582       (!TT.isOSWindows() ||
583        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
584     addPass(createCFIInstrInserter());
585 
586   if (TT.isOSWindows()) {
587     // Identify valid longjmp targets for Windows Control Flow Guard.
588     addPass(createCFGuardLongjmpPass());
589     // Identify valid eh continuation targets for Windows EHCont Guard.
590     addPass(createEHContGuardCatchretPass());
591   }
592   addPass(createX86LoadValueInjectionRetHardeningPass());
593 
594   // Insert pseudo probe annotation for callsite profiling
595   addPass(createPseudoProbeInserter());
596 
597   // On Darwin platforms, BLR_RVMARKER pseudo instructions are lowered to
598   // bundles.
599   if (TT.isOSDarwin())
600     addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
601       // Only run bundle expansion if there are relevant ObjC runtime functions
602       // present in the module.
603       const Function &F = MF.getFunction();
604       const Module *M = F.getParent();
605       return M->getFunction("objc_retainAutoreleasedReturnValue") ||
606              M->getFunction("objc_unsafeClaimAutoreleasedReturnValue");
607     }));
608 }
609 
610 bool X86PassConfig::addPostFastRegAllocRewrite() {
611   addPass(createX86FastTileConfigPass());
612   return true;
613 }
614 
615 bool X86PassConfig::addPreRewrite() {
616   addPass(createX86TileConfigPass());
617   return true;
618 }
619 
620 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
621   return getStandardCSEConfigForOpt(TM->getOptLevel());
622 }
623