1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
60                                cl::desc("Enable the conditional branch "
61                                         "folding pass"),
62                                cl::init(false), cl::Hidden);
63 
64 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
65   // Register the target.
66   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
67   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
68 
69   PassRegistry &PR = *PassRegistry::getPassRegistry();
70   initializeGlobalISel(PR);
71   initializeWinEHStatePassPass(PR);
72   initializeFixupBWInstPassPass(PR);
73   initializeEvexToVexInstPassPass(PR);
74   initializeFixupLEAPassPass(PR);
75   initializeFPSPass(PR);
76   initializeX86FixupSetCCPassPass(PR);
77   initializeX86CallFrameOptimizationPass(PR);
78   initializeX86CmovConverterPassPass(PR);
79   initializeX86ExpandPseudoPass(PR);
80   initializeX86ExecutionDomainFixPass(PR);
81   initializeX86DomainReassignmentPass(PR);
82   initializeX86AvoidSFBPassPass(PR);
83   initializeX86AvoidTrailingCallPassPass(PR);
84   initializeX86SpeculativeLoadHardeningPassPass(PR);
85   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
86   initializeX86FlagsCopyLoweringPassPass(PR);
87   initializeX86CondBrFoldingPassPass(PR);
88   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
89   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
90   initializeX86OptimizeLEAPassPass(PR);
91   initializeX86PartialReductionPass(PR);
92 }
93 
94 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
95   if (TT.isOSBinFormatMachO()) {
96     if (TT.getArch() == Triple::x86_64)
97       return std::make_unique<X86_64MachoTargetObjectFile>();
98     return std::make_unique<TargetLoweringObjectFileMachO>();
99   }
100 
101   if (TT.isOSBinFormatCOFF())
102     return std::make_unique<TargetLoweringObjectFileCOFF>();
103   return std::make_unique<X86ELFTargetObjectFile>();
104 }
105 
106 static std::string computeDataLayout(const Triple &TT) {
107   // X86 is little endian
108   std::string Ret = "e";
109 
110   Ret += DataLayout::getManglingComponent(TT);
111   // X86 and x32 have 32 bit pointers.
112   if ((TT.isArch64Bit() &&
113        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
114       !TT.isArch64Bit())
115     Ret += "-p:32:32";
116 
117   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
118   Ret += "-p270:32:32-p271:32:32-p272:64:64";
119 
120   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
121   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
122     Ret += "-i64:64";
123   else if (TT.isOSIAMCU())
124     Ret += "-i64:32-f64:32";
125   else
126     Ret += "-f64:32:64";
127 
128   // Some ABIs align long double to 128 bits, others to 32.
129   if (TT.isOSNaCl() || TT.isOSIAMCU())
130     ; // No f80
131   else if (TT.isArch64Bit() || TT.isOSDarwin())
132     Ret += "-f80:128";
133   else
134     Ret += "-f80:32";
135 
136   if (TT.isOSIAMCU())
137     Ret += "-f128:32";
138 
139   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
140   if (TT.isArch64Bit())
141     Ret += "-n8:16:32:64";
142   else
143     Ret += "-n8:16:32";
144 
145   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
146   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
147     Ret += "-a:0:32-S32";
148   else
149     Ret += "-S128";
150 
151   return Ret;
152 }
153 
154 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
155                                            bool JIT,
156                                            Optional<Reloc::Model> RM) {
157   bool is64Bit = TT.getArch() == Triple::x86_64;
158   if (!RM.hasValue()) {
159     // JIT codegen should use static relocations by default, since it's
160     // typically executed in process and not relocatable.
161     if (JIT)
162       return Reloc::Static;
163 
164     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
165     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
166     // use static relocation model by default.
167     if (TT.isOSDarwin()) {
168       if (is64Bit)
169         return Reloc::PIC_;
170       return Reloc::DynamicNoPIC;
171     }
172     if (TT.isOSWindows() && is64Bit)
173       return Reloc::PIC_;
174     return Reloc::Static;
175   }
176 
177   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
178   // is defined as a model for code which may be used in static or dynamic
179   // executables but not necessarily a shared library. On X86-32 we just
180   // compile in -static mode, in x86-64 we use PIC.
181   if (*RM == Reloc::DynamicNoPIC) {
182     if (is64Bit)
183       return Reloc::PIC_;
184     if (!TT.isOSDarwin())
185       return Reloc::Static;
186   }
187 
188   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
189   // the Mach-O file format doesn't support it.
190   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
191     return Reloc::PIC_;
192 
193   return *RM;
194 }
195 
196 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
197                                                  bool JIT, bool Is64Bit) {
198   if (CM) {
199     if (*CM == CodeModel::Tiny)
200       report_fatal_error("Target does not support the tiny CodeModel", false);
201     return *CM;
202   }
203   if (JIT)
204     return Is64Bit ? CodeModel::Large : CodeModel::Small;
205   return CodeModel::Small;
206 }
207 
208 /// Create an X86 target.
209 ///
210 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
211                                    StringRef CPU, StringRef FS,
212                                    const TargetOptions &Options,
213                                    Optional<Reloc::Model> RM,
214                                    Optional<CodeModel::Model> CM,
215                                    CodeGenOpt::Level OL, bool JIT)
216     : LLVMTargetMachine(
217           T, computeDataLayout(TT), TT, CPU, FS, Options,
218           getEffectiveRelocModel(TT, JIT, RM),
219           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
220           OL),
221       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
222   // On PS4, the "return address" of a 'noreturn' call must still be within
223   // the calling function, and TrapUnreachable is an easy way to get that.
224   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
225     this->Options.TrapUnreachable = true;
226     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
227   }
228 
229   setMachineOutliner(true);
230 
231   // x86 supports the debug entry values.
232   setSupportsDebugEntryValues(true);
233 
234   initAsmInfo();
235 }
236 
237 X86TargetMachine::~X86TargetMachine() = default;
238 
239 const X86Subtarget *
240 X86TargetMachine::getSubtargetImpl(const Function &F) const {
241   Attribute CPUAttr = F.getFnAttribute("target-cpu");
242   Attribute FSAttr = F.getFnAttribute("target-features");
243 
244   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
245                       ? CPUAttr.getValueAsString()
246                       : (StringRef)TargetCPU;
247   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
248                      ? FSAttr.getValueAsString()
249                      : (StringRef)TargetFS;
250 
251   SmallString<512> Key;
252   // The additions here are ordered so that the definitely short strings are
253   // added first so we won't exceed the small size. We append the
254   // much longer FS string at the end so that we only heap allocate at most
255   // one time.
256 
257   // Extract prefer-vector-width attribute.
258   unsigned PreferVectorWidthOverride = 0;
259   if (F.hasFnAttribute("prefer-vector-width")) {
260     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
261     unsigned Width;
262     if (!Val.getAsInteger(0, Width)) {
263       Key += "prefer-vector-width=";
264       Key += Val;
265       PreferVectorWidthOverride = Width;
266     }
267   }
268 
269   // Extract min-legal-vector-width attribute.
270   unsigned RequiredVectorWidth = UINT32_MAX;
271   if (F.hasFnAttribute("min-legal-vector-width")) {
272     StringRef Val =
273         F.getFnAttribute("min-legal-vector-width").getValueAsString();
274     unsigned Width;
275     if (!Val.getAsInteger(0, Width)) {
276       Key += "min-legal-vector-width=";
277       Key += Val;
278       RequiredVectorWidth = Width;
279     }
280   }
281 
282   // Add CPU to the Key.
283   Key += CPU;
284 
285   // Keep track of the start of the feature portion of the string.
286   unsigned FSStart = Key.size();
287 
288   // FIXME: This is related to the code below to reset the target options,
289   // we need to know whether or not the soft float flag is set on the
290   // function before we can generate a subtarget. We also need to use
291   // it as a key for the subtarget since that can be the only difference
292   // between two functions.
293   bool SoftFloat =
294       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
295   // If the soft float attribute is set on the function turn on the soft float
296   // subtarget feature.
297   if (SoftFloat)
298     Key += FS.empty() ? "+soft-float" : "+soft-float,";
299 
300   Key += FS;
301 
302   // We may have added +soft-float to the features so move the StringRef to
303   // point to the full string in the Key.
304   FS = Key.substr(FSStart);
305 
306   auto &I = SubtargetMap[Key];
307   if (!I) {
308     // This needs to be done before we create a new subtarget since any
309     // creation will depend on the TM and the code generation flags on the
310     // function that reside in TargetOptions.
311     resetTargetOptions(F);
312     I = std::make_unique<X86Subtarget>(
313         TargetTriple, CPU, FS, *this,
314         MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
315         RequiredVectorWidth);
316   }
317   return I.get();
318 }
319 
320 //===----------------------------------------------------------------------===//
321 // X86 TTI query.
322 //===----------------------------------------------------------------------===//
323 
324 TargetTransformInfo
325 X86TargetMachine::getTargetTransformInfo(const Function &F) {
326   return TargetTransformInfo(X86TTIImpl(this, F));
327 }
328 
329 //===----------------------------------------------------------------------===//
330 // Pass Pipeline Configuration
331 //===----------------------------------------------------------------------===//
332 
333 namespace {
334 
335 /// X86 Code Generator Pass Configuration Options.
336 class X86PassConfig : public TargetPassConfig {
337 public:
338   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
339     : TargetPassConfig(TM, PM) {}
340 
341   X86TargetMachine &getX86TargetMachine() const {
342     return getTM<X86TargetMachine>();
343   }
344 
345   ScheduleDAGInstrs *
346   createMachineScheduler(MachineSchedContext *C) const override {
347     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
348     DAG->addMutation(createX86MacroFusionDAGMutation());
349     return DAG;
350   }
351 
352   ScheduleDAGInstrs *
353   createPostMachineScheduler(MachineSchedContext *C) const override {
354     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
355     DAG->addMutation(createX86MacroFusionDAGMutation());
356     return DAG;
357   }
358 
359   void addIRPasses() override;
360   bool addInstSelector() override;
361   bool addIRTranslator() override;
362   bool addLegalizeMachineIR() override;
363   bool addRegBankSelect() override;
364   bool addGlobalInstructionSelect() override;
365   bool addILPOpts() override;
366   bool addPreISel() override;
367   void addMachineSSAOptimization() override;
368   void addPreRegAlloc() override;
369   void addPostRegAlloc() override;
370   void addPreEmitPass() override;
371   void addPreEmitPass2() override;
372   void addPreSched2() override;
373 
374   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
375 };
376 
377 class X86ExecutionDomainFix : public ExecutionDomainFix {
378 public:
379   static char ID;
380   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
381   StringRef getPassName() const override {
382     return "X86 Execution Dependency Fix";
383   }
384 };
385 char X86ExecutionDomainFix::ID;
386 
387 } // end anonymous namespace
388 
389 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
390   "X86 Execution Domain Fix", false, false)
391 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
392 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
393   "X86 Execution Domain Fix", false, false)
394 
395 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
396   return new X86PassConfig(*this, PM);
397 }
398 
399 void X86PassConfig::addIRPasses() {
400   addPass(createAtomicExpandPass());
401 
402   TargetPassConfig::addIRPasses();
403 
404   if (TM->getOptLevel() != CodeGenOpt::None) {
405     addPass(createInterleavedAccessPass());
406     addPass(createX86PartialReductionPass());
407   }
408 
409   // Add passes that handle indirect branch removal and insertion of a retpoline
410   // thunk. These will be a no-op unless a function subtarget has the retpoline
411   // feature enabled.
412   addPass(createIndirectBrExpandPass());
413 
414   // Add Control Flow Guard checks.
415   const Triple &TT = TM->getTargetTriple();
416   if (TT.isOSWindows()) {
417     if (TT.getArch() == Triple::x86_64) {
418       addPass(createCFGuardDispatchPass());
419     } else {
420       addPass(createCFGuardCheckPass());
421     }
422   }
423 }
424 
425 bool X86PassConfig::addInstSelector() {
426   // Install an instruction selector.
427   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
428 
429   // For ELF, cleanup any local-dynamic TLS accesses.
430   if (TM->getTargetTriple().isOSBinFormatELF() &&
431       getOptLevel() != CodeGenOpt::None)
432     addPass(createCleanupLocalDynamicTLSPass());
433 
434   addPass(createX86GlobalBaseRegPass());
435   return false;
436 }
437 
438 bool X86PassConfig::addIRTranslator() {
439   addPass(new IRTranslator());
440   return false;
441 }
442 
443 bool X86PassConfig::addLegalizeMachineIR() {
444   addPass(new Legalizer());
445   return false;
446 }
447 
448 bool X86PassConfig::addRegBankSelect() {
449   addPass(new RegBankSelect());
450   return false;
451 }
452 
453 bool X86PassConfig::addGlobalInstructionSelect() {
454   addPass(new InstructionSelect());
455   return false;
456 }
457 
458 bool X86PassConfig::addILPOpts() {
459   if (EnableCondBrFoldingPass)
460     addPass(createX86CondBrFolding());
461   addPass(&EarlyIfConverterID);
462   if (EnableMachineCombinerPass)
463     addPass(&MachineCombinerID);
464   addPass(createX86CmovConverterPass());
465   return true;
466 }
467 
468 bool X86PassConfig::addPreISel() {
469   // Only add this pass for 32-bit x86 Windows.
470   const Triple &TT = TM->getTargetTriple();
471   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
472     addPass(createX86WinEHStatePass());
473   return true;
474 }
475 
476 void X86PassConfig::addPreRegAlloc() {
477   if (getOptLevel() != CodeGenOpt::None) {
478     addPass(&LiveRangeShrinkID);
479     addPass(createX86FixupSetCC());
480     addPass(createX86OptimizeLEAs());
481     addPass(createX86CallFrameOptimization());
482     addPass(createX86AvoidStoreForwardingBlocks());
483   }
484 
485   addPass(createX86SpeculativeLoadHardeningPass());
486   addPass(createX86FlagsCopyLoweringPass());
487   addPass(createX86WinAllocaExpander());
488 }
489 void X86PassConfig::addMachineSSAOptimization() {
490   addPass(createX86DomainReassignmentPass());
491   TargetPassConfig::addMachineSSAOptimization();
492 }
493 
494 void X86PassConfig::addPostRegAlloc() {
495   addPass(createX86FloatingPointStackifierPass());
496   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
497   // to using the Speculative Execution Side Effect Suppression pass for
498   // mitigation. This is to prevent slow downs due to
499   // analyses needed by the LVIHardening pass when compiling at -O0.
500   if (getOptLevel() != CodeGenOpt::None)
501     addPass(createX86LoadValueInjectionLoadHardeningPass());
502 }
503 
504 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
505 
506 void X86PassConfig::addPreEmitPass() {
507   if (getOptLevel() != CodeGenOpt::None) {
508     addPass(new X86ExecutionDomainFix());
509     addPass(createBreakFalseDeps());
510   }
511 
512   addPass(createX86IndirectBranchTrackingPass());
513 
514   addPass(createX86IssueVZeroUpperPass());
515 
516   if (getOptLevel() != CodeGenOpt::None) {
517     addPass(createX86FixupBWInsts());
518     addPass(createX86PadShortFunctions());
519     addPass(createX86FixupLEAs());
520   }
521   addPass(createX86EvexToVexInsts());
522   addPass(createX86DiscriminateMemOpsPass());
523   addPass(createX86InsertPrefetchPass());
524   addPass(createX86InsertX87waitPass());
525 }
526 
527 void X86PassConfig::addPreEmitPass2() {
528   const Triple &TT = TM->getTargetTriple();
529   const MCAsmInfo *MAI = TM->getMCAsmInfo();
530 
531   // The X86 Speculative Execution Pass must run after all control
532   // flow graph modifying passes. As a result it was listed to run right before
533   // the X86 Retpoline Thunks pass. The reason it must run after control flow
534   // graph modifications is that the model of LFENCE in LLVM has to be updated
535   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
536   // placement of this pass was hand checked to ensure that the subsequent
537   // passes don't move the code around the LFENCEs in a way that will hurt the
538   // correctness of this pass. This placement has been shown to work based on
539   // hand inspection of the codegen output.
540   addPass(createX86SpeculativeExecutionSideEffectSuppression());
541   addPass(createX86IndirectThunksPass());
542 
543   // Insert extra int3 instructions after trailing call instructions to avoid
544   // issues in the unwinder.
545   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
546     addPass(createX86AvoidTrailingCallPass());
547 
548   // Verify basic block incoming and outgoing cfa offset and register values and
549   // correct CFA calculation rule where needed by inserting appropriate CFI
550   // instructions.
551   if (!TT.isOSDarwin() &&
552       (!TT.isOSWindows() ||
553        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
554     addPass(createCFIInstrInserter());
555   // Identify valid longjmp targets for Windows Control Flow Guard.
556   if (TT.isOSWindows())
557     addPass(createCFGuardLongjmpPass());
558   addPass(createX86LoadValueInjectionRetHardeningPass());
559 }
560 
561 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
562   return getStandardCSEConfigForOpt(TM->getOptLevel());
563 }
564