1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 using namespace llvm;
26 
27 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
28                                cl::desc("Enable the machine combiner pass"),
29                                cl::init(true), cl::Hidden);
30 
31 extern "C" void LLVMInitializeX86Target() {
32   // Register the target.
33   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
34   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
35 }
36 
37 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
38   if (TT.isOSBinFormatMachO()) {
39     if (TT.getArch() == Triple::x86_64)
40       return make_unique<X86_64MachoTargetObjectFile>();
41     return make_unique<TargetLoweringObjectFileMachO>();
42   }
43 
44   if (TT.isOSLinux() || TT.isOSNaCl())
45     return make_unique<X86LinuxNaClTargetObjectFile>();
46   if (TT.isOSBinFormatELF())
47     return make_unique<X86ELFTargetObjectFile>();
48   if (TT.isKnownWindowsMSVCEnvironment())
49     return make_unique<X86WindowsTargetObjectFile>();
50   if (TT.isOSBinFormatCOFF())
51     return make_unique<TargetLoweringObjectFileCOFF>();
52   llvm_unreachable("unknown subtarget type");
53 }
54 
55 static std::string computeDataLayout(const Triple &TT) {
56   // X86 is little endian
57   std::string Ret = "e";
58 
59   Ret += DataLayout::getManglingComponent(TT);
60   // X86 and x32 have 32 bit pointers.
61   if ((TT.isArch64Bit() &&
62        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
63       !TT.isArch64Bit())
64     Ret += "-p:32:32";
65 
66   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
67   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
68     Ret += "-i64:64";
69   else
70     Ret += "-f64:32:64";
71 
72   // Some ABIs align long double to 128 bits, others to 32.
73   if (TT.isOSNaCl())
74     ; // No f80
75   else if (TT.isArch64Bit() || TT.isOSDarwin())
76     Ret += "-f80:128";
77   else
78     Ret += "-f80:32";
79 
80   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
81   if (TT.isArch64Bit())
82     Ret += "-n8:16:32:64";
83   else
84     Ret += "-n8:16:32";
85 
86   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
87   if (!TT.isArch64Bit() && TT.isOSWindows())
88     Ret += "-a:0:32-S32";
89   else
90     Ret += "-S128";
91 
92   return Ret;
93 }
94 
95 /// X86TargetMachine ctor - Create an X86 target.
96 ///
97 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
98                                    StringRef CPU, StringRef FS,
99                                    const TargetOptions &Options,
100                                    Reloc::Model RM, CodeModel::Model CM,
101                                    CodeGenOpt::Level OL)
102     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
103                         OL),
104       TLOF(createTLOF(Triple(getTargetTriple()))),
105       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
106   // Windows stack unwinder gets confused when execution flow "falls through"
107   // after a call to 'noreturn' function.
108   // To prevent that, we emit a trap for 'unreachable' IR instructions.
109   // (which on X86, happens to be the 'ud2' instruction)
110   if (Subtarget.isTargetWin64())
111     this->Options.TrapUnreachable = true;
112 
113   // TODO: By default, all reciprocal estimate operations are off because
114   // that matches the behavior before TargetRecip was added (except for btver2
115   // which used subtarget features to enable this type of codegen).
116   // We should change this to match GCC behavior where everything but
117   // scalar division estimates are turned on by default with -ffast-math.
118   this->Options.Reciprocals.setDefaults("all", false, 1);
119 
120   initAsmInfo();
121 }
122 
123 X86TargetMachine::~X86TargetMachine() {}
124 
125 const X86Subtarget *
126 X86TargetMachine::getSubtargetImpl(const Function &F) const {
127   Attribute CPUAttr = F.getFnAttribute("target-cpu");
128   Attribute FSAttr = F.getFnAttribute("target-features");
129 
130   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
131                         ? CPUAttr.getValueAsString().str()
132                         : TargetCPU;
133   std::string FS = !FSAttr.hasAttribute(Attribute::None)
134                        ? FSAttr.getValueAsString().str()
135                        : TargetFS;
136 
137   // FIXME: This is related to the code below to reset the target options,
138   // we need to know whether or not the soft float flag is set on the
139   // function before we can generate a subtarget. We also need to use
140   // it as a key for the subtarget since that can be the only difference
141   // between two functions.
142   bool SoftFloat =
143       F.hasFnAttribute("use-soft-float") &&
144       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
145   // If the soft float attribute is set on the function turn on the soft float
146   // subtarget feature.
147   if (SoftFloat)
148     FS += FS.empty() ? "+soft-float" : ",+soft-float";
149 
150   auto &I = SubtargetMap[CPU + FS];
151   if (!I) {
152     // This needs to be done before we create a new subtarget since any
153     // creation will depend on the TM and the code generation flags on the
154     // function that reside in TargetOptions.
155     resetTargetOptions(F);
156     I = llvm::make_unique<X86Subtarget>(Triple(TargetTriple), CPU, FS, *this,
157                                         Options.StackAlignmentOverride);
158   }
159   return I.get();
160 }
161 
162 //===----------------------------------------------------------------------===//
163 // Command line options for x86
164 //===----------------------------------------------------------------------===//
165 static cl::opt<bool>
166 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
167   cl::desc("Minimize AVX to SSE transition penalty"),
168   cl::init(true));
169 
170 //===----------------------------------------------------------------------===//
171 // X86 TTI query.
172 //===----------------------------------------------------------------------===//
173 
174 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
175   return TargetIRAnalysis(
176       [this](Function &F) { return TargetTransformInfo(X86TTIImpl(this, F)); });
177 }
178 
179 
180 //===----------------------------------------------------------------------===//
181 // Pass Pipeline Configuration
182 //===----------------------------------------------------------------------===//
183 
184 namespace {
185 /// X86 Code Generator Pass Configuration Options.
186 class X86PassConfig : public TargetPassConfig {
187 public:
188   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
189     : TargetPassConfig(TM, PM) {}
190 
191   X86TargetMachine &getX86TargetMachine() const {
192     return getTM<X86TargetMachine>();
193   }
194 
195   void addIRPasses() override;
196   bool addInstSelector() override;
197   bool addILPOpts() override;
198   bool addPreISel() override;
199   void addPreRegAlloc() override;
200   void addPostRegAlloc() override;
201   void addPreEmitPass() override;
202   void addPreSched2() override;
203 };
204 } // namespace
205 
206 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
207   return new X86PassConfig(this, PM);
208 }
209 
210 void X86PassConfig::addIRPasses() {
211   addPass(createAtomicExpandPass(&getX86TargetMachine()));
212 
213   TargetPassConfig::addIRPasses();
214 }
215 
216 bool X86PassConfig::addInstSelector() {
217   // Install an instruction selector.
218   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
219 
220   // For ELF, cleanup any local-dynamic TLS accesses.
221   if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
222       getOptLevel() != CodeGenOpt::None)
223     addPass(createCleanupLocalDynamicTLSPass());
224 
225   addPass(createX86GlobalBaseRegPass());
226 
227   return false;
228 }
229 
230 bool X86PassConfig::addILPOpts() {
231   addPass(&EarlyIfConverterID);
232   if (EnableMachineCombinerPass)
233     addPass(&MachineCombinerID);
234   return true;
235 }
236 
237 bool X86PassConfig::addPreISel() {
238   // Only add this pass for 32-bit x86 Windows.
239   Triple TT(TM->getTargetTriple());
240   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
241     addPass(createX86WinEHStatePass());
242   return true;
243 }
244 
245 void X86PassConfig::addPreRegAlloc() {
246   addPass(createX86CallFrameOptimization());
247 }
248 
249 void X86PassConfig::addPostRegAlloc() {
250   addPass(createX86FloatingPointStackifierPass());
251 }
252 
253 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
254 
255 void X86PassConfig::addPreEmitPass() {
256   if (getOptLevel() != CodeGenOpt::None)
257     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
258 
259   if (UseVZeroUpper)
260     addPass(createX86IssueVZeroUpperPass());
261 
262   if (getOptLevel() != CodeGenOpt::None) {
263     addPass(createX86PadShortFunctions());
264     addPass(createX86FixupLEAs());
265   }
266 }
267