1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
60   // Register the target.
61   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
62   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
63 
64   PassRegistry &PR = *PassRegistry::getPassRegistry();
65   initializeGlobalISel(PR);
66   initializeWinEHStatePassPass(PR);
67   initializeFixupBWInstPassPass(PR);
68   initializeEvexToVexInstPassPass(PR);
69   initializeFixupLEAPassPass(PR);
70   initializeFPSPass(PR);
71   initializeX86FixupSetCCPassPass(PR);
72   initializeX86CallFrameOptimizationPass(PR);
73   initializeX86CmovConverterPassPass(PR);
74   initializeX86ExpandPseudoPass(PR);
75   initializeX86ExecutionDomainFixPass(PR);
76   initializeX86DomainReassignmentPass(PR);
77   initializeX86AvoidSFBPassPass(PR);
78   initializeX86AvoidTrailingCallPassPass(PR);
79   initializeX86SpeculativeLoadHardeningPassPass(PR);
80   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
81   initializeX86FlagsCopyLoweringPassPass(PR);
82   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
83   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
84   initializeX86OptimizeLEAPassPass(PR);
85   initializeX86PartialReductionPass(PR);
86 }
87 
88 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
89   if (TT.isOSBinFormatMachO()) {
90     if (TT.getArch() == Triple::x86_64)
91       return std::make_unique<X86_64MachoTargetObjectFile>();
92     return std::make_unique<TargetLoweringObjectFileMachO>();
93   }
94 
95   if (TT.isOSBinFormatCOFF())
96     return std::make_unique<TargetLoweringObjectFileCOFF>();
97   return std::make_unique<X86ELFTargetObjectFile>();
98 }
99 
100 static std::string computeDataLayout(const Triple &TT) {
101   // X86 is little endian
102   std::string Ret = "e";
103 
104   Ret += DataLayout::getManglingComponent(TT);
105   // X86 and x32 have 32 bit pointers.
106   if ((TT.isArch64Bit() &&
107        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
108       !TT.isArch64Bit())
109     Ret += "-p:32:32";
110 
111   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
112   Ret += "-p270:32:32-p271:32:32-p272:64:64";
113 
114   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
115   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
116     Ret += "-i64:64";
117   else if (TT.isOSIAMCU())
118     Ret += "-i64:32-f64:32";
119   else
120     Ret += "-f64:32:64";
121 
122   // Some ABIs align long double to 128 bits, others to 32.
123   if (TT.isOSNaCl() || TT.isOSIAMCU())
124     ; // No f80
125   else if (TT.isArch64Bit() || TT.isOSDarwin())
126     Ret += "-f80:128";
127   else
128     Ret += "-f80:32";
129 
130   if (TT.isOSIAMCU())
131     Ret += "-f128:32";
132 
133   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
134   if (TT.isArch64Bit())
135     Ret += "-n8:16:32:64";
136   else
137     Ret += "-n8:16:32";
138 
139   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
140   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
141     Ret += "-a:0:32-S32";
142   else
143     Ret += "-S128";
144 
145   return Ret;
146 }
147 
148 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
149                                            bool JIT,
150                                            Optional<Reloc::Model> RM) {
151   bool is64Bit = TT.getArch() == Triple::x86_64;
152   if (!RM.hasValue()) {
153     // JIT codegen should use static relocations by default, since it's
154     // typically executed in process and not relocatable.
155     if (JIT)
156       return Reloc::Static;
157 
158     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
159     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
160     // use static relocation model by default.
161     if (TT.isOSDarwin()) {
162       if (is64Bit)
163         return Reloc::PIC_;
164       return Reloc::DynamicNoPIC;
165     }
166     if (TT.isOSWindows() && is64Bit)
167       return Reloc::PIC_;
168     return Reloc::Static;
169   }
170 
171   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
172   // is defined as a model for code which may be used in static or dynamic
173   // executables but not necessarily a shared library. On X86-32 we just
174   // compile in -static mode, in x86-64 we use PIC.
175   if (*RM == Reloc::DynamicNoPIC) {
176     if (is64Bit)
177       return Reloc::PIC_;
178     if (!TT.isOSDarwin())
179       return Reloc::Static;
180   }
181 
182   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
183   // the Mach-O file format doesn't support it.
184   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
185     return Reloc::PIC_;
186 
187   return *RM;
188 }
189 
190 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
191                                                  bool JIT, bool Is64Bit) {
192   if (CM) {
193     if (*CM == CodeModel::Tiny)
194       report_fatal_error("Target does not support the tiny CodeModel", false);
195     return *CM;
196   }
197   if (JIT)
198     return Is64Bit ? CodeModel::Large : CodeModel::Small;
199   return CodeModel::Small;
200 }
201 
202 /// Create an X86 target.
203 ///
204 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
205                                    StringRef CPU, StringRef FS,
206                                    const TargetOptions &Options,
207                                    Optional<Reloc::Model> RM,
208                                    Optional<CodeModel::Model> CM,
209                                    CodeGenOpt::Level OL, bool JIT)
210     : LLVMTargetMachine(
211           T, computeDataLayout(TT), TT, CPU, FS, Options,
212           getEffectiveRelocModel(TT, JIT, RM),
213           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
214           OL),
215       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
216   // On PS4, the "return address" of a 'noreturn' call must still be within
217   // the calling function, and TrapUnreachable is an easy way to get that.
218   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
219     this->Options.TrapUnreachable = true;
220     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
221   }
222 
223   setMachineOutliner(true);
224 
225   // x86 supports the debug entry values.
226   setSupportsDebugEntryValues(true);
227 
228   initAsmInfo();
229 }
230 
231 X86TargetMachine::~X86TargetMachine() = default;
232 
233 const X86Subtarget *
234 X86TargetMachine::getSubtargetImpl(const Function &F) const {
235   Attribute CPUAttr = F.getFnAttribute("target-cpu");
236   Attribute FSAttr = F.getFnAttribute("target-features");
237 
238   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
239                       ? CPUAttr.getValueAsString()
240                       : (StringRef)TargetCPU;
241   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
242                      ? FSAttr.getValueAsString()
243                      : (StringRef)TargetFS;
244 
245   SmallString<512> Key;
246   // The additions here are ordered so that the definitely short strings are
247   // added first so we won't exceed the small size. We append the
248   // much longer FS string at the end so that we only heap allocate at most
249   // one time.
250 
251   // Extract prefer-vector-width attribute.
252   unsigned PreferVectorWidthOverride = 0;
253   if (F.hasFnAttribute("prefer-vector-width")) {
254     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
255     unsigned Width;
256     if (!Val.getAsInteger(0, Width)) {
257       Key += "prefer-vector-width=";
258       Key += Val;
259       PreferVectorWidthOverride = Width;
260     }
261   }
262 
263   // Extract min-legal-vector-width attribute.
264   unsigned RequiredVectorWidth = UINT32_MAX;
265   if (F.hasFnAttribute("min-legal-vector-width")) {
266     StringRef Val =
267         F.getFnAttribute("min-legal-vector-width").getValueAsString();
268     unsigned Width;
269     if (!Val.getAsInteger(0, Width)) {
270       Key += "min-legal-vector-width=";
271       Key += Val;
272       RequiredVectorWidth = Width;
273     }
274   }
275 
276   // Add CPU to the Key.
277   Key += CPU;
278 
279   // Keep track of the start of the feature portion of the string.
280   unsigned FSStart = Key.size();
281 
282   // FIXME: This is related to the code below to reset the target options,
283   // we need to know whether or not the soft float flag is set on the
284   // function before we can generate a subtarget. We also need to use
285   // it as a key for the subtarget since that can be the only difference
286   // between two functions.
287   bool SoftFloat =
288       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
289   // If the soft float attribute is set on the function turn on the soft float
290   // subtarget feature.
291   if (SoftFloat)
292     Key += FS.empty() ? "+soft-float" : "+soft-float,";
293 
294   Key += FS;
295 
296   // We may have added +soft-float to the features so move the StringRef to
297   // point to the full string in the Key.
298   FS = Key.substr(FSStart);
299 
300   auto &I = SubtargetMap[Key];
301   if (!I) {
302     // This needs to be done before we create a new subtarget since any
303     // creation will depend on the TM and the code generation flags on the
304     // function that reside in TargetOptions.
305     resetTargetOptions(F);
306     I = std::make_unique<X86Subtarget>(
307         TargetTriple, CPU, FS, *this,
308         MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
309         RequiredVectorWidth);
310   }
311   return I.get();
312 }
313 
314 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
315                                            unsigned DestAS) const {
316   assert(SrcAS != DestAS && "Expected different address spaces!");
317   if (getPointerSize(SrcAS) != getPointerSize(DestAS))
318     return false;
319   return SrcAS < 256 && DestAS < 256;
320 }
321 
322 //===----------------------------------------------------------------------===//
323 // X86 TTI query.
324 //===----------------------------------------------------------------------===//
325 
326 TargetTransformInfo
327 X86TargetMachine::getTargetTransformInfo(const Function &F) {
328   return TargetTransformInfo(X86TTIImpl(this, F));
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // Pass Pipeline Configuration
333 //===----------------------------------------------------------------------===//
334 
335 namespace {
336 
337 /// X86 Code Generator Pass Configuration Options.
338 class X86PassConfig : public TargetPassConfig {
339 public:
340   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
341     : TargetPassConfig(TM, PM) {}
342 
343   X86TargetMachine &getX86TargetMachine() const {
344     return getTM<X86TargetMachine>();
345   }
346 
347   ScheduleDAGInstrs *
348   createMachineScheduler(MachineSchedContext *C) const override {
349     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
350     DAG->addMutation(createX86MacroFusionDAGMutation());
351     return DAG;
352   }
353 
354   ScheduleDAGInstrs *
355   createPostMachineScheduler(MachineSchedContext *C) const override {
356     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
357     DAG->addMutation(createX86MacroFusionDAGMutation());
358     return DAG;
359   }
360 
361   void addIRPasses() override;
362   bool addInstSelector() override;
363   bool addIRTranslator() override;
364   bool addLegalizeMachineIR() override;
365   bool addRegBankSelect() override;
366   bool addGlobalInstructionSelect() override;
367   bool addILPOpts() override;
368   bool addPreISel() override;
369   void addMachineSSAOptimization() override;
370   void addPreRegAlloc() override;
371   void addPostRegAlloc() override;
372   void addPreEmitPass() override;
373   void addPreEmitPass2() override;
374   void addPreSched2() override;
375 
376   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
377 };
378 
379 class X86ExecutionDomainFix : public ExecutionDomainFix {
380 public:
381   static char ID;
382   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
383   StringRef getPassName() const override {
384     return "X86 Execution Dependency Fix";
385   }
386 };
387 char X86ExecutionDomainFix::ID;
388 
389 } // end anonymous namespace
390 
391 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
392   "X86 Execution Domain Fix", false, false)
393 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
394 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
395   "X86 Execution Domain Fix", false, false)
396 
397 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
398   return new X86PassConfig(*this, PM);
399 }
400 
401 void X86PassConfig::addIRPasses() {
402   addPass(createAtomicExpandPass());
403 
404   TargetPassConfig::addIRPasses();
405 
406   if (TM->getOptLevel() != CodeGenOpt::None) {
407     addPass(createInterleavedAccessPass());
408     addPass(createX86PartialReductionPass());
409   }
410 
411   // Add passes that handle indirect branch removal and insertion of a retpoline
412   // thunk. These will be a no-op unless a function subtarget has the retpoline
413   // feature enabled.
414   addPass(createIndirectBrExpandPass());
415 
416   // Add Control Flow Guard checks.
417   const Triple &TT = TM->getTargetTriple();
418   if (TT.isOSWindows()) {
419     if (TT.getArch() == Triple::x86_64) {
420       addPass(createCFGuardDispatchPass());
421     } else {
422       addPass(createCFGuardCheckPass());
423     }
424   }
425 }
426 
427 bool X86PassConfig::addInstSelector() {
428   // Install an instruction selector.
429   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
430 
431   // For ELF, cleanup any local-dynamic TLS accesses.
432   if (TM->getTargetTriple().isOSBinFormatELF() &&
433       getOptLevel() != CodeGenOpt::None)
434     addPass(createCleanupLocalDynamicTLSPass());
435 
436   addPass(createX86GlobalBaseRegPass());
437   return false;
438 }
439 
440 bool X86PassConfig::addIRTranslator() {
441   addPass(new IRTranslator());
442   return false;
443 }
444 
445 bool X86PassConfig::addLegalizeMachineIR() {
446   addPass(new Legalizer());
447   return false;
448 }
449 
450 bool X86PassConfig::addRegBankSelect() {
451   addPass(new RegBankSelect());
452   return false;
453 }
454 
455 bool X86PassConfig::addGlobalInstructionSelect() {
456   addPass(new InstructionSelect());
457   return false;
458 }
459 
460 bool X86PassConfig::addILPOpts() {
461   addPass(&EarlyIfConverterID);
462   if (EnableMachineCombinerPass)
463     addPass(&MachineCombinerID);
464   addPass(createX86CmovConverterPass());
465   return true;
466 }
467 
468 bool X86PassConfig::addPreISel() {
469   // Only add this pass for 32-bit x86 Windows.
470   const Triple &TT = TM->getTargetTriple();
471   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
472     addPass(createX86WinEHStatePass());
473   return true;
474 }
475 
476 void X86PassConfig::addPreRegAlloc() {
477   if (getOptLevel() != CodeGenOpt::None) {
478     addPass(&LiveRangeShrinkID);
479     addPass(createX86FixupSetCC());
480     addPass(createX86OptimizeLEAs());
481     addPass(createX86CallFrameOptimization());
482     addPass(createX86AvoidStoreForwardingBlocks());
483   }
484 
485   addPass(createX86SpeculativeLoadHardeningPass());
486   addPass(createX86FlagsCopyLoweringPass());
487   addPass(createX86WinAllocaExpander());
488 }
489 void X86PassConfig::addMachineSSAOptimization() {
490   addPass(createX86DomainReassignmentPass());
491   TargetPassConfig::addMachineSSAOptimization();
492 }
493 
494 void X86PassConfig::addPostRegAlloc() {
495   addPass(createX86FloatingPointStackifierPass());
496   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
497   // to using the Speculative Execution Side Effect Suppression pass for
498   // mitigation. This is to prevent slow downs due to
499   // analyses needed by the LVIHardening pass when compiling at -O0.
500   if (getOptLevel() != CodeGenOpt::None)
501     addPass(createX86LoadValueInjectionLoadHardeningPass());
502 }
503 
504 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
505 
506 void X86PassConfig::addPreEmitPass() {
507   if (getOptLevel() != CodeGenOpt::None) {
508     addPass(new X86ExecutionDomainFix());
509     addPass(createBreakFalseDeps());
510   }
511 
512   addPass(createX86IndirectBranchTrackingPass());
513 
514   addPass(createX86IssueVZeroUpperPass());
515 
516   if (getOptLevel() != CodeGenOpt::None) {
517     addPass(createX86FixupBWInsts());
518     addPass(createX86PadShortFunctions());
519     addPass(createX86FixupLEAs());
520   }
521   addPass(createX86EvexToVexInsts());
522   addPass(createX86DiscriminateMemOpsPass());
523   addPass(createX86InsertPrefetchPass());
524   addPass(createX86InsertX87waitPass());
525 }
526 
527 void X86PassConfig::addPreEmitPass2() {
528   const Triple &TT = TM->getTargetTriple();
529   const MCAsmInfo *MAI = TM->getMCAsmInfo();
530 
531   // The X86 Speculative Execution Pass must run after all control
532   // flow graph modifying passes. As a result it was listed to run right before
533   // the X86 Retpoline Thunks pass. The reason it must run after control flow
534   // graph modifications is that the model of LFENCE in LLVM has to be updated
535   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
536   // placement of this pass was hand checked to ensure that the subsequent
537   // passes don't move the code around the LFENCEs in a way that will hurt the
538   // correctness of this pass. This placement has been shown to work based on
539   // hand inspection of the codegen output.
540   addPass(createX86SpeculativeExecutionSideEffectSuppression());
541   addPass(createX86IndirectThunksPass());
542 
543   // Insert extra int3 instructions after trailing call instructions to avoid
544   // issues in the unwinder.
545   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
546     addPass(createX86AvoidTrailingCallPass());
547 
548   // Verify basic block incoming and outgoing cfa offset and register values and
549   // correct CFA calculation rule where needed by inserting appropriate CFI
550   // instructions.
551   if (!TT.isOSDarwin() &&
552       (!TT.isOSWindows() ||
553        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
554     addPass(createCFIInstrInserter());
555   // Identify valid longjmp targets for Windows Control Flow Guard.
556   if (TT.isOSWindows())
557     addPass(createCFGuardLongjmpPass());
558   addPass(createX86LoadValueInjectionRetHardeningPass());
559 }
560 
561 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
562   return getStandardCSEConfigForOpt(TM->getOptLevel());
563 }
564