1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the X86 specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86MCAsmInfo.h" 15 #include "X86TargetMachine.h" 16 #include "X86.h" 17 #include "llvm/PassManager.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/Passes.h" 20 #include "llvm/MC/MCCodeEmitter.h" 21 #include "llvm/MC/MCStreamer.h" 22 #include "llvm/Support/FormattedStream.h" 23 #include "llvm/Target/TargetOptions.h" 24 #include "llvm/Target/TargetRegistry.h" 25 using namespace llvm; 26 27 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { 28 Triple TheTriple(TT); 29 30 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) { 31 if (TheTriple.getArch() == Triple::x86_64) 32 return new X86_64MCAsmInfoDarwin(TheTriple); 33 else 34 return new X86MCAsmInfoDarwin(TheTriple); 35 } 36 37 if (TheTriple.isOSWindows()) 38 return new X86MCAsmInfoCOFF(TheTriple); 39 40 return new X86ELFMCAsmInfo(TheTriple); 41 } 42 43 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT, 44 MCContext &Ctx, TargetAsmBackend &TAB, 45 raw_ostream &_OS, 46 MCCodeEmitter *_Emitter, 47 bool RelaxAll, 48 bool NoExecStack) { 49 Triple TheTriple(TT); 50 51 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) 52 return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll); 53 54 if (TheTriple.isOSWindows()) 55 return createWinCOFFStreamer(Ctx, TAB, *_Emitter, _OS, RelaxAll); 56 57 return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll, NoExecStack); 58 } 59 60 extern "C" void LLVMInitializeX86Target() { 61 // Register the target. 62 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 63 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 64 65 // Register the target asm info. 66 RegisterAsmInfoFn A(TheX86_32Target, createMCAsmInfo); 67 RegisterAsmInfoFn B(TheX86_64Target, createMCAsmInfo); 68 69 // Register the code emitter. 70 TargetRegistry::RegisterCodeEmitter(TheX86_32Target, 71 createX86MCCodeEmitter); 72 TargetRegistry::RegisterCodeEmitter(TheX86_64Target, 73 createX86MCCodeEmitter); 74 75 // Register the asm backend. 76 TargetRegistry::RegisterAsmBackend(TheX86_32Target, 77 createX86_32AsmBackend); 78 TargetRegistry::RegisterAsmBackend(TheX86_64Target, 79 createX86_64AsmBackend); 80 81 // Register the object streamer. 82 TargetRegistry::RegisterObjectStreamer(TheX86_32Target, 83 createMCStreamer); 84 TargetRegistry::RegisterObjectStreamer(TheX86_64Target, 85 createMCStreamer); 86 } 87 88 89 X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT, 90 const std::string &CPU, 91 const std::string &FS) 92 : X86TargetMachine(T, TT, CPU, FS, false), 93 DataLayout(getSubtargetImpl()->isTargetDarwin() ? 94 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" : 95 (getSubtargetImpl()->isTargetCygMing() || 96 getSubtargetImpl()->isTargetWindows()) ? 97 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-n8:16:32" : 98 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-n8:16:32"), 99 InstrInfo(*this), 100 TSInfo(*this), 101 TLInfo(*this), 102 JITInfo(*this) { 103 } 104 105 106 X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, 107 const std::string &CPU, 108 const std::string &FS) 109 : X86TargetMachine(T, TT, CPU, FS, true), 110 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"), 111 InstrInfo(*this), 112 TSInfo(*this), 113 TLInfo(*this), 114 JITInfo(*this) { 115 } 116 117 /// X86TargetMachine ctor - Create an X86 target. 118 /// 119 X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, 120 const std::string &CPU, 121 const std::string &FS, bool is64Bit) 122 : LLVMTargetMachine(T, TT, CPU, FS), 123 Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), 124 FrameLowering(*this, Subtarget), 125 ELFWriterInfo(is64Bit, true) { 126 DefRelocModel = getRelocationModel(); 127 128 // If no relocation model was picked, default as appropriate for the target. 129 if (getRelocationModel() == Reloc::Default) { 130 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. 131 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we 132 // use static relocation model by default. 133 if (Subtarget.isTargetDarwin()) { 134 if (Subtarget.is64Bit()) 135 setRelocationModel(Reloc::PIC_); 136 else 137 setRelocationModel(Reloc::DynamicNoPIC); 138 } else if (Subtarget.isTargetWin64()) 139 setRelocationModel(Reloc::PIC_); 140 else 141 setRelocationModel(Reloc::Static); 142 } 143 144 assert(getRelocationModel() != Reloc::Default && 145 "Relocation mode not picked"); 146 147 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC 148 // is defined as a model for code which may be used in static or dynamic 149 // executables but not necessarily a shared library. On X86-32 we just 150 // compile in -static mode, in x86-64 we use PIC. 151 if (getRelocationModel() == Reloc::DynamicNoPIC) { 152 if (is64Bit) 153 setRelocationModel(Reloc::PIC_); 154 else if (!Subtarget.isTargetDarwin()) 155 setRelocationModel(Reloc::Static); 156 } 157 158 // If we are on Darwin, disallow static relocation model in X86-64 mode, since 159 // the Mach-O file format doesn't support it. 160 if (getRelocationModel() == Reloc::Static && 161 Subtarget.isTargetDarwin() && 162 is64Bit) 163 setRelocationModel(Reloc::PIC_); 164 165 // Determine the PICStyle based on the target selected. 166 if (getRelocationModel() == Reloc::Static) { 167 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 168 Subtarget.setPICStyle(PICStyles::None); 169 } else if (Subtarget.is64Bit()) { 170 // PIC in 64 bit mode is always rip-rel. 171 Subtarget.setPICStyle(PICStyles::RIPRel); 172 } else if (Subtarget.isTargetCygMing()) { 173 Subtarget.setPICStyle(PICStyles::None); 174 } else if (Subtarget.isTargetDarwin()) { 175 if (getRelocationModel() == Reloc::PIC_) 176 Subtarget.setPICStyle(PICStyles::StubPIC); 177 else { 178 assert(getRelocationModel() == Reloc::DynamicNoPIC); 179 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 180 } 181 } else if (Subtarget.isTargetELF()) { 182 Subtarget.setPICStyle(PICStyles::GOT); 183 } 184 185 // Finally, if we have "none" as our PIC style, force to static mode. 186 if (Subtarget.getPICStyle() == PICStyles::None) 187 setRelocationModel(Reloc::Static); 188 189 // default to hard float ABI 190 if (FloatABIType == FloatABI::Default) 191 FloatABIType = FloatABI::Hard; 192 } 193 194 //===----------------------------------------------------------------------===// 195 // Pass Pipeline Configuration 196 //===----------------------------------------------------------------------===// 197 198 bool X86TargetMachine::addInstSelector(PassManagerBase &PM, 199 CodeGenOpt::Level OptLevel) { 200 // Install an instruction selector. 201 PM.add(createX86ISelDag(*this, OptLevel)); 202 203 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 204 if (!Subtarget.is64Bit()) 205 PM.add(createGlobalBaseRegPass()); 206 207 return false; 208 } 209 210 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, 211 CodeGenOpt::Level OptLevel) { 212 PM.add(createX86MaxStackAlignmentHeuristicPass()); 213 return false; // -print-machineinstr shouldn't print after this. 214 } 215 216 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, 217 CodeGenOpt::Level OptLevel) { 218 PM.add(createX86FloatingPointStackifierPass()); 219 return true; // -print-machineinstr should print after this. 220 } 221 222 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM, 223 CodeGenOpt::Level OptLevel) { 224 if (OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) { 225 PM.add(createSSEDomainFixPass()); 226 return true; 227 } 228 return false; 229 } 230 231 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 232 CodeGenOpt::Level OptLevel, 233 JITCodeEmitter &JCE) { 234 // FIXME: Move this to TargetJITInfo! 235 // On Darwin, do not override 64-bit setting made in X86TargetMachine(). 236 if (DefRelocModel == Reloc::Default && 237 (!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) { 238 setRelocationModel(Reloc::Static); 239 Subtarget.setPICStyle(PICStyles::None); 240 } 241 242 243 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 244 245 return false; 246 } 247 248 void X86TargetMachine::setCodeModelForStatic() { 249 250 if (getCodeModel() != CodeModel::Default) return; 251 252 // For static codegen, if we're not already set, use Small codegen. 253 setCodeModel(CodeModel::Small); 254 } 255 256 257 void X86TargetMachine::setCodeModelForJIT() { 258 259 if (getCodeModel() != CodeModel::Default) return; 260 261 // 64-bit JIT places everything in the same buffer except external functions. 262 if (Subtarget.is64Bit()) 263 setCodeModel(CodeModel::Large); 264 else 265 setCodeModel(CodeModel::Small); 266 } 267