1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the X86 specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86TargetMachine.h" 15 #include "X86.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/FormattedStream.h" 21 #include "llvm/Target/TargetOptions.h" 22 #include "llvm/Support/TargetRegistry.h" 23 using namespace llvm; 24 25 extern "C" void LLVMInitializeX86Target() { 26 // Register the target. 27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 29 } 30 31 32 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, 33 StringRef CPU, StringRef FS, 34 Reloc::Model RM, CodeModel::Model CM) 35 : X86TargetMachine(T, TT, CPU, FS, RM, CM, false), 36 DataLayout(getSubtargetImpl()->isTargetDarwin() ? 37 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32-S128" : 38 (getSubtargetImpl()->isTargetCygMing() || 39 getSubtargetImpl()->isTargetWindows()) ? 40 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-n8:16:32-S32" : 41 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-n8:16:32-S128"), 42 InstrInfo(*this), 43 TSInfo(*this), 44 TLInfo(*this), 45 JITInfo(*this) { 46 } 47 48 49 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, 50 StringRef CPU, StringRef FS, 51 Reloc::Model RM, CodeModel::Model CM) 52 : X86TargetMachine(T, TT, CPU, FS, RM, CM, true), 53 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64-S128"), 54 InstrInfo(*this), 55 TSInfo(*this), 56 TLInfo(*this), 57 JITInfo(*this) { 58 } 59 60 /// X86TargetMachine ctor - Create an X86 target. 61 /// 62 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 63 StringRef CPU, StringRef FS, 64 Reloc::Model RM, CodeModel::Model CM, 65 bool is64Bit) 66 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 67 Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit), 68 FrameLowering(*this, Subtarget), 69 ELFWriterInfo(is64Bit, true) { 70 // Determine the PICStyle based on the target selected. 71 if (getRelocationModel() == Reloc::Static) { 72 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 73 Subtarget.setPICStyle(PICStyles::None); 74 } else if (Subtarget.is64Bit()) { 75 // PIC in 64 bit mode is always rip-rel. 76 Subtarget.setPICStyle(PICStyles::RIPRel); 77 } else if (Subtarget.isTargetCygMing()) { 78 Subtarget.setPICStyle(PICStyles::None); 79 } else if (Subtarget.isTargetDarwin()) { 80 if (getRelocationModel() == Reloc::PIC_) 81 Subtarget.setPICStyle(PICStyles::StubPIC); 82 else { 83 assert(getRelocationModel() == Reloc::DynamicNoPIC); 84 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 85 } 86 } else if (Subtarget.isTargetELF()) { 87 Subtarget.setPICStyle(PICStyles::GOT); 88 } 89 90 // default to hard float ABI 91 if (FloatABIType == FloatABI::Default) 92 FloatABIType = FloatABI::Hard; 93 } 94 95 //===----------------------------------------------------------------------===// 96 // Command line options for x86 97 //===----------------------------------------------------------------------===// 98 static cl::opt<bool> 99 UseVZeroUpper("x86-use-vzeroupper", 100 cl::desc("Minimize AVX to SSE transition penalty"), 101 cl::init(false)); 102 103 //===----------------------------------------------------------------------===// 104 // Pass Pipeline Configuration 105 //===----------------------------------------------------------------------===// 106 107 bool X86TargetMachine::addInstSelector(PassManagerBase &PM, 108 CodeGenOpt::Level OptLevel) { 109 // Install an instruction selector. 110 PM.add(createX86ISelDag(*this, OptLevel)); 111 112 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 113 if (!Subtarget.is64Bit()) 114 PM.add(createGlobalBaseRegPass()); 115 116 return false; 117 } 118 119 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, 120 CodeGenOpt::Level OptLevel) { 121 PM.add(createX86MaxStackAlignmentHeuristicPass()); 122 return false; // -print-machineinstr shouldn't print after this. 123 } 124 125 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, 126 CodeGenOpt::Level OptLevel) { 127 PM.add(createX86FloatingPointStackifierPass()); 128 return true; // -print-machineinstr should print after this. 129 } 130 131 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM, 132 CodeGenOpt::Level OptLevel) { 133 bool ShouldPrint = false; 134 if (OptLevel != CodeGenOpt::None && 135 (Subtarget.hasSSE2() || Subtarget.hasAVX())) { 136 PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass)); 137 ShouldPrint = true; 138 } 139 140 if (Subtarget.hasAVX() && UseVZeroUpper) { 141 PM.add(createX86IssueVZeroUpperPass()); 142 ShouldPrint = true; 143 } 144 145 return ShouldPrint; 146 } 147 148 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 149 CodeGenOpt::Level OptLevel, 150 JITCodeEmitter &JCE) { 151 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 152 153 return false; 154 } 155