1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
22 using namespace llvm;
23 
24 extern "C" void LLVMInitializeX86Target() {
25   // Register the target.
26   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
27   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
28 }
29 
30 void X86TargetMachine::anchor() { }
31 
32 /// X86TargetMachine ctor - Create an X86 target.
33 ///
34 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
35                                    StringRef FS, const TargetOptions &Options,
36                                    Reloc::Model RM, CodeModel::Model CM,
37                                    CodeGenOpt::Level OL)
38     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
39       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
40   // default to hard float ABI
41   if (Options.FloatABIType == FloatABI::Default)
42     this->Options.FloatABIType = FloatABI::Hard;
43 
44   // Windows stack unwinder gets confused when execution flow "falls through"
45   // after a call to 'noreturn' function.
46   // To prevent that, we emit a trap for 'unreachable' IR instructions.
47   // (which on X86, happens to be the 'ud2' instruction)
48   if (Subtarget.isTargetWin64())
49     this->Options.TrapUnreachable = true;
50 
51   initAsmInfo();
52 }
53 
54 //===----------------------------------------------------------------------===//
55 // Command line options for x86
56 //===----------------------------------------------------------------------===//
57 static cl::opt<bool>
58 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
59   cl::desc("Minimize AVX to SSE transition penalty"),
60   cl::init(true));
61 
62 //===----------------------------------------------------------------------===//
63 // X86 Analysis Pass Setup
64 //===----------------------------------------------------------------------===//
65 
66 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
67   // Add first the target-independent BasicTTI pass, then our X86 pass. This
68   // allows the X86 pass to delegate to the target independent layer when
69   // appropriate.
70   PM.add(createBasicTargetTransformInfoPass(this));
71   PM.add(createX86TargetTransformInfoPass(this));
72 }
73 
74 
75 //===----------------------------------------------------------------------===//
76 // Pass Pipeline Configuration
77 //===----------------------------------------------------------------------===//
78 
79 namespace {
80 /// X86 Code Generator Pass Configuration Options.
81 class X86PassConfig : public TargetPassConfig {
82 public:
83   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
84     : TargetPassConfig(TM, PM) {}
85 
86   X86TargetMachine &getX86TargetMachine() const {
87     return getTM<X86TargetMachine>();
88   }
89 
90   const X86Subtarget &getX86Subtarget() const {
91     return *getX86TargetMachine().getSubtargetImpl();
92   }
93 
94   void addIRPasses() override;
95   bool addInstSelector() override;
96   bool addILPOpts() override;
97   bool addPreRegAlloc() override;
98   bool addPostRegAlloc() override;
99   bool addPreEmitPass() override;
100 };
101 } // namespace
102 
103 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
104   return new X86PassConfig(this, PM);
105 }
106 
107 void X86PassConfig::addIRPasses() {
108   addPass(createX86AtomicExpandPass(&getX86TargetMachine()));
109 
110   TargetPassConfig::addIRPasses();
111 }
112 
113 bool X86PassConfig::addInstSelector() {
114   // Install an instruction selector.
115   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
116 
117   // For ELF, cleanup any local-dynamic TLS accesses.
118   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
119     addPass(createCleanupLocalDynamicTLSPass());
120 
121   addPass(createX86GlobalBaseRegPass());
122 
123   return false;
124 }
125 
126 bool X86PassConfig::addILPOpts() {
127   addPass(&EarlyIfConverterID);
128   return true;
129 }
130 
131 bool X86PassConfig::addPreRegAlloc() {
132   return false;  // -print-machineinstr shouldn't print after this.
133 }
134 
135 bool X86PassConfig::addPostRegAlloc() {
136   addPass(createX86FloatingPointStackifierPass());
137   return true;  // -print-machineinstr should print after this.
138 }
139 
140 bool X86PassConfig::addPreEmitPass() {
141   bool ShouldPrint = false;
142   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
143     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
144     ShouldPrint = true;
145   }
146 
147   if (UseVZeroUpper) {
148     addPass(createX86IssueVZeroUpperPass());
149     ShouldPrint = true;
150   }
151 
152   if (getOptLevel() != CodeGenOpt::None) {
153     addPass(createX86PadShortFunctions());
154     addPass(createX86FixupLEAs());
155     ShouldPrint = true;
156   }
157 
158   return ShouldPrint;
159 }
160 
161 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
162                                       JITCodeEmitter &JCE) {
163   PM.add(createX86JITCodeEmitterPass(*this, JCE));
164 
165   return false;
166 }
167