1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 using namespace llvm;
26 
27 extern "C" void LLVMInitializeX86Target() {
28   // Register the target.
29   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
30   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
31 }
32 
33 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
34   if (TT.isOSBinFormatMachO()) {
35     if (TT.getArch() == Triple::x86_64)
36       return make_unique<X86_64MachoTargetObjectFile>();
37     return make_unique<TargetLoweringObjectFileMachO>();
38   }
39 
40   if (TT.isOSLinux() || TT.isOSNaCl())
41     return make_unique<X86LinuxNaClTargetObjectFile>();
42   if (TT.isOSBinFormatELF())
43     return make_unique<X86ELFTargetObjectFile>();
44   if (TT.isKnownWindowsMSVCEnvironment())
45     return make_unique<X86WindowsTargetObjectFile>();
46   if (TT.isOSBinFormatCOFF())
47     return make_unique<TargetLoweringObjectFileCOFF>();
48   llvm_unreachable("unknown subtarget type");
49 }
50 
51 static std::string computeDataLayout(const Triple &TT) {
52   // X86 is little endian
53   std::string Ret = "e";
54 
55   Ret += DataLayout::getManglingComponent(TT);
56   // X86 and x32 have 32 bit pointers.
57   if ((TT.isArch64Bit() &&
58        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
59       !TT.isArch64Bit())
60     Ret += "-p:32:32";
61 
62   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
63   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
64     Ret += "-i64:64";
65   else
66     Ret += "-f64:32:64";
67 
68   // Some ABIs align long double to 128 bits, others to 32.
69   if (TT.isOSNaCl())
70     ; // No f80
71   else if (TT.isArch64Bit() || TT.isOSDarwin())
72     Ret += "-f80:128";
73   else
74     Ret += "-f80:32";
75 
76   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
77   if (TT.isArch64Bit())
78     Ret += "-n8:16:32:64";
79   else
80     Ret += "-n8:16:32";
81 
82   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
83   if (!TT.isArch64Bit() && TT.isOSWindows())
84     Ret += "-a:0:32-S32";
85   else
86     Ret += "-S128";
87 
88   return Ret;
89 }
90 
91 /// X86TargetMachine ctor - Create an X86 target.
92 ///
93 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
94                                    StringRef FS, const TargetOptions &Options,
95                                    Reloc::Model RM, CodeModel::Model CM,
96                                    CodeGenOpt::Level OL)
97     : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
98                         RM, CM, OL),
99       TLOF(createTLOF(Triple(getTargetTriple()))),
100       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
101   // Windows stack unwinder gets confused when execution flow "falls through"
102   // after a call to 'noreturn' function.
103   // To prevent that, we emit a trap for 'unreachable' IR instructions.
104   // (which on X86, happens to be the 'ud2' instruction)
105   if (Subtarget.isTargetWin64())
106     this->Options.TrapUnreachable = true;
107 
108   initAsmInfo();
109 }
110 
111 X86TargetMachine::~X86TargetMachine() {}
112 
113 const X86Subtarget *
114 X86TargetMachine::getSubtargetImpl(const Function &F) const {
115   Attribute CPUAttr = F.getFnAttribute("target-cpu");
116   Attribute FSAttr = F.getFnAttribute("target-features");
117 
118   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
119                         ? CPUAttr.getValueAsString().str()
120                         : TargetCPU;
121   std::string FS = !FSAttr.hasAttribute(Attribute::None)
122                        ? FSAttr.getValueAsString().str()
123                        : TargetFS;
124 
125   // FIXME: This is related to the code below to reset the target options,
126   // we need to know whether or not the soft float flag is set on the
127   // function before we can generate a subtarget. We also need to use
128   // it as a key for the subtarget since that can be the only difference
129   // between two functions.
130   bool SoftFloat =
131       F.hasFnAttribute("use-soft-float") &&
132       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
133   // If the soft float attribute is set on the function turn on the soft float
134   // subtarget feature.
135   if (SoftFloat)
136     FS += FS.empty() ? "+soft-float" : ",+soft-float";
137 
138   auto &I = SubtargetMap[CPU + FS];
139   if (!I) {
140     // This needs to be done before we create a new subtarget since any
141     // creation will depend on the TM and the code generation flags on the
142     // function that reside in TargetOptions.
143     resetTargetOptions(F);
144     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
145                                         Options.StackAlignmentOverride);
146   }
147   return I.get();
148 }
149 
150 //===----------------------------------------------------------------------===//
151 // Command line options for x86
152 //===----------------------------------------------------------------------===//
153 static cl::opt<bool>
154 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
155   cl::desc("Minimize AVX to SSE transition penalty"),
156   cl::init(true));
157 
158 //===----------------------------------------------------------------------===//
159 // X86 TTI query.
160 //===----------------------------------------------------------------------===//
161 
162 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
163   return TargetIRAnalysis(
164       [this](Function &F) { return TargetTransformInfo(X86TTIImpl(this, F)); });
165 }
166 
167 
168 //===----------------------------------------------------------------------===//
169 // Pass Pipeline Configuration
170 //===----------------------------------------------------------------------===//
171 
172 namespace {
173 /// X86 Code Generator Pass Configuration Options.
174 class X86PassConfig : public TargetPassConfig {
175 public:
176   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
177     : TargetPassConfig(TM, PM) {}
178 
179   X86TargetMachine &getX86TargetMachine() const {
180     return getTM<X86TargetMachine>();
181   }
182 
183   void addIRPasses() override;
184   bool addInstSelector() override;
185   bool addILPOpts() override;
186   bool addPreISel() override;
187   void addPreRegAlloc() override;
188   void addPostRegAlloc() override;
189   void addPreEmitPass() override;
190 };
191 } // namespace
192 
193 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
194   return new X86PassConfig(this, PM);
195 }
196 
197 void X86PassConfig::addIRPasses() {
198   addPass(createAtomicExpandPass(&getX86TargetMachine()));
199 
200   TargetPassConfig::addIRPasses();
201 }
202 
203 bool X86PassConfig::addInstSelector() {
204   // Install an instruction selector.
205   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
206 
207   // For ELF, cleanup any local-dynamic TLS accesses.
208   if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
209       getOptLevel() != CodeGenOpt::None)
210     addPass(createCleanupLocalDynamicTLSPass());
211 
212   addPass(createX86GlobalBaseRegPass());
213 
214   return false;
215 }
216 
217 bool X86PassConfig::addILPOpts() {
218   addPass(&EarlyIfConverterID);
219   return true;
220 }
221 
222 bool X86PassConfig::addPreISel() {
223   // Only add this pass for 32-bit x86.
224   Triple TT(TM->getTargetTriple());
225   if (TT.getArch() == Triple::x86)
226     addPass(createX86WinEHStatePass());
227   return true;
228 }
229 
230 void X86PassConfig::addPreRegAlloc() {
231   addPass(createX86CallFrameOptimization());
232 }
233 
234 void X86PassConfig::addPostRegAlloc() {
235   addPass(createX86FloatingPointStackifierPass());
236 }
237 
238 void X86PassConfig::addPreEmitPass() {
239   if (getOptLevel() != CodeGenOpt::None)
240     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
241 
242   if (UseVZeroUpper)
243     addPass(createX86IssueVZeroUpperPass());
244 
245   if (getOptLevel() != CodeGenOpt::None) {
246     addPass(createX86PadShortFunctions());
247     addPass(createX86FixupLEAs());
248   }
249 }
250