1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 extern "C" void LLVMInitializeX86Target() {
26   // Register the target.
27   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
28   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
29 }
30 
31 void X86TargetMachine::anchor() { }
32 
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34   // X86 is little endian
35   std::string Ret = "e";
36 
37   Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
38   // X86 and x32 have 32 bit pointers.
39   if (ST.isTarget64BitILP32() || !ST.is64Bit())
40     Ret += "-p:32:32";
41 
42   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
43   if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
44       ST.isTargetNaCl())
45     Ret += "-i64:64";
46   else
47     Ret += "-f64:32:64";
48 
49   // Some ABIs align long double to 128 bits, others to 32.
50   if (ST.isTargetNaCl())
51     ; // No f80
52   else if (ST.is64Bit() || ST.isTargetDarwin())
53     Ret += "-f80:128";
54   else
55     Ret += "-f80:32";
56 
57   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
58   if (ST.is64Bit())
59     Ret += "-n8:16:32:64";
60   else
61     Ret += "-n8:16:32";
62 
63   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
64   if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
65     Ret += "-S32";
66   else
67     Ret += "-S128";
68 
69   return Ret;
70 }
71 
72 /// X86TargetMachine ctor - Create an X86 target.
73 ///
74 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
75                                    StringRef CPU, StringRef FS,
76                                    const TargetOptions &Options,
77                                    Reloc::Model RM, CodeModel::Model CM,
78                                    CodeGenOpt::Level OL)
79   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
80     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
81     FrameLowering(*this, Subtarget),
82     InstrItins(Subtarget.getInstrItineraryData()),
83     DL(computeDataLayout(*getSubtargetImpl())),
84     InstrInfo(*this),
85     TLInfo(*this),
86     TSInfo(*this),
87     JITInfo(*this) {
88   // Determine the PICStyle based on the target selected.
89   if (getRelocationModel() == Reloc::Static) {
90     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
91     Subtarget.setPICStyle(PICStyles::None);
92   } else if (Subtarget.is64Bit()) {
93     // PIC in 64 bit mode is always rip-rel.
94     Subtarget.setPICStyle(PICStyles::RIPRel);
95   } else if (Subtarget.isTargetCOFF()) {
96     Subtarget.setPICStyle(PICStyles::None);
97   } else if (Subtarget.isTargetDarwin()) {
98     if (getRelocationModel() == Reloc::PIC_)
99       Subtarget.setPICStyle(PICStyles::StubPIC);
100     else {
101       assert(getRelocationModel() == Reloc::DynamicNoPIC);
102       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
103     }
104   } else if (Subtarget.isTargetELF()) {
105     Subtarget.setPICStyle(PICStyles::GOT);
106   }
107 
108   // default to hard float ABI
109   if (Options.FloatABIType == FloatABI::Default)
110     this->Options.FloatABIType = FloatABI::Hard;
111 
112   initAsmInfo();
113 }
114 
115 //===----------------------------------------------------------------------===//
116 // Command line options for x86
117 //===----------------------------------------------------------------------===//
118 static cl::opt<bool>
119 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
120   cl::desc("Minimize AVX to SSE transition penalty"),
121   cl::init(true));
122 
123 // Temporary option to control early if-conversion for x86 while adding machine
124 // models.
125 static cl::opt<bool>
126 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
127 	       cl::desc("Enable early if-conversion on X86"));
128 
129 //===----------------------------------------------------------------------===//
130 // X86 Analysis Pass Setup
131 //===----------------------------------------------------------------------===//
132 
133 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
134   // Add first the target-independent BasicTTI pass, then our X86 pass. This
135   // allows the X86 pass to delegate to the target independent layer when
136   // appropriate.
137   PM.add(createBasicTargetTransformInfoPass(this));
138   PM.add(createX86TargetTransformInfoPass(this));
139 }
140 
141 
142 //===----------------------------------------------------------------------===//
143 // Pass Pipeline Configuration
144 //===----------------------------------------------------------------------===//
145 
146 namespace {
147 /// X86 Code Generator Pass Configuration Options.
148 class X86PassConfig : public TargetPassConfig {
149 public:
150   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
151     : TargetPassConfig(TM, PM) {}
152 
153   X86TargetMachine &getX86TargetMachine() const {
154     return getTM<X86TargetMachine>();
155   }
156 
157   const X86Subtarget &getX86Subtarget() const {
158     return *getX86TargetMachine().getSubtargetImpl();
159   }
160 
161   virtual bool addInstSelector();
162   virtual bool addILPOpts();
163   virtual bool addPreRegAlloc();
164   virtual bool addPostRegAlloc();
165   virtual bool addPreEmitPass();
166 };
167 } // namespace
168 
169 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
170   return new X86PassConfig(this, PM);
171 }
172 
173 bool X86PassConfig::addInstSelector() {
174   // Install an instruction selector.
175   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
176 
177   // For ELF, cleanup any local-dynamic TLS accesses.
178   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
179     addPass(createCleanupLocalDynamicTLSPass());
180 
181   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
182   if (!getX86Subtarget().is64Bit())
183     addPass(createGlobalBaseRegPass());
184 
185   return false;
186 }
187 
188 bool X86PassConfig::addILPOpts() {
189   if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
190     addPass(&EarlyIfConverterID);
191     return true;
192   }
193   return false;
194 }
195 
196 bool X86PassConfig::addPreRegAlloc() {
197   return false;  // -print-machineinstr shouldn't print after this.
198 }
199 
200 bool X86PassConfig::addPostRegAlloc() {
201   addPass(createX86FloatingPointStackifierPass());
202   return true;  // -print-machineinstr should print after this.
203 }
204 
205 bool X86PassConfig::addPreEmitPass() {
206   bool ShouldPrint = false;
207   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
208     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
209     ShouldPrint = true;
210   }
211 
212   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
213     addPass(createX86IssueVZeroUpperPass());
214     ShouldPrint = true;
215   }
216 
217   if (getOptLevel() != CodeGenOpt::None &&
218       getX86Subtarget().padShortFunctions()) {
219     addPass(createX86PadShortFunctions());
220     ShouldPrint = true;
221   }
222   if (getOptLevel() != CodeGenOpt::None &&
223       getX86Subtarget().LEAusesAG()){
224     addPass(createX86FixupLEAs());
225     ShouldPrint = true;
226   }
227 
228   return ShouldPrint;
229 }
230 
231 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
232                                       JITCodeEmitter &JCE) {
233   PM.add(createX86JITCodeEmitterPass(*this, JCE));
234 
235   return false;
236 }
237