1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 using namespace llvm;
27 
28 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
29                                cl::desc("Enable the machine combiner pass"),
30                                cl::init(true), cl::Hidden);
31 
32 namespace llvm {
33 void initializeWinEHStatePassPass(PassRegistry &);
34 }
35 
36 extern "C" void LLVMInitializeX86Target() {
37   // Register the target.
38   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
39   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
40 
41   PassRegistry &PR = *PassRegistry::getPassRegistry();
42   initializeWinEHStatePassPass(PR);
43   initializeFixupBWInstPassPass(PR);
44 }
45 
46 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
47   if (TT.isOSBinFormatMachO()) {
48     if (TT.getArch() == Triple::x86_64)
49       return make_unique<X86_64MachoTargetObjectFile>();
50     return make_unique<TargetLoweringObjectFileMachO>();
51   }
52 
53   if (TT.isOSFreeBSD())
54     return make_unique<X86FreeBSDTargetObjectFile>();
55   if (TT.isOSLinux() || TT.isOSNaCl())
56     return make_unique<X86LinuxNaClTargetObjectFile>();
57   if (TT.isOSFuchsia())
58     return make_unique<X86FuchsiaTargetObjectFile>();
59   if (TT.isOSBinFormatELF())
60     return make_unique<X86ELFTargetObjectFile>();
61   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
62     return make_unique<X86WindowsTargetObjectFile>();
63   if (TT.isOSBinFormatCOFF())
64     return make_unique<TargetLoweringObjectFileCOFF>();
65   llvm_unreachable("unknown subtarget type");
66 }
67 
68 static std::string computeDataLayout(const Triple &TT) {
69   // X86 is little endian
70   std::string Ret = "e";
71 
72   Ret += DataLayout::getManglingComponent(TT);
73   // X86 and x32 have 32 bit pointers.
74   if ((TT.isArch64Bit() &&
75        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
76       !TT.isArch64Bit())
77     Ret += "-p:32:32";
78 
79   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
80   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
81     Ret += "-i64:64";
82   else if (TT.isOSIAMCU())
83     Ret += "-i64:32-f64:32";
84   else
85     Ret += "-f64:32:64";
86 
87   // Some ABIs align long double to 128 bits, others to 32.
88   if (TT.isOSNaCl() || TT.isOSIAMCU())
89     ; // No f80
90   else if (TT.isArch64Bit() || TT.isOSDarwin())
91     Ret += "-f80:128";
92   else
93     Ret += "-f80:32";
94 
95   if (TT.isOSIAMCU())
96     Ret += "-f128:32";
97 
98   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
99   if (TT.isArch64Bit())
100     Ret += "-n8:16:32:64";
101   else
102     Ret += "-n8:16:32";
103 
104   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
105   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
106     Ret += "-a:0:32-S32";
107   else
108     Ret += "-S128";
109 
110   return Ret;
111 }
112 
113 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
114                                            Optional<Reloc::Model> RM) {
115   bool is64Bit = TT.getArch() == Triple::x86_64;
116   if (!RM.hasValue()) {
117     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
118     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
119     // use static relocation model by default.
120     if (TT.isOSDarwin()) {
121       if (is64Bit)
122         return Reloc::PIC_;
123       return Reloc::DynamicNoPIC;
124     }
125     if (TT.isOSWindows() && is64Bit)
126       return Reloc::PIC_;
127     return Reloc::Static;
128   }
129 
130   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
131   // is defined as a model for code which may be used in static or dynamic
132   // executables but not necessarily a shared library. On X86-32 we just
133   // compile in -static mode, in x86-64 we use PIC.
134   if (*RM == Reloc::DynamicNoPIC) {
135     if (is64Bit)
136       return Reloc::PIC_;
137     if (!TT.isOSDarwin())
138       return Reloc::Static;
139   }
140 
141   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
142   // the Mach-O file format doesn't support it.
143   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
144     return Reloc::PIC_;
145 
146   return *RM;
147 }
148 
149 /// Create an X86 target.
150 ///
151 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
152                                    StringRef CPU, StringRef FS,
153                                    const TargetOptions &Options,
154                                    Optional<Reloc::Model> RM,
155                                    CodeModel::Model CM, CodeGenOpt::Level OL)
156     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
157                         getEffectiveRelocModel(TT, RM), CM, OL),
158       TLOF(createTLOF(getTargetTriple())) {
159   // Windows stack unwinder gets confused when execution flow "falls through"
160   // after a call to 'noreturn' function.
161   // To prevent that, we emit a trap for 'unreachable' IR instructions.
162   // (which on X86, happens to be the 'ud2' instruction)
163   // On PS4, the "return address" of a 'noreturn' call must still be within
164   // the calling function, and TrapUnreachable is an easy way to get that.
165   // The check here for 64-bit windows is a bit icky, but as we're unlikely
166   // to ever want to mix 32 and 64-bit windows code in a single module
167   // this should be fine.
168   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
169     this->Options.TrapUnreachable = true;
170 
171   initAsmInfo();
172 }
173 
174 X86TargetMachine::~X86TargetMachine() {}
175 
176 const X86Subtarget *
177 X86TargetMachine::getSubtargetImpl(const Function &F) const {
178   Attribute CPUAttr = F.getFnAttribute("target-cpu");
179   Attribute FSAttr = F.getFnAttribute("target-features");
180 
181   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
182                       ? CPUAttr.getValueAsString()
183                       : (StringRef)TargetCPU;
184   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
185                      ? FSAttr.getValueAsString()
186                      : (StringRef)TargetFS;
187 
188   SmallString<512> Key;
189   Key.reserve(CPU.size() + FS.size());
190   Key += CPU;
191   Key += FS;
192 
193   // FIXME: This is related to the code below to reset the target options,
194   // we need to know whether or not the soft float flag is set on the
195   // function before we can generate a subtarget. We also need to use
196   // it as a key for the subtarget since that can be the only difference
197   // between two functions.
198   bool SoftFloat =
199       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
200   // If the soft float attribute is set on the function turn on the soft float
201   // subtarget feature.
202   if (SoftFloat)
203     Key += FS.empty() ? "+soft-float" : ",+soft-float";
204 
205   FS = Key.substr(CPU.size());
206 
207   auto &I = SubtargetMap[Key];
208   if (!I) {
209     // This needs to be done before we create a new subtarget since any
210     // creation will depend on the TM and the code generation flags on the
211     // function that reside in TargetOptions.
212     resetTargetOptions(F);
213     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
214                                         Options.StackAlignmentOverride);
215   }
216   return I.get();
217 }
218 
219 //===----------------------------------------------------------------------===//
220 // Command line options for x86
221 //===----------------------------------------------------------------------===//
222 static cl::opt<bool>
223 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
224   cl::desc("Minimize AVX to SSE transition penalty"),
225   cl::init(true));
226 
227 //===----------------------------------------------------------------------===//
228 // X86 TTI query.
229 //===----------------------------------------------------------------------===//
230 
231 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
232   return TargetIRAnalysis([this](const Function &F) {
233     return TargetTransformInfo(X86TTIImpl(this, F));
234   });
235 }
236 
237 
238 //===----------------------------------------------------------------------===//
239 // Pass Pipeline Configuration
240 //===----------------------------------------------------------------------===//
241 
242 namespace {
243 /// X86 Code Generator Pass Configuration Options.
244 class X86PassConfig : public TargetPassConfig {
245 public:
246   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
247     : TargetPassConfig(TM, PM) {}
248 
249   X86TargetMachine &getX86TargetMachine() const {
250     return getTM<X86TargetMachine>();
251   }
252 
253   void addIRPasses() override;
254   bool addInstSelector() override;
255   bool addILPOpts() override;
256   bool addPreISel() override;
257   void addPreRegAlloc() override;
258   void addPostRegAlloc() override;
259   void addPreEmitPass() override;
260   void addPreSched2() override;
261 };
262 } // namespace
263 
264 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
265   return new X86PassConfig(this, PM);
266 }
267 
268 void X86PassConfig::addIRPasses() {
269   addPass(createAtomicExpandPass(&getX86TargetMachine()));
270 
271   TargetPassConfig::addIRPasses();
272 }
273 
274 bool X86PassConfig::addInstSelector() {
275   // Install an instruction selector.
276   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
277 
278   // For ELF, cleanup any local-dynamic TLS accesses.
279   if (TM->getTargetTriple().isOSBinFormatELF() &&
280       getOptLevel() != CodeGenOpt::None)
281     addPass(createCleanupLocalDynamicTLSPass());
282 
283   addPass(createX86GlobalBaseRegPass());
284   return false;
285 }
286 
287 bool X86PassConfig::addILPOpts() {
288   addPass(&EarlyIfConverterID);
289   if (EnableMachineCombinerPass)
290     addPass(&MachineCombinerID);
291   return true;
292 }
293 
294 bool X86PassConfig::addPreISel() {
295   // Only add this pass for 32-bit x86 Windows.
296   const Triple &TT = TM->getTargetTriple();
297   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
298     addPass(createX86WinEHStatePass());
299   return true;
300 }
301 
302 void X86PassConfig::addPreRegAlloc() {
303   if (getOptLevel() != CodeGenOpt::None) {
304     addPass(createX86FixupSetCC());
305     addPass(createX86OptimizeLEAs());
306     addPass(createX86CallFrameOptimization());
307   }
308 
309   addPass(createX86WinAllocaExpander());
310 }
311 
312 void X86PassConfig::addPostRegAlloc() {
313   addPass(createX86FloatingPointStackifierPass());
314 }
315 
316 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
317 
318 void X86PassConfig::addPreEmitPass() {
319   if (getOptLevel() != CodeGenOpt::None)
320     addPass(createExecutionDependencyFixPass(&X86::VR128XRegClass));
321 
322   if (UseVZeroUpper)
323     addPass(createX86IssueVZeroUpperPass());
324 
325   if (getOptLevel() != CodeGenOpt::None) {
326     addPass(createX86FixupBWInsts());
327     addPass(createX86PadShortFunctions());
328     addPass(createX86FixupLEAs());
329   }
330 }
331