1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "MCTargetDesc/X86MCTargetDesc.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54                                cl::desc("Enable the machine combiner pass"),
55                                cl::init(true), cl::Hidden);
56 
57 namespace llvm {
58 
59 void initializeWinEHStatePassPass(PassRegistry &);
60 void initializeFixupLEAPassPass(PassRegistry &);
61 void initializeShadowCallStackPass(PassRegistry &);
62 void initializeX86CallFrameOptimizationPass(PassRegistry &);
63 void initializeX86CmovConverterPassPass(PassRegistry &);
64 void initializeX86ExecutionDomainFixPass(PassRegistry &);
65 void initializeX86DomainReassignmentPass(PassRegistry &);
66 void initializeX86AvoidSFBPassPass(PassRegistry &);
67 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
68 
69 } // end namespace llvm
70 
71 extern "C" void LLVMInitializeX86Target() {
72   // Register the target.
73   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
74   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
75 
76   PassRegistry &PR = *PassRegistry::getPassRegistry();
77   initializeGlobalISel(PR);
78   initializeWinEHStatePassPass(PR);
79   initializeFixupBWInstPassPass(PR);
80   initializeEvexToVexInstPassPass(PR);
81   initializeFixupLEAPassPass(PR);
82   initializeShadowCallStackPass(PR);
83   initializeX86CallFrameOptimizationPass(PR);
84   initializeX86CmovConverterPassPass(PR);
85   initializeX86ExecutionDomainFixPass(PR);
86   initializeX86DomainReassignmentPass(PR);
87   initializeX86AvoidSFBPassPass(PR);
88   initializeX86FlagsCopyLoweringPassPass(PR);
89 }
90 
91 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
92   if (TT.isOSBinFormatMachO()) {
93     if (TT.getArch() == Triple::x86_64)
94       return llvm::make_unique<X86_64MachoTargetObjectFile>();
95     return llvm::make_unique<TargetLoweringObjectFileMachO>();
96   }
97 
98   if (TT.isOSFreeBSD())
99     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
100   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
101     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
102   if (TT.isOSSolaris())
103     return llvm::make_unique<X86SolarisTargetObjectFile>();
104   if (TT.isOSFuchsia())
105     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
106   if (TT.isOSBinFormatELF())
107     return llvm::make_unique<X86ELFTargetObjectFile>();
108   if (TT.isOSBinFormatCOFF())
109     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
110   llvm_unreachable("unknown subtarget type");
111 }
112 
113 static std::string computeDataLayout(const Triple &TT) {
114   // X86 is little endian
115   std::string Ret = "e";
116 
117   Ret += DataLayout::getManglingComponent(TT);
118   // X86 and x32 have 32 bit pointers.
119   if ((TT.isArch64Bit() &&
120        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
121       !TT.isArch64Bit())
122     Ret += "-p:32:32";
123 
124   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
125   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
126     Ret += "-i64:64";
127   else if (TT.isOSIAMCU())
128     Ret += "-i64:32-f64:32";
129   else
130     Ret += "-f64:32:64";
131 
132   // Some ABIs align long double to 128 bits, others to 32.
133   if (TT.isOSNaCl() || TT.isOSIAMCU())
134     ; // No f80
135   else if (TT.isArch64Bit() || TT.isOSDarwin())
136     Ret += "-f80:128";
137   else
138     Ret += "-f80:32";
139 
140   if (TT.isOSIAMCU())
141     Ret += "-f128:32";
142 
143   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
144   if (TT.isArch64Bit())
145     Ret += "-n8:16:32:64";
146   else
147     Ret += "-n8:16:32";
148 
149   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
150   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
151     Ret += "-a:0:32-S32";
152   else
153     Ret += "-S128";
154 
155   return Ret;
156 }
157 
158 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
159                                            bool JIT,
160                                            Optional<Reloc::Model> RM) {
161   bool is64Bit = TT.getArch() == Triple::x86_64;
162   if (!RM.hasValue()) {
163     // JIT codegen should use static relocations by default, since it's
164     // typically executed in process and not relocatable.
165     if (JIT)
166       return Reloc::Static;
167 
168     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
169     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
170     // use static relocation model by default.
171     if (TT.isOSDarwin()) {
172       if (is64Bit)
173         return Reloc::PIC_;
174       return Reloc::DynamicNoPIC;
175     }
176     if (TT.isOSWindows() && is64Bit)
177       return Reloc::PIC_;
178     return Reloc::Static;
179   }
180 
181   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
182   // is defined as a model for code which may be used in static or dynamic
183   // executables but not necessarily a shared library. On X86-32 we just
184   // compile in -static mode, in x86-64 we use PIC.
185   if (*RM == Reloc::DynamicNoPIC) {
186     if (is64Bit)
187       return Reloc::PIC_;
188     if (!TT.isOSDarwin())
189       return Reloc::Static;
190   }
191 
192   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
193   // the Mach-O file format doesn't support it.
194   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
195     return Reloc::PIC_;
196 
197   return *RM;
198 }
199 
200 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
201                                               bool JIT, bool Is64Bit) {
202   if (CM)
203     return *CM;
204   if (JIT)
205     return Is64Bit ? CodeModel::Large : CodeModel::Small;
206   return CodeModel::Small;
207 }
208 
209 /// Create an X86 target.
210 ///
211 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
212                                    StringRef CPU, StringRef FS,
213                                    const TargetOptions &Options,
214                                    Optional<Reloc::Model> RM,
215                                    Optional<CodeModel::Model> CM,
216                                    CodeGenOpt::Level OL, bool JIT)
217     : LLVMTargetMachine(
218           T, computeDataLayout(TT), TT, CPU, FS, Options,
219           getEffectiveRelocModel(TT, JIT, RM),
220           getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
221       TLOF(createTLOF(getTargetTriple())) {
222   // Windows stack unwinder gets confused when execution flow "falls through"
223   // after a call to 'noreturn' function.
224   // To prevent that, we emit a trap for 'unreachable' IR instructions.
225   // (which on X86, happens to be the 'ud2' instruction)
226   // On PS4, the "return address" of a 'noreturn' call must still be within
227   // the calling function, and TrapUnreachable is an easy way to get that.
228   // The check here for 64-bit windows is a bit icky, but as we're unlikely
229   // to ever want to mix 32 and 64-bit windows code in a single module
230   // this should be fine.
231   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
232       TT.isOSBinFormatMachO())
233     this->Options.TrapUnreachable = true;
234 
235   initAsmInfo();
236 }
237 
238 X86TargetMachine::~X86TargetMachine() = default;
239 
240 const X86Subtarget *
241 X86TargetMachine::getSubtargetImpl(const Function &F) const {
242   Attribute CPUAttr = F.getFnAttribute("target-cpu");
243   Attribute FSAttr = F.getFnAttribute("target-features");
244 
245   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
246                       ? CPUAttr.getValueAsString()
247                       : (StringRef)TargetCPU;
248   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
249                      ? FSAttr.getValueAsString()
250                      : (StringRef)TargetFS;
251 
252   SmallString<512> Key;
253   Key.reserve(CPU.size() + FS.size());
254   Key += CPU;
255   Key += FS;
256 
257   // FIXME: This is related to the code below to reset the target options,
258   // we need to know whether or not the soft float flag is set on the
259   // function before we can generate a subtarget. We also need to use
260   // it as a key for the subtarget since that can be the only difference
261   // between two functions.
262   bool SoftFloat =
263       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
264   // If the soft float attribute is set on the function turn on the soft float
265   // subtarget feature.
266   if (SoftFloat)
267     Key += FS.empty() ? "+soft-float" : ",+soft-float";
268 
269   // Keep track of the key width after all features are added so we can extract
270   // the feature string out later.
271   unsigned CPUFSWidth = Key.size();
272 
273   // Extract prefer-vector-width attribute.
274   unsigned PreferVectorWidthOverride = 0;
275   if (F.hasFnAttribute("prefer-vector-width")) {
276     StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
277     unsigned Width;
278     if (!Val.getAsInteger(0, Width)) {
279       Key += ",prefer-vector-width=";
280       Key += Val;
281       PreferVectorWidthOverride = Width;
282     }
283   }
284 
285   // Extract required-vector-width attribute.
286   unsigned RequiredVectorWidth = UINT32_MAX;
287   if (F.hasFnAttribute("required-vector-width")) {
288     StringRef Val = F.getFnAttribute("required-vector-width").getValueAsString();
289     unsigned Width;
290     if (!Val.getAsInteger(0, Width)) {
291       Key += ",required-vector-width=";
292       Key += Val;
293       RequiredVectorWidth = Width;
294     }
295   }
296 
297   // Extracted here so that we make sure there is backing for the StringRef. If
298   // we assigned earlier, its possible the SmallString reallocated leaving a
299   // dangling StringRef.
300   FS = Key.slice(CPU.size(), CPUFSWidth);
301 
302   auto &I = SubtargetMap[Key];
303   if (!I) {
304     // This needs to be done before we create a new subtarget since any
305     // creation will depend on the TM and the code generation flags on the
306     // function that reside in TargetOptions.
307     resetTargetOptions(F);
308     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
309                                         Options.StackAlignmentOverride,
310                                         PreferVectorWidthOverride,
311                                         RequiredVectorWidth);
312   }
313   return I.get();
314 }
315 
316 //===----------------------------------------------------------------------===//
317 // Command line options for x86
318 //===----------------------------------------------------------------------===//
319 static cl::opt<bool>
320 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
321   cl::desc("Minimize AVX to SSE transition penalty"),
322   cl::init(true));
323 
324 //===----------------------------------------------------------------------===//
325 // X86 TTI query.
326 //===----------------------------------------------------------------------===//
327 
328 TargetTransformInfo
329 X86TargetMachine::getTargetTransformInfo(const Function &F) {
330   return TargetTransformInfo(X86TTIImpl(this, F));
331 }
332 
333 //===----------------------------------------------------------------------===//
334 // Pass Pipeline Configuration
335 //===----------------------------------------------------------------------===//
336 
337 namespace {
338 
339 /// X86 Code Generator Pass Configuration Options.
340 class X86PassConfig : public TargetPassConfig {
341 public:
342   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
343     : TargetPassConfig(TM, PM) {}
344 
345   X86TargetMachine &getX86TargetMachine() const {
346     return getTM<X86TargetMachine>();
347   }
348 
349   ScheduleDAGInstrs *
350   createMachineScheduler(MachineSchedContext *C) const override {
351     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
352     DAG->addMutation(createX86MacroFusionDAGMutation());
353     return DAG;
354   }
355 
356   void addIRPasses() override;
357   bool addInstSelector() override;
358   bool addIRTranslator() override;
359   bool addLegalizeMachineIR() override;
360   bool addRegBankSelect() override;
361   bool addGlobalInstructionSelect() override;
362   bool addILPOpts() override;
363   bool addPreISel() override;
364   void addMachineSSAOptimization() override;
365   void addPreRegAlloc() override;
366   void addPostRegAlloc() override;
367   void addPreEmitPass() override;
368   void addPreEmitPass2() override;
369   void addPreSched2() override;
370 };
371 
372 class X86ExecutionDomainFix : public ExecutionDomainFix {
373 public:
374   static char ID;
375   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
376   StringRef getPassName() const override {
377     return "X86 Execution Dependency Fix";
378   }
379 };
380 char X86ExecutionDomainFix::ID;
381 
382 } // end anonymous namespace
383 
384 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
385   "X86 Execution Domain Fix", false, false)
386 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
387 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
388   "X86 Execution Domain Fix", false, false)
389 
390 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
391   return new X86PassConfig(*this, PM);
392 }
393 
394 void X86PassConfig::addIRPasses() {
395   addPass(createAtomicExpandPass());
396 
397   TargetPassConfig::addIRPasses();
398 
399   if (TM->getOptLevel() != CodeGenOpt::None)
400     addPass(createInterleavedAccessPass());
401 
402   // Add passes that handle indirect branch removal and insertion of a retpoline
403   // thunk. These will be a no-op unless a function subtarget has the retpoline
404   // feature enabled.
405   addPass(createIndirectBrExpandPass());
406 }
407 
408 bool X86PassConfig::addInstSelector() {
409   // Install an instruction selector.
410   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
411 
412   // For ELF, cleanup any local-dynamic TLS accesses.
413   if (TM->getTargetTriple().isOSBinFormatELF() &&
414       getOptLevel() != CodeGenOpt::None)
415     addPass(createCleanupLocalDynamicTLSPass());
416 
417   addPass(createX86GlobalBaseRegPass());
418   return false;
419 }
420 
421 bool X86PassConfig::addIRTranslator() {
422   addPass(new IRTranslator());
423   return false;
424 }
425 
426 bool X86PassConfig::addLegalizeMachineIR() {
427   addPass(new Legalizer());
428   return false;
429 }
430 
431 bool X86PassConfig::addRegBankSelect() {
432   addPass(new RegBankSelect());
433   return false;
434 }
435 
436 bool X86PassConfig::addGlobalInstructionSelect() {
437   addPass(new InstructionSelect());
438   return false;
439 }
440 
441 bool X86PassConfig::addILPOpts() {
442   addPass(&EarlyIfConverterID);
443   if (EnableMachineCombinerPass)
444     addPass(&MachineCombinerID);
445   addPass(createX86CmovConverterPass());
446   return true;
447 }
448 
449 bool X86PassConfig::addPreISel() {
450   // Only add this pass for 32-bit x86 Windows.
451   const Triple &TT = TM->getTargetTriple();
452   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
453     addPass(createX86WinEHStatePass());
454   return true;
455 }
456 
457 void X86PassConfig::addPreRegAlloc() {
458   if (getOptLevel() != CodeGenOpt::None) {
459     addPass(&LiveRangeShrinkID);
460     addPass(createX86FixupSetCC());
461     addPass(createX86OptimizeLEAs());
462     addPass(createX86CallFrameOptimization());
463     addPass(createX86AvoidStoreForwardingBlocks());
464   }
465 
466   addPass(createX86FlagsCopyLoweringPass());
467   addPass(createX86WinAllocaExpander());
468 }
469 void X86PassConfig::addMachineSSAOptimization() {
470   addPass(createX86DomainReassignmentPass());
471   TargetPassConfig::addMachineSSAOptimization();
472 }
473 
474 void X86PassConfig::addPostRegAlloc() {
475   addPass(createX86FloatingPointStackifierPass());
476 }
477 
478 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
479 
480 void X86PassConfig::addPreEmitPass() {
481   if (getOptLevel() != CodeGenOpt::None) {
482     addPass(new X86ExecutionDomainFix());
483     addPass(createBreakFalseDeps());
484   }
485 
486   addPass(createShadowCallStackPass());
487   addPass(createX86IndirectBranchTrackingPass());
488 
489   if (UseVZeroUpper)
490     addPass(createX86IssueVZeroUpperPass());
491 
492   if (getOptLevel() != CodeGenOpt::None) {
493     addPass(createX86FixupBWInsts());
494     addPass(createX86PadShortFunctions());
495     addPass(createX86FixupLEAs());
496     addPass(createX86EvexToVexInsts());
497   }
498 }
499 
500 void X86PassConfig::addPreEmitPass2() {
501   addPass(createX86RetpolineThunksPass());
502   // Verify basic block incoming and outgoing cfa offset and register values and
503   // correct CFA calculation rule where needed by inserting appropriate CFI
504   // instructions.
505   const Triple &TT = TM->getTargetTriple();
506   if (!TT.isOSDarwin() && !TT.isOSWindows())
507     addPass(createCFIInstrInserter());
508 }
509