1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86InstructionSelector.h"
19 #ifdef LLVM_BUILD_GLOBAL_ISEL
20 #include "X86RegisterBankInfo.h"
21 #endif
22 #include "X86MacroFusion.h"
23 #include "X86Subtarget.h"
24 #include "X86TargetMachine.h"
25 #include "X86TargetObjectFile.h"
26 #include "X86TargetTransformInfo.h"
27 #include "llvm/ADT/Optional.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/ADT/Triple.h"
32 #include "llvm/Analysis/TargetTransformInfo.h"
33 #include "llvm/CodeGen/ExecutionDepsFix.h"
34 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
35 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
36 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
37 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
38 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
39 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
40 #include "llvm/CodeGen/MachineScheduler.h"
41 #include "llvm/CodeGen/Passes.h"
42 #include "llvm/CodeGen/TargetPassConfig.h"
43 #include "llvm/IR/Attributes.h"
44 #include "llvm/IR/DataLayout.h"
45 #include "llvm/IR/Function.h"
46 #include "llvm/Pass.h"
47 #include "llvm/Support/CodeGen.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/TargetRegistry.h"
51 #include "llvm/Target/TargetLoweringObjectFile.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include <memory>
54 #include <string>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
59                                cl::desc("Enable the machine combiner pass"),
60                                cl::init(true), cl::Hidden);
61 
62 namespace llvm {
63 
64 void initializeWinEHStatePassPass(PassRegistry &);
65 void initializeX86ExecutionDepsFixPass(PassRegistry &);
66 
67 } // end namespace llvm
68 
69 extern "C" void LLVMInitializeX86Target() {
70   // Register the target.
71   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
72   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
73 
74   PassRegistry &PR = *PassRegistry::getPassRegistry();
75   initializeGlobalISel(PR);
76   initializeWinEHStatePassPass(PR);
77   initializeFixupBWInstPassPass(PR);
78   initializeEvexToVexInstPassPass(PR);
79   initializeX86ExecutionDepsFixPass(PR);
80 }
81 
82 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
83   if (TT.isOSBinFormatMachO()) {
84     if (TT.getArch() == Triple::x86_64)
85       return llvm::make_unique<X86_64MachoTargetObjectFile>();
86     return llvm::make_unique<TargetLoweringObjectFileMachO>();
87   }
88 
89   if (TT.isOSFreeBSD())
90     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
91   if (TT.isOSLinux() || TT.isOSNaCl())
92     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
93   if (TT.isOSFuchsia())
94     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
95   if (TT.isOSBinFormatELF())
96     return llvm::make_unique<X86ELFTargetObjectFile>();
97   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
98     return llvm::make_unique<X86WindowsTargetObjectFile>();
99   if (TT.isOSBinFormatCOFF())
100     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
101   llvm_unreachable("unknown subtarget type");
102 }
103 
104 static std::string computeDataLayout(const Triple &TT) {
105   // X86 is little endian
106   std::string Ret = "e";
107 
108   Ret += DataLayout::getManglingComponent(TT);
109   // X86 and x32 have 32 bit pointers.
110   if ((TT.isArch64Bit() &&
111        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
112       !TT.isArch64Bit())
113     Ret += "-p:32:32";
114 
115   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
116   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
117     Ret += "-i64:64";
118   else if (TT.isOSIAMCU())
119     Ret += "-i64:32-f64:32";
120   else
121     Ret += "-f64:32:64";
122 
123   // Some ABIs align long double to 128 bits, others to 32.
124   if (TT.isOSNaCl() || TT.isOSIAMCU())
125     ; // No f80
126   else if (TT.isArch64Bit() || TT.isOSDarwin())
127     Ret += "-f80:128";
128   else
129     Ret += "-f80:32";
130 
131   if (TT.isOSIAMCU())
132     Ret += "-f128:32";
133 
134   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
135   if (TT.isArch64Bit())
136     Ret += "-n8:16:32:64";
137   else
138     Ret += "-n8:16:32";
139 
140   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
141   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
142     Ret += "-a:0:32-S32";
143   else
144     Ret += "-S128";
145 
146   return Ret;
147 }
148 
149 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
150                                            Optional<Reloc::Model> RM) {
151   bool is64Bit = TT.getArch() == Triple::x86_64;
152   if (!RM.hasValue()) {
153     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
154     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
155     // use static relocation model by default.
156     if (TT.isOSDarwin()) {
157       if (is64Bit)
158         return Reloc::PIC_;
159       return Reloc::DynamicNoPIC;
160     }
161     if (TT.isOSWindows() && is64Bit)
162       return Reloc::PIC_;
163     return Reloc::Static;
164   }
165 
166   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
167   // is defined as a model for code which may be used in static or dynamic
168   // executables but not necessarily a shared library. On X86-32 we just
169   // compile in -static mode, in x86-64 we use PIC.
170   if (*RM == Reloc::DynamicNoPIC) {
171     if (is64Bit)
172       return Reloc::PIC_;
173     if (!TT.isOSDarwin())
174       return Reloc::Static;
175   }
176 
177   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
178   // the Mach-O file format doesn't support it.
179   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
180     return Reloc::PIC_;
181 
182   return *RM;
183 }
184 
185 /// Create an X86 target.
186 ///
187 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
188                                    StringRef CPU, StringRef FS,
189                                    const TargetOptions &Options,
190                                    Optional<Reloc::Model> RM,
191                                    CodeModel::Model CM, CodeGenOpt::Level OL)
192     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
193                         getEffectiveRelocModel(TT, RM), CM, OL),
194       TLOF(createTLOF(getTargetTriple())) {
195   // Windows stack unwinder gets confused when execution flow "falls through"
196   // after a call to 'noreturn' function.
197   // To prevent that, we emit a trap for 'unreachable' IR instructions.
198   // (which on X86, happens to be the 'ud2' instruction)
199   // On PS4, the "return address" of a 'noreturn' call must still be within
200   // the calling function, and TrapUnreachable is an easy way to get that.
201   // The check here for 64-bit windows is a bit icky, but as we're unlikely
202   // to ever want to mix 32 and 64-bit windows code in a single module
203   // this should be fine.
204   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
205     this->Options.TrapUnreachable = true;
206 
207   initAsmInfo();
208 }
209 
210 X86TargetMachine::~X86TargetMachine() = default;
211 
212 #ifdef LLVM_BUILD_GLOBAL_ISEL
213 namespace {
214 
215 struct X86GISelActualAccessor : public GISelAccessor {
216   std::unique_ptr<CallLowering> CallLoweringInfo;
217   std::unique_ptr<LegalizerInfo> Legalizer;
218   std::unique_ptr<RegisterBankInfo> RegBankInfo;
219   std::unique_ptr<InstructionSelector> InstSelector;
220 
221   const CallLowering *getCallLowering() const override {
222     return CallLoweringInfo.get();
223   }
224 
225   const InstructionSelector *getInstructionSelector() const override {
226     return InstSelector.get();
227   }
228 
229   const LegalizerInfo *getLegalizerInfo() const override {
230     return Legalizer.get();
231   }
232 
233   const RegisterBankInfo *getRegBankInfo() const override {
234     return RegBankInfo.get();
235   }
236 };
237 
238 } // end anonymous namespace
239 #endif
240 
241 const X86Subtarget *
242 X86TargetMachine::getSubtargetImpl(const Function &F) const {
243   Attribute CPUAttr = F.getFnAttribute("target-cpu");
244   Attribute FSAttr = F.getFnAttribute("target-features");
245 
246   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
247                       ? CPUAttr.getValueAsString()
248                       : (StringRef)TargetCPU;
249   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
250                      ? FSAttr.getValueAsString()
251                      : (StringRef)TargetFS;
252 
253   SmallString<512> Key;
254   Key.reserve(CPU.size() + FS.size());
255   Key += CPU;
256   Key += FS;
257 
258   // FIXME: This is related to the code below to reset the target options,
259   // we need to know whether or not the soft float flag is set on the
260   // function before we can generate a subtarget. We also need to use
261   // it as a key for the subtarget since that can be the only difference
262   // between two functions.
263   bool SoftFloat =
264       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
265   // If the soft float attribute is set on the function turn on the soft float
266   // subtarget feature.
267   if (SoftFloat)
268     Key += FS.empty() ? "+soft-float" : ",+soft-float";
269 
270   FS = Key.substr(CPU.size());
271 
272   auto &I = SubtargetMap[Key];
273   if (!I) {
274     // This needs to be done before we create a new subtarget since any
275     // creation will depend on the TM and the code generation flags on the
276     // function that reside in TargetOptions.
277     resetTargetOptions(F);
278     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
279                                         Options.StackAlignmentOverride);
280 #ifndef LLVM_BUILD_GLOBAL_ISEL
281     GISelAccessor *GISel = new GISelAccessor();
282 #else
283     X86GISelActualAccessor *GISel = new X86GISelActualAccessor();
284 
285     GISel->CallLoweringInfo.reset(new X86CallLowering(*I->getTargetLowering()));
286     GISel->Legalizer.reset(new X86LegalizerInfo(*I));
287 
288     auto *RBI = new X86RegisterBankInfo(*I->getRegisterInfo());
289     GISel->RegBankInfo.reset(RBI);
290     GISel->InstSelector.reset(new X86InstructionSelector(*I, *RBI));
291 
292 #endif
293     I->setGISelAccessor(*GISel);
294   }
295   return I.get();
296 }
297 
298 //===----------------------------------------------------------------------===//
299 // Command line options for x86
300 //===----------------------------------------------------------------------===//
301 static cl::opt<bool>
302 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
303   cl::desc("Minimize AVX to SSE transition penalty"),
304   cl::init(true));
305 
306 //===----------------------------------------------------------------------===//
307 // X86 TTI query.
308 //===----------------------------------------------------------------------===//
309 
310 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
311   return TargetIRAnalysis([this](const Function &F) {
312     return TargetTransformInfo(X86TTIImpl(this, F));
313   });
314 }
315 
316 //===----------------------------------------------------------------------===//
317 // Pass Pipeline Configuration
318 //===----------------------------------------------------------------------===//
319 
320 namespace {
321 
322 /// X86 Code Generator Pass Configuration Options.
323 class X86PassConfig : public TargetPassConfig {
324 public:
325   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
326     : TargetPassConfig(TM, PM) {}
327 
328   X86TargetMachine &getX86TargetMachine() const {
329     return getTM<X86TargetMachine>();
330   }
331 
332   ScheduleDAGInstrs *
333   createMachineScheduler(MachineSchedContext *C) const override {
334     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
335     DAG->addMutation(createX86MacroFusionDAGMutation());
336     return DAG;
337   }
338 
339   void addIRPasses() override;
340   bool addInstSelector() override;
341 #ifdef LLVM_BUILD_GLOBAL_ISEL
342   bool addIRTranslator() override;
343   bool addLegalizeMachineIR() override;
344   bool addRegBankSelect() override;
345   bool addGlobalInstructionSelect() override;
346 #endif
347   bool addILPOpts() override;
348   bool addPreISel() override;
349   void addPreRegAlloc() override;
350   void addPostRegAlloc() override;
351   void addPreEmitPass() override;
352   void addPreSched2() override;
353 };
354 
355 class X86ExecutionDepsFix : public ExecutionDepsFix {
356 public:
357   static char ID;
358   X86ExecutionDepsFix() : ExecutionDepsFix(ID, X86::VR128XRegClass) {}
359   StringRef getPassName() const override {
360     return "X86 Execution Dependency Fix";
361   }
362 };
363 char X86ExecutionDepsFix::ID;
364 
365 } // end anonymous namespace
366 
367 INITIALIZE_PASS(X86ExecutionDepsFix, "x86-execution-deps-fix",
368                 "X86 Execution Dependency Fix", false, false)
369 
370 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
371   return new X86PassConfig(this, PM);
372 }
373 
374 void X86PassConfig::addIRPasses() {
375   addPass(createAtomicExpandPass(&getX86TargetMachine()));
376 
377   TargetPassConfig::addIRPasses();
378 
379   if (TM->getOptLevel() != CodeGenOpt::None)
380     addPass(createInterleavedAccessPass(TM));
381 }
382 
383 bool X86PassConfig::addInstSelector() {
384   // Install an instruction selector.
385   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
386 
387   // For ELF, cleanup any local-dynamic TLS accesses.
388   if (TM->getTargetTriple().isOSBinFormatELF() &&
389       getOptLevel() != CodeGenOpt::None)
390     addPass(createCleanupLocalDynamicTLSPass());
391 
392   addPass(createX86GlobalBaseRegPass());
393   return false;
394 }
395 
396 #ifdef LLVM_BUILD_GLOBAL_ISEL
397 bool X86PassConfig::addIRTranslator() {
398   addPass(new IRTranslator());
399   return false;
400 }
401 
402 bool X86PassConfig::addLegalizeMachineIR() {
403   addPass(new Legalizer());
404   return false;
405 }
406 
407 bool X86PassConfig::addRegBankSelect() {
408   addPass(new RegBankSelect());
409   return false;
410 }
411 
412 bool X86PassConfig::addGlobalInstructionSelect() {
413   addPass(new InstructionSelect());
414   return false;
415 }
416 #endif
417 
418 bool X86PassConfig::addILPOpts() {
419   addPass(&EarlyIfConverterID);
420   if (EnableMachineCombinerPass)
421     addPass(&MachineCombinerID);
422   return true;
423 }
424 
425 bool X86PassConfig::addPreISel() {
426   // Only add this pass for 32-bit x86 Windows.
427   const Triple &TT = TM->getTargetTriple();
428   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
429     addPass(createX86WinEHStatePass());
430   return true;
431 }
432 
433 void X86PassConfig::addPreRegAlloc() {
434   if (getOptLevel() != CodeGenOpt::None) {
435     addPass(createX86FixupSetCC());
436     addPass(createX86OptimizeLEAs());
437     addPass(createX86CallFrameOptimization());
438   }
439 
440   addPass(createX86WinAllocaExpander());
441 }
442 
443 void X86PassConfig::addPostRegAlloc() {
444   addPass(createX86FloatingPointStackifierPass());
445 }
446 
447 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
448 
449 void X86PassConfig::addPreEmitPass() {
450   if (getOptLevel() != CodeGenOpt::None)
451     addPass(new X86ExecutionDepsFix());
452 
453   if (UseVZeroUpper)
454     addPass(createX86IssueVZeroUpperPass());
455 
456   if (getOptLevel() != CodeGenOpt::None) {
457     addPass(createX86FixupBWInsts());
458     addPass(createX86PadShortFunctions());
459     addPass(createX86FixupLEAs());
460     addPass(createX86EvexToVexInsts());
461   }
462 }
463