1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #ifdef LLVM_BUILD_GLOBAL_ISEL
19 #include "X86RegisterBankInfo.h"
20 #endif
21 #include "X86MacroFusion.h"
22 #include "X86Subtarget.h"
23 #include "X86TargetMachine.h"
24 #include "X86TargetObjectFile.h"
25 #include "X86TargetTransformInfo.h"
26 #include "llvm/ADT/Optional.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/Analysis/TargetTransformInfo.h"
32 #include "llvm/CodeGen/ExecutionDepsFix.h"
33 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
34 #include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
35 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
36 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
37 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
38 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
39 #include "llvm/CodeGen/MachineScheduler.h"
40 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/CodeGen/TargetPassConfig.h"
42 #include "llvm/IR/Attributes.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Target/TargetLoweringObjectFile.h"
51 #include "llvm/Target/TargetOptions.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58                                cl::desc("Enable the machine combiner pass"),
59                                cl::init(true), cl::Hidden);
60 
61 namespace llvm {
62 
63 void initializeWinEHStatePassPass(PassRegistry &);
64 void initializeFixupLEAPassPass(PassRegistry &);
65 void initializeX86ExecutionDepsFixPass(PassRegistry &);
66 
67 } // end namespace llvm
68 
69 extern "C" void LLVMInitializeX86Target() {
70   // Register the target.
71   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
72   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
73 
74   PassRegistry &PR = *PassRegistry::getPassRegistry();
75   initializeGlobalISel(PR);
76   initializeWinEHStatePassPass(PR);
77   initializeFixupBWInstPassPass(PR);
78   initializeEvexToVexInstPassPass(PR);
79   initializeFixupLEAPassPass(PR);
80   initializeX86ExecutionDepsFixPass(PR);
81 }
82 
83 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
84   if (TT.isOSBinFormatMachO()) {
85     if (TT.getArch() == Triple::x86_64)
86       return llvm::make_unique<X86_64MachoTargetObjectFile>();
87     return llvm::make_unique<TargetLoweringObjectFileMachO>();
88   }
89 
90   if (TT.isOSFreeBSD())
91     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
92   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
93     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
94   if (TT.isOSSolaris())
95     return llvm::make_unique<X86SolarisTargetObjectFile>();
96   if (TT.isOSFuchsia())
97     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
98   if (TT.isOSBinFormatELF())
99     return llvm::make_unique<X86ELFTargetObjectFile>();
100   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
101     return llvm::make_unique<X86WindowsTargetObjectFile>();
102   if (TT.isOSBinFormatCOFF())
103     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
104   llvm_unreachable("unknown subtarget type");
105 }
106 
107 static std::string computeDataLayout(const Triple &TT) {
108   // X86 is little endian
109   std::string Ret = "e";
110 
111   Ret += DataLayout::getManglingComponent(TT);
112   // X86 and x32 have 32 bit pointers.
113   if ((TT.isArch64Bit() &&
114        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
115       !TT.isArch64Bit())
116     Ret += "-p:32:32";
117 
118   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
119   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
120     Ret += "-i64:64";
121   else if (TT.isOSIAMCU())
122     Ret += "-i64:32-f64:32";
123   else
124     Ret += "-f64:32:64";
125 
126   // Some ABIs align long double to 128 bits, others to 32.
127   if (TT.isOSNaCl() || TT.isOSIAMCU())
128     ; // No f80
129   else if (TT.isArch64Bit() || TT.isOSDarwin())
130     Ret += "-f80:128";
131   else
132     Ret += "-f80:32";
133 
134   if (TT.isOSIAMCU())
135     Ret += "-f128:32";
136 
137   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
138   if (TT.isArch64Bit())
139     Ret += "-n8:16:32:64";
140   else
141     Ret += "-n8:16:32";
142 
143   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
144   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
145     Ret += "-a:0:32-S32";
146   else
147     Ret += "-S128";
148 
149   return Ret;
150 }
151 
152 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
153                                            Optional<Reloc::Model> RM) {
154   bool is64Bit = TT.getArch() == Triple::x86_64;
155   if (!RM.hasValue()) {
156     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
157     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
158     // use static relocation model by default.
159     if (TT.isOSDarwin()) {
160       if (is64Bit)
161         return Reloc::PIC_;
162       return Reloc::DynamicNoPIC;
163     }
164     if (TT.isOSWindows() && is64Bit)
165       return Reloc::PIC_;
166     return Reloc::Static;
167   }
168 
169   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
170   // is defined as a model for code which may be used in static or dynamic
171   // executables but not necessarily a shared library. On X86-32 we just
172   // compile in -static mode, in x86-64 we use PIC.
173   if (*RM == Reloc::DynamicNoPIC) {
174     if (is64Bit)
175       return Reloc::PIC_;
176     if (!TT.isOSDarwin())
177       return Reloc::Static;
178   }
179 
180   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
181   // the Mach-O file format doesn't support it.
182   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
183     return Reloc::PIC_;
184 
185   return *RM;
186 }
187 
188 /// Create an X86 target.
189 ///
190 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
191                                    StringRef CPU, StringRef FS,
192                                    const TargetOptions &Options,
193                                    Optional<Reloc::Model> RM,
194                                    CodeModel::Model CM, CodeGenOpt::Level OL)
195     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
196                         getEffectiveRelocModel(TT, RM), CM, OL),
197       TLOF(createTLOF(getTargetTriple())) {
198   // Windows stack unwinder gets confused when execution flow "falls through"
199   // after a call to 'noreturn' function.
200   // To prevent that, we emit a trap for 'unreachable' IR instructions.
201   // (which on X86, happens to be the 'ud2' instruction)
202   // On PS4, the "return address" of a 'noreturn' call must still be within
203   // the calling function, and TrapUnreachable is an easy way to get that.
204   // The check here for 64-bit windows is a bit icky, but as we're unlikely
205   // to ever want to mix 32 and 64-bit windows code in a single module
206   // this should be fine.
207   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
208     this->Options.TrapUnreachable = true;
209 
210   initAsmInfo();
211 }
212 
213 X86TargetMachine::~X86TargetMachine() = default;
214 
215 #ifdef LLVM_BUILD_GLOBAL_ISEL
216 namespace {
217 
218 struct X86GISelActualAccessor : public GISelAccessor {
219   std::unique_ptr<CallLowering> CallLoweringInfo;
220   std::unique_ptr<LegalizerInfo> Legalizer;
221   std::unique_ptr<RegisterBankInfo> RegBankInfo;
222   std::unique_ptr<InstructionSelector> InstSelector;
223 
224   const CallLowering *getCallLowering() const override {
225     return CallLoweringInfo.get();
226   }
227 
228   const InstructionSelector *getInstructionSelector() const override {
229     return InstSelector.get();
230   }
231 
232   const LegalizerInfo *getLegalizerInfo() const override {
233     return Legalizer.get();
234   }
235 
236   const RegisterBankInfo *getRegBankInfo() const override {
237     return RegBankInfo.get();
238   }
239 };
240 
241 } // end anonymous namespace
242 #endif
243 
244 const X86Subtarget *
245 X86TargetMachine::getSubtargetImpl(const Function &F) const {
246   Attribute CPUAttr = F.getFnAttribute("target-cpu");
247   Attribute FSAttr = F.getFnAttribute("target-features");
248 
249   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
250                       ? CPUAttr.getValueAsString()
251                       : (StringRef)TargetCPU;
252   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
253                      ? FSAttr.getValueAsString()
254                      : (StringRef)TargetFS;
255 
256   SmallString<512> Key;
257   Key.reserve(CPU.size() + FS.size());
258   Key += CPU;
259   Key += FS;
260 
261   // FIXME: This is related to the code below to reset the target options,
262   // we need to know whether or not the soft float flag is set on the
263   // function before we can generate a subtarget. We also need to use
264   // it as a key for the subtarget since that can be the only difference
265   // between two functions.
266   bool SoftFloat =
267       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
268   // If the soft float attribute is set on the function turn on the soft float
269   // subtarget feature.
270   if (SoftFloat)
271     Key += FS.empty() ? "+soft-float" : ",+soft-float";
272 
273   FS = Key.substr(CPU.size());
274 
275   auto &I = SubtargetMap[Key];
276   if (!I) {
277     // This needs to be done before we create a new subtarget since any
278     // creation will depend on the TM and the code generation flags on the
279     // function that reside in TargetOptions.
280     resetTargetOptions(F);
281     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
282                                         Options.StackAlignmentOverride);
283 #ifndef LLVM_BUILD_GLOBAL_ISEL
284     GISelAccessor *GISel = new GISelAccessor();
285 #else
286     X86GISelActualAccessor *GISel = new X86GISelActualAccessor();
287 
288     GISel->CallLoweringInfo.reset(new X86CallLowering(*I->getTargetLowering()));
289     GISel->Legalizer.reset(new X86LegalizerInfo(*I, *this));
290 
291     auto *RBI = new X86RegisterBankInfo(*I->getRegisterInfo());
292     GISel->RegBankInfo.reset(RBI);
293     GISel->InstSelector.reset(createX86InstructionSelector(
294         *this, *I, *RBI));
295 #endif
296     I->setGISelAccessor(*GISel);
297   }
298   return I.get();
299 }
300 
301 //===----------------------------------------------------------------------===//
302 // Command line options for x86
303 //===----------------------------------------------------------------------===//
304 static cl::opt<bool>
305 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
306   cl::desc("Minimize AVX to SSE transition penalty"),
307   cl::init(true));
308 
309 //===----------------------------------------------------------------------===//
310 // X86 TTI query.
311 //===----------------------------------------------------------------------===//
312 
313 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
314   return TargetIRAnalysis([this](const Function &F) {
315     return TargetTransformInfo(X86TTIImpl(this, F));
316   });
317 }
318 
319 //===----------------------------------------------------------------------===//
320 // Pass Pipeline Configuration
321 //===----------------------------------------------------------------------===//
322 
323 namespace {
324 
325 /// X86 Code Generator Pass Configuration Options.
326 class X86PassConfig : public TargetPassConfig {
327 public:
328   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
329     : TargetPassConfig(TM, PM) {}
330 
331   X86TargetMachine &getX86TargetMachine() const {
332     return getTM<X86TargetMachine>();
333   }
334 
335   ScheduleDAGInstrs *
336   createMachineScheduler(MachineSchedContext *C) const override {
337     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
338     DAG->addMutation(createX86MacroFusionDAGMutation());
339     return DAG;
340   }
341 
342   void addIRPasses() override;
343   bool addInstSelector() override;
344 #ifdef LLVM_BUILD_GLOBAL_ISEL
345   bool addIRTranslator() override;
346   bool addLegalizeMachineIR() override;
347   bool addRegBankSelect() override;
348   bool addGlobalInstructionSelect() override;
349 #endif
350   bool addILPOpts() override;
351   bool addPreISel() override;
352   void addPreRegAlloc() override;
353   void addPostRegAlloc() override;
354   void addPreEmitPass() override;
355   void addPreSched2() override;
356 };
357 
358 class X86ExecutionDepsFix : public ExecutionDepsFix {
359 public:
360   static char ID;
361   X86ExecutionDepsFix() : ExecutionDepsFix(ID, X86::VR128XRegClass) {}
362   StringRef getPassName() const override {
363     return "X86 Execution Dependency Fix";
364   }
365 };
366 char X86ExecutionDepsFix::ID;
367 
368 } // end anonymous namespace
369 
370 INITIALIZE_PASS(X86ExecutionDepsFix, "x86-execution-deps-fix",
371                 "X86 Execution Dependency Fix", false, false)
372 
373 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
374   return new X86PassConfig(*this, PM);
375 }
376 
377 void X86PassConfig::addIRPasses() {
378   addPass(createAtomicExpandPass());
379 
380   TargetPassConfig::addIRPasses();
381 
382   if (TM->getOptLevel() != CodeGenOpt::None)
383     addPass(createInterleavedAccessPass());
384 }
385 
386 bool X86PassConfig::addInstSelector() {
387   // Install an instruction selector.
388   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
389 
390   // For ELF, cleanup any local-dynamic TLS accesses.
391   if (TM->getTargetTriple().isOSBinFormatELF() &&
392       getOptLevel() != CodeGenOpt::None)
393     addPass(createCleanupLocalDynamicTLSPass());
394 
395   addPass(createX86GlobalBaseRegPass());
396   return false;
397 }
398 
399 #ifdef LLVM_BUILD_GLOBAL_ISEL
400 bool X86PassConfig::addIRTranslator() {
401   addPass(new IRTranslator());
402   return false;
403 }
404 
405 bool X86PassConfig::addLegalizeMachineIR() {
406   addPass(new Legalizer());
407   return false;
408 }
409 
410 bool X86PassConfig::addRegBankSelect() {
411   addPass(new RegBankSelect());
412   return false;
413 }
414 
415 bool X86PassConfig::addGlobalInstructionSelect() {
416   addPass(new InstructionSelect());
417   return false;
418 }
419 #endif
420 
421 bool X86PassConfig::addILPOpts() {
422   addPass(&EarlyIfConverterID);
423   if (EnableMachineCombinerPass)
424     addPass(&MachineCombinerID);
425   return true;
426 }
427 
428 bool X86PassConfig::addPreISel() {
429   // Only add this pass for 32-bit x86 Windows.
430   const Triple &TT = TM->getTargetTriple();
431   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
432     addPass(createX86WinEHStatePass());
433   return true;
434 }
435 
436 void X86PassConfig::addPreRegAlloc() {
437   if (getOptLevel() != CodeGenOpt::None) {
438     addPass(&LiveRangeShrinkID);
439     addPass(createX86FixupSetCC());
440     addPass(createX86OptimizeLEAs());
441     addPass(createX86CallFrameOptimization());
442   }
443 
444   addPass(createX86WinAllocaExpander());
445 }
446 
447 void X86PassConfig::addPostRegAlloc() {
448   addPass(createX86FloatingPointStackifierPass());
449 }
450 
451 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
452 
453 void X86PassConfig::addPreEmitPass() {
454   if (getOptLevel() != CodeGenOpt::None)
455     addPass(new X86ExecutionDepsFix());
456 
457   if (UseVZeroUpper)
458     addPass(createX86IssueVZeroUpperPass());
459 
460   if (getOptLevel() != CodeGenOpt::None) {
461     addPass(createX86FixupBWInsts());
462     addPass(createX86PadShortFunctions());
463     addPass(createX86FixupLEAs());
464     addPass(createX86EvexToVexInsts());
465   }
466 }
467