1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the X86 specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86TargetMachine.h" 15 #include "X86.h" 16 #include "llvm/IntrinsicLowering.h" 17 #include "llvm/Module.h" 18 #include "llvm/PassManager.h" 19 #include "llvm/Target/TargetMachineImpls.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/Transforms/Scalar.h" 23 #include "Support/CommandLine.h" 24 #include "Support/Statistic.h" 25 using namespace llvm; 26 27 namespace { 28 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true), 29 cl::desc("Use the 'simple' X86 instruction selector")); 30 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true), 31 cl::desc("Disable the ssa-based peephole optimizer " 32 "(defaults to disabled)")); 33 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden, 34 cl::desc("Disable the X86 asm printer, for use " 35 "when profiling the code generator.")); 36 cl::opt<bool> NoSimpleISel("disable-simple-isel", cl::init(true), 37 cl::desc("Use the hand coded 'simple' X86 instruction selector")); 38 } 39 40 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine 41 // that implements the X86 backend. 42 // 43 TargetMachine *llvm::allocateX86TargetMachine(const Module &M, 44 IntrinsicLowering *IL) { 45 return new X86TargetMachine(M, IL); 46 } 47 48 49 /// X86TargetMachine ctor - Create an ILP32 architecture model 50 /// 51 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL) 52 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4), 53 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4), 54 JITInfo(*this) { 55 } 56 57 58 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT 59 // does to emit statically compiled machine code. 60 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM, 61 std::ostream &Out) { 62 // FIXME: Implement the invoke/unwind instructions! 63 PM.add(createLowerInvokePass()); 64 65 // FIXME: The code generator does not properly handle functions with 66 // unreachable basic blocks. 67 PM.add(createCFGSimplificationPass()); 68 69 // FIXME: Implement the switch instruction in the instruction selector! 70 PM.add(createLowerSwitchPass()); 71 72 if (NoPatternISel && NoSimpleISel) 73 PM.add(createX86SimpleInstructionSelector(*this)); 74 else if (NoPatternISel) 75 PM.add(createX86ReallySimpleInstructionSelector(*this)); 76 else 77 PM.add(createX86PatternInstructionSelector(*this)); 78 79 // Run optional SSA-based machine code optimizations next... 80 if (!NoSSAPeephole) 81 PM.add(createX86SSAPeepholeOptimizerPass()); 82 83 // Print the instruction selected machine code... 84 if (PrintMachineCode) 85 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 86 87 // Perform register allocation to convert to a concrete x86 representation 88 PM.add(createRegisterAllocator()); 89 90 if (PrintMachineCode) 91 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 92 93 PM.add(createX86FloatingPointStackifierPass()); 94 95 if (PrintMachineCode) 96 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 97 98 // Insert prolog/epilog code. Eliminate abstract frame index references... 99 PM.add(createPrologEpilogCodeInserter()); 100 101 PM.add(createX86PeepholeOptimizerPass()); 102 103 if (PrintMachineCode) // Print the register-allocated code 104 PM.add(createX86CodePrinterPass(std::cerr, *this)); 105 106 if (!DisableOutput) 107 PM.add(createX86CodePrinterPass(Out, *this)); 108 109 // Delete machine code for this function 110 PM.add(createMachineCodeDeleter()); 111 112 return false; // success! 113 } 114 115 /// addPassesToJITCompile - Add passes to the specified pass manager to 116 /// implement a fast dynamic compiler for this target. Return true if this is 117 /// not supported for this target. 118 /// 119 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) { 120 121 // FIXME: Implement the invoke/unwind instructions! 122 PM.add(createLowerInvokePass()); 123 124 // FIXME: The code generator does not properly handle functions with 125 // unreachable basic blocks. 126 PM.add(createCFGSimplificationPass()); 127 128 // FIXME: Implement the switch instruction in the instruction selector! 129 PM.add(createLowerSwitchPass()); 130 131 if (NoPatternISel) 132 PM.add(createX86SimpleInstructionSelector(TM)); 133 else 134 PM.add(createX86PatternInstructionSelector(TM)); 135 136 // Run optional SSA-based machine code optimizations next... 137 if (!NoSSAPeephole) 138 PM.add(createX86SSAPeepholeOptimizerPass()); 139 140 // FIXME: Add SSA based peephole optimizer here. 141 142 // Print the instruction selected machine code... 143 if (PrintMachineCode) 144 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 145 146 // Perform register allocation to convert to a concrete x86 representation 147 PM.add(createRegisterAllocator()); 148 149 if (PrintMachineCode) 150 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 151 152 PM.add(createX86FloatingPointStackifierPass()); 153 154 if (PrintMachineCode) 155 PM.add(createMachineFunctionPrinterPass(&std::cerr)); 156 157 // Insert prolog/epilog code. Eliminate abstract frame index references... 158 PM.add(createPrologEpilogCodeInserter()); 159 160 PM.add(createX86PeepholeOptimizerPass()); 161 162 if (PrintMachineCode) // Print the register-allocated code 163 PM.add(createX86CodePrinterPass(std::cerr, TM)); 164 } 165 166