1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 using namespace llvm;
24 
25 extern "C" void LLVMInitializeX86Target() {
26   // Register the target.
27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
29 }
30 
31 void X86_32TargetMachine::anchor() { }
32 
33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34                                          StringRef CPU, StringRef FS,
35                                          const TargetOptions &Options,
36                                          Reloc::Model RM, CodeModel::Model CM,
37                                          CodeGenOpt::Level OL)
38   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39     DL(getSubtargetImpl()->isTargetDarwin() ?
40                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
41                "n8:16:32-S128" :
42                (getSubtargetImpl()->isTargetCygMing() ||
43                 getSubtargetImpl()->isTargetWindows()) ?
44                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
45                "n8:16:32-S32" :
46                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
47                "n8:16:32-S128"),
48     InstrInfo(*this),
49     TLInfo(*this),
50     TSInfo(*this),
51     JITInfo(*this) {
52 }
53 
54 void X86_64TargetMachine::anchor() { }
55 
56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
57                                          StringRef CPU, StringRef FS,
58                                          const TargetOptions &Options,
59                                          Reloc::Model RM, CodeModel::Model CM,
60                                          CodeGenOpt::Level OL)
61   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
62     DL("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
63                "n8:16:32:64-S128"),
64     InstrInfo(*this),
65     TLInfo(*this),
66     TSInfo(*this),
67     JITInfo(*this) {
68 }
69 
70 /// X86TargetMachine ctor - Create an X86 target.
71 ///
72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
73                                    StringRef CPU, StringRef FS,
74                                    const TargetOptions &Options,
75                                    Reloc::Model RM, CodeModel::Model CM,
76                                    CodeGenOpt::Level OL,
77                                    bool is64Bit)
78   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
80     FrameLowering(*this, Subtarget),
81     InstrItins(Subtarget.getInstrItineraryData()){
82   // Determine the PICStyle based on the target selected.
83   if (getRelocationModel() == Reloc::Static) {
84     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
85     Subtarget.setPICStyle(PICStyles::None);
86   } else if (Subtarget.is64Bit()) {
87     // PIC in 64 bit mode is always rip-rel.
88     Subtarget.setPICStyle(PICStyles::RIPRel);
89   } else if (Subtarget.isTargetCygMing()) {
90     Subtarget.setPICStyle(PICStyles::None);
91   } else if (Subtarget.isTargetDarwin()) {
92     if (getRelocationModel() == Reloc::PIC_)
93       Subtarget.setPICStyle(PICStyles::StubPIC);
94     else {
95       assert(getRelocationModel() == Reloc::DynamicNoPIC);
96       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
97     }
98   } else if (Subtarget.isTargetELF()) {
99     Subtarget.setPICStyle(PICStyles::GOT);
100   }
101 
102   // default to hard float ABI
103   if (Options.FloatABIType == FloatABI::Default)
104     this->Options.FloatABIType = FloatABI::Hard;
105 }
106 
107 //===----------------------------------------------------------------------===//
108 // Command line options for x86
109 //===----------------------------------------------------------------------===//
110 static cl::opt<bool>
111 UseVZeroUpper("x86-use-vzeroupper",
112   cl::desc("Minimize AVX to SSE transition penalty"),
113   cl::init(true));
114 
115 // Temporary option to control early if-conversion for x86 while adding machine
116 // models.
117 static cl::opt<bool>
118 X86EarlyIfConv("x86-early-ifcvt",
119 	       cl::desc("Enable early if-conversion on X86"));
120 
121 //===----------------------------------------------------------------------===//
122 // X86 Analysis Pass Setup
123 //===----------------------------------------------------------------------===//
124 
125 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
126   // Add first the target-independent BasicTTI pass, then our X86 pass. This
127   // allows the X86 pass to delegate to the target independent layer when
128   // appropriate.
129   PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
130   PM.add(createX86TargetTransformInfoPass(this));
131 }
132 
133 
134 //===----------------------------------------------------------------------===//
135 // Pass Pipeline Configuration
136 //===----------------------------------------------------------------------===//
137 
138 namespace {
139 /// X86 Code Generator Pass Configuration Options.
140 class X86PassConfig : public TargetPassConfig {
141 public:
142   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
143     : TargetPassConfig(TM, PM) {}
144 
145   X86TargetMachine &getX86TargetMachine() const {
146     return getTM<X86TargetMachine>();
147   }
148 
149   const X86Subtarget &getX86Subtarget() const {
150     return *getX86TargetMachine().getSubtargetImpl();
151   }
152 
153   virtual bool addInstSelector();
154   virtual bool addPreRegAlloc();
155   virtual bool addPostRegAlloc();
156   virtual bool addPreEmitPass();
157 };
158 } // namespace
159 
160 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
161   X86PassConfig *PC = new X86PassConfig(this, PM);
162 
163   if (X86EarlyIfConv && Subtarget.hasCMov())
164     PC->enablePass(&EarlyIfConverterID);
165 
166   return PC;
167 }
168 
169 bool X86PassConfig::addInstSelector() {
170   // Install an instruction selector.
171   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
172 
173   // For ELF, cleanup any local-dynamic TLS accesses.
174   if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
175     addPass(createCleanupLocalDynamicTLSPass());
176 
177   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
178   if (!getX86Subtarget().is64Bit())
179     addPass(createGlobalBaseRegPass());
180 
181   return false;
182 }
183 
184 bool X86PassConfig::addPreRegAlloc() {
185   return false;  // -print-machineinstr shouldn't print after this.
186 }
187 
188 bool X86PassConfig::addPostRegAlloc() {
189   addPass(createX86FloatingPointStackifierPass());
190   return true;  // -print-machineinstr should print after this.
191 }
192 
193 bool X86PassConfig::addPreEmitPass() {
194   bool ShouldPrint = false;
195   if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
196     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
197     ShouldPrint = true;
198   }
199 
200   if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
201     addPass(createX86IssueVZeroUpperPass());
202     ShouldPrint = true;
203   }
204 
205   if (getOptLevel() != CodeGenOpt::None &&
206       getX86Subtarget().padShortFunctions()) {
207     addPass(createX86PadShortFunctions());
208     ShouldPrint = true;
209   }
210 
211   return ShouldPrint;
212 }
213 
214 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
215                                       JITCodeEmitter &JCE) {
216   PM.add(createX86JITCodeEmitterPass(*this, JCE));
217 
218   return false;
219 }
220