1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86MacroFusion.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDepsFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Target/TargetLoweringObjectFile.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
54                                cl::desc("Enable the machine combiner pass"),
55                                cl::init(true), cl::Hidden);
56 
57 namespace llvm {
58 
59 void initializeWinEHStatePassPass(PassRegistry &);
60 void initializeFixupLEAPassPass(PassRegistry &);
61 void initializeX86CmovConverterPassPass(PassRegistry &);
62 void initializeX86ExecutionDepsFixPass(PassRegistry &);
63 void initializeX86DomainReassignmentPass(PassRegistry &);
64 
65 } // end namespace llvm
66 
67 extern "C" void LLVMInitializeX86Target() {
68   // Register the target.
69   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
70   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
71 
72   PassRegistry &PR = *PassRegistry::getPassRegistry();
73   initializeGlobalISel(PR);
74   initializeWinEHStatePassPass(PR);
75   initializeFixupBWInstPassPass(PR);
76   initializeEvexToVexInstPassPass(PR);
77   initializeFixupLEAPassPass(PR);
78   initializeX86CmovConverterPassPass(PR);
79   initializeX86ExecutionDepsFixPass(PR);
80   initializeX86DomainReassignmentPass(PR);
81 }
82 
83 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
84   if (TT.isOSBinFormatMachO()) {
85     if (TT.getArch() == Triple::x86_64)
86       return llvm::make_unique<X86_64MachoTargetObjectFile>();
87     return llvm::make_unique<TargetLoweringObjectFileMachO>();
88   }
89 
90   if (TT.isOSFreeBSD())
91     return llvm::make_unique<X86FreeBSDTargetObjectFile>();
92   if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
93     return llvm::make_unique<X86LinuxNaClTargetObjectFile>();
94   if (TT.isOSSolaris())
95     return llvm::make_unique<X86SolarisTargetObjectFile>();
96   if (TT.isOSFuchsia())
97     return llvm::make_unique<X86FuchsiaTargetObjectFile>();
98   if (TT.isOSBinFormatELF())
99     return llvm::make_unique<X86ELFTargetObjectFile>();
100   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
101     return llvm::make_unique<X86WindowsTargetObjectFile>();
102   if (TT.isOSBinFormatCOFF())
103     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
104   llvm_unreachable("unknown subtarget type");
105 }
106 
107 static std::string computeDataLayout(const Triple &TT) {
108   // X86 is little endian
109   std::string Ret = "e";
110 
111   Ret += DataLayout::getManglingComponent(TT);
112   // X86 and x32 have 32 bit pointers.
113   if ((TT.isArch64Bit() &&
114        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
115       !TT.isArch64Bit())
116     Ret += "-p:32:32";
117 
118   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
119   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
120     Ret += "-i64:64";
121   else if (TT.isOSIAMCU())
122     Ret += "-i64:32-f64:32";
123   else
124     Ret += "-f64:32:64";
125 
126   // Some ABIs align long double to 128 bits, others to 32.
127   if (TT.isOSNaCl() || TT.isOSIAMCU())
128     ; // No f80
129   else if (TT.isArch64Bit() || TT.isOSDarwin())
130     Ret += "-f80:128";
131   else
132     Ret += "-f80:32";
133 
134   if (TT.isOSIAMCU())
135     Ret += "-f128:32";
136 
137   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
138   if (TT.isArch64Bit())
139     Ret += "-n8:16:32:64";
140   else
141     Ret += "-n8:16:32";
142 
143   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
144   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
145     Ret += "-a:0:32-S32";
146   else
147     Ret += "-S128";
148 
149   return Ret;
150 }
151 
152 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
153                                            Optional<Reloc::Model> RM) {
154   bool is64Bit = TT.getArch() == Triple::x86_64;
155   if (!RM.hasValue()) {
156     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
157     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
158     // use static relocation model by default.
159     if (TT.isOSDarwin()) {
160       if (is64Bit)
161         return Reloc::PIC_;
162       return Reloc::DynamicNoPIC;
163     }
164     if (TT.isOSWindows() && is64Bit)
165       return Reloc::PIC_;
166     return Reloc::Static;
167   }
168 
169   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
170   // is defined as a model for code which may be used in static or dynamic
171   // executables but not necessarily a shared library. On X86-32 we just
172   // compile in -static mode, in x86-64 we use PIC.
173   if (*RM == Reloc::DynamicNoPIC) {
174     if (is64Bit)
175       return Reloc::PIC_;
176     if (!TT.isOSDarwin())
177       return Reloc::Static;
178   }
179 
180   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
181   // the Mach-O file format doesn't support it.
182   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
183     return Reloc::PIC_;
184 
185   return *RM;
186 }
187 
188 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM,
189                                               bool JIT, bool Is64Bit) {
190   if (CM)
191     return *CM;
192   if (JIT)
193     return Is64Bit ? CodeModel::Large : CodeModel::Small;
194   return CodeModel::Small;
195 }
196 
197 /// Create an X86 target.
198 ///
199 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
200                                    StringRef CPU, StringRef FS,
201                                    const TargetOptions &Options,
202                                    Optional<Reloc::Model> RM,
203                                    Optional<CodeModel::Model> CM,
204                                    CodeGenOpt::Level OL, bool JIT)
205     : LLVMTargetMachine(
206           T, computeDataLayout(TT), TT, CPU, FS, Options,
207           getEffectiveRelocModel(TT, RM),
208           getEffectiveCodeModel(CM, JIT, TT.getArch() == Triple::x86_64), OL),
209       TLOF(createTLOF(getTargetTriple())) {
210   // Windows stack unwinder gets confused when execution flow "falls through"
211   // after a call to 'noreturn' function.
212   // To prevent that, we emit a trap for 'unreachable' IR instructions.
213   // (which on X86, happens to be the 'ud2' instruction)
214   // On PS4, the "return address" of a 'noreturn' call must still be within
215   // the calling function, and TrapUnreachable is an easy way to get that.
216   // The check here for 64-bit windows is a bit icky, but as we're unlikely
217   // to ever want to mix 32 and 64-bit windows code in a single module
218   // this should be fine.
219   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
220     this->Options.TrapUnreachable = true;
221 
222   initAsmInfo();
223 }
224 
225 X86TargetMachine::~X86TargetMachine() = default;
226 
227 const X86Subtarget *
228 X86TargetMachine::getSubtargetImpl(const Function &F) const {
229   Attribute CPUAttr = F.getFnAttribute("target-cpu");
230   Attribute FSAttr = F.getFnAttribute("target-features");
231 
232   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
233                       ? CPUAttr.getValueAsString()
234                       : (StringRef)TargetCPU;
235   StringRef FS = !FSAttr.hasAttribute(Attribute::None)
236                      ? FSAttr.getValueAsString()
237                      : (StringRef)TargetFS;
238 
239   SmallString<512> Key;
240   Key.reserve(CPU.size() + FS.size());
241   Key += CPU;
242   Key += FS;
243 
244   // FIXME: This is related to the code below to reset the target options,
245   // we need to know whether or not the soft float flag is set on the
246   // function before we can generate a subtarget. We also need to use
247   // it as a key for the subtarget since that can be the only difference
248   // between two functions.
249   bool SoftFloat =
250       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
251   // If the soft float attribute is set on the function turn on the soft float
252   // subtarget feature.
253   if (SoftFloat)
254     Key += FS.empty() ? "+soft-float" : ",+soft-float";
255 
256   FS = Key.substr(CPU.size());
257 
258   auto &I = SubtargetMap[Key];
259   if (!I) {
260     // This needs to be done before we create a new subtarget since any
261     // creation will depend on the TM and the code generation flags on the
262     // function that reside in TargetOptions.
263     resetTargetOptions(F);
264     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
265                                         Options.StackAlignmentOverride);
266   }
267   return I.get();
268 }
269 
270 //===----------------------------------------------------------------------===//
271 // Command line options for x86
272 //===----------------------------------------------------------------------===//
273 static cl::opt<bool>
274 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
275   cl::desc("Minimize AVX to SSE transition penalty"),
276   cl::init(true));
277 
278 //===----------------------------------------------------------------------===//
279 // X86 TTI query.
280 //===----------------------------------------------------------------------===//
281 
282 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
283   return TargetIRAnalysis([this](const Function &F) {
284     return TargetTransformInfo(X86TTIImpl(this, F));
285   });
286 }
287 
288 //===----------------------------------------------------------------------===//
289 // Pass Pipeline Configuration
290 //===----------------------------------------------------------------------===//
291 
292 namespace {
293 
294 /// X86 Code Generator Pass Configuration Options.
295 class X86PassConfig : public TargetPassConfig {
296 public:
297   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
298     : TargetPassConfig(TM, PM) {}
299 
300   X86TargetMachine &getX86TargetMachine() const {
301     return getTM<X86TargetMachine>();
302   }
303 
304   ScheduleDAGInstrs *
305   createMachineScheduler(MachineSchedContext *C) const override {
306     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
307     DAG->addMutation(createX86MacroFusionDAGMutation());
308     return DAG;
309   }
310 
311   void addIRPasses() override;
312   bool addInstSelector() override;
313   bool addIRTranslator() override;
314   bool addLegalizeMachineIR() override;
315   bool addRegBankSelect() override;
316   bool addGlobalInstructionSelect() override;
317   bool addILPOpts() override;
318   bool addPreISel() override;
319   void addMachineSSAOptimization() override;
320   void addPreRegAlloc() override;
321   void addPostRegAlloc() override;
322   void addPreEmitPass() override;
323   void addPreSched2() override;
324 };
325 
326 class X86ExecutionDepsFix : public ExecutionDepsFix {
327 public:
328   static char ID;
329   X86ExecutionDepsFix() : ExecutionDepsFix(ID, X86::VR128XRegClass) {}
330   StringRef getPassName() const override {
331     return "X86 Execution Dependency Fix";
332   }
333 };
334 char X86ExecutionDepsFix::ID;
335 
336 } // end anonymous namespace
337 
338 INITIALIZE_PASS(X86ExecutionDepsFix, "x86-execution-deps-fix",
339                 "X86 Execution Dependency Fix", false, false)
340 
341 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
342   return new X86PassConfig(*this, PM);
343 }
344 
345 void X86PassConfig::addIRPasses() {
346   addPass(createAtomicExpandPass());
347 
348   TargetPassConfig::addIRPasses();
349 
350   if (TM->getOptLevel() != CodeGenOpt::None)
351     addPass(createInterleavedAccessPass());
352 }
353 
354 bool X86PassConfig::addInstSelector() {
355   // Install an instruction selector.
356   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
357 
358   // For ELF, cleanup any local-dynamic TLS accesses.
359   if (TM->getTargetTriple().isOSBinFormatELF() &&
360       getOptLevel() != CodeGenOpt::None)
361     addPass(createCleanupLocalDynamicTLSPass());
362 
363   addPass(createX86GlobalBaseRegPass());
364   return false;
365 }
366 
367 bool X86PassConfig::addIRTranslator() {
368   addPass(new IRTranslator());
369   return false;
370 }
371 
372 bool X86PassConfig::addLegalizeMachineIR() {
373   addPass(new Legalizer());
374   return false;
375 }
376 
377 bool X86PassConfig::addRegBankSelect() {
378   addPass(new RegBankSelect());
379   return false;
380 }
381 
382 bool X86PassConfig::addGlobalInstructionSelect() {
383   addPass(new InstructionSelect());
384   return false;
385 }
386 
387 bool X86PassConfig::addILPOpts() {
388   addPass(&EarlyIfConverterID);
389   if (EnableMachineCombinerPass)
390     addPass(&MachineCombinerID);
391   addPass(createX86CmovConverterPass());
392   return true;
393 }
394 
395 bool X86PassConfig::addPreISel() {
396   // Only add this pass for 32-bit x86 Windows.
397   const Triple &TT = TM->getTargetTriple();
398   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
399     addPass(createX86WinEHStatePass());
400   return true;
401 }
402 
403 void X86PassConfig::addPreRegAlloc() {
404   if (getOptLevel() != CodeGenOpt::None) {
405     addPass(&LiveRangeShrinkID);
406     addPass(createX86FixupSetCC());
407     addPass(createX86OptimizeLEAs());
408     addPass(createX86CallFrameOptimization());
409   }
410 
411   addPass(createX86WinAllocaExpander());
412 }
413 void X86PassConfig::addMachineSSAOptimization() {
414   addPass(createX86DomainReassignmentPass());
415   TargetPassConfig::addMachineSSAOptimization();
416 }
417 
418 void X86PassConfig::addPostRegAlloc() {
419   addPass(createX86FloatingPointStackifierPass());
420 }
421 
422 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
423 
424 void X86PassConfig::addPreEmitPass() {
425   if (getOptLevel() != CodeGenOpt::None)
426     addPass(new X86ExecutionDepsFix());
427 
428   if (UseVZeroUpper)
429     addPass(createX86IssueVZeroUpperPass());
430 
431   if (getOptLevel() != CodeGenOpt::None) {
432     addPass(createX86FixupBWInsts());
433     addPass(createX86PadShortFunctions());
434     addPass(createX86FixupLEAs());
435     addPass(createX86EvexToVexInsts());
436   }
437 }
438