1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the X86 specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86TargetMachine.h"
15 #include "X86.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 using namespace llvm;
27 
28 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
29                                cl::desc("Enable the machine combiner pass"),
30                                cl::init(true), cl::Hidden);
31 
32 namespace llvm {
33 void initializeWinEHStatePassPass(PassRegistry &);
34 }
35 
36 extern "C" void LLVMInitializeX86Target() {
37   // Register the target.
38   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
39   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
40 
41   PassRegistry &PR = *PassRegistry::getPassRegistry();
42   initializeWinEHStatePassPass(PR);
43   initializeFixupBWInstPassPass(PR);
44 }
45 
46 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
47   if (TT.isOSBinFormatMachO()) {
48     if (TT.getArch() == Triple::x86_64)
49       return make_unique<X86_64MachoTargetObjectFile>();
50     return make_unique<TargetLoweringObjectFileMachO>();
51   }
52 
53   if (TT.isOSLinux() || TT.isOSNaCl())
54     return make_unique<X86LinuxNaClTargetObjectFile>();
55   if (TT.isOSBinFormatELF())
56     return make_unique<X86ELFTargetObjectFile>();
57   if (TT.isKnownWindowsMSVCEnvironment() || TT.isWindowsCoreCLREnvironment())
58     return make_unique<X86WindowsTargetObjectFile>();
59   if (TT.isOSBinFormatCOFF())
60     return make_unique<TargetLoweringObjectFileCOFF>();
61   llvm_unreachable("unknown subtarget type");
62 }
63 
64 static std::string computeDataLayout(const Triple &TT) {
65   // X86 is little endian
66   std::string Ret = "e";
67 
68   Ret += DataLayout::getManglingComponent(TT);
69   // X86 and x32 have 32 bit pointers.
70   if ((TT.isArch64Bit() &&
71        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
72       !TT.isArch64Bit())
73     Ret += "-p:32:32";
74 
75   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
76   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
77     Ret += "-i64:64";
78   else if (TT.isOSIAMCU())
79     Ret += "-i64:32-f64:32";
80   else
81     Ret += "-f64:32:64";
82 
83   // Some ABIs align long double to 128 bits, others to 32.
84   if (TT.isOSNaCl() || TT.isOSIAMCU())
85     ; // No f80
86   else if (TT.isArch64Bit() || TT.isOSDarwin())
87     Ret += "-f80:128";
88   else
89     Ret += "-f80:32";
90 
91   if (TT.isOSIAMCU())
92     Ret += "-f128:32";
93 
94   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
95   if (TT.isArch64Bit())
96     Ret += "-n8:16:32:64";
97   else
98     Ret += "-n8:16:32";
99 
100   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
101   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
102     Ret += "-a:0:32-S32";
103   else
104     Ret += "-S128";
105 
106   return Ret;
107 }
108 
109 /// X86TargetMachine ctor - Create an X86 target.
110 ///
111 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
112                                    StringRef CPU, StringRef FS,
113                                    const TargetOptions &Options,
114                                    Reloc::Model RM, CodeModel::Model CM,
115                                    CodeGenOpt::Level OL)
116     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
117                         OL),
118       TLOF(createTLOF(getTargetTriple())),
119       Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
120   // Windows stack unwinder gets confused when execution flow "falls through"
121   // after a call to 'noreturn' function.
122   // To prevent that, we emit a trap for 'unreachable' IR instructions.
123   // (which on X86, happens to be the 'ud2' instruction)
124   // On PS4, the "return address" of a 'noreturn' call must still be within
125   // the calling function, and TrapUnreachable is an easy way to get that.
126   if (Subtarget.isTargetWin64() || Subtarget.isTargetPS4())
127     this->Options.TrapUnreachable = true;
128 
129   // By default (and when -ffast-math is on), enable estimate codegen for
130   // everything except scalar division. By default, use 1 refinement step for
131   // all operations. Defaults may be overridden by using command-line options.
132   // Scalar division estimates are disabled because they break too much
133   // real-world code. These defaults match GCC behavior.
134   this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
135   this->Options.Reciprocals.setDefaults("divf", false, 1);
136   this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
137   this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
138 
139   initAsmInfo();
140 }
141 
142 X86TargetMachine::~X86TargetMachine() {}
143 
144 const X86Subtarget *
145 X86TargetMachine::getSubtargetImpl(const Function &F) const {
146   Attribute CPUAttr = F.getFnAttribute("target-cpu");
147   Attribute FSAttr = F.getFnAttribute("target-features");
148 
149   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
150                         ? CPUAttr.getValueAsString().str()
151                         : TargetCPU;
152   std::string FS = !FSAttr.hasAttribute(Attribute::None)
153                        ? FSAttr.getValueAsString().str()
154                        : TargetFS;
155 
156   // FIXME: This is related to the code below to reset the target options,
157   // we need to know whether or not the soft float flag is set on the
158   // function before we can generate a subtarget. We also need to use
159   // it as a key for the subtarget since that can be the only difference
160   // between two functions.
161   bool SoftFloat =
162       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
163   // If the soft float attribute is set on the function turn on the soft float
164   // subtarget feature.
165   if (SoftFloat)
166     FS += FS.empty() ? "+soft-float" : ",+soft-float";
167 
168   auto &I = SubtargetMap[CPU + FS];
169   if (!I) {
170     // This needs to be done before we create a new subtarget since any
171     // creation will depend on the TM and the code generation flags on the
172     // function that reside in TargetOptions.
173     resetTargetOptions(F);
174     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
175                                         Options.StackAlignmentOverride);
176   }
177   return I.get();
178 }
179 
180 //===----------------------------------------------------------------------===//
181 // Command line options for x86
182 //===----------------------------------------------------------------------===//
183 static cl::opt<bool>
184 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
185   cl::desc("Minimize AVX to SSE transition penalty"),
186   cl::init(true));
187 
188 //===----------------------------------------------------------------------===//
189 // X86 TTI query.
190 //===----------------------------------------------------------------------===//
191 
192 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
193   return TargetIRAnalysis([this](const Function &F) {
194     return TargetTransformInfo(X86TTIImpl(this, F));
195   });
196 }
197 
198 
199 //===----------------------------------------------------------------------===//
200 // Pass Pipeline Configuration
201 //===----------------------------------------------------------------------===//
202 
203 namespace {
204 /// X86 Code Generator Pass Configuration Options.
205 class X86PassConfig : public TargetPassConfig {
206 public:
207   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
208     : TargetPassConfig(TM, PM) {}
209 
210   X86TargetMachine &getX86TargetMachine() const {
211     return getTM<X86TargetMachine>();
212   }
213 
214   void addIRPasses() override;
215   bool addInstSelector() override;
216   bool addILPOpts() override;
217   bool addPreISel() override;
218   void addPreRegAlloc() override;
219   void addPostRegAlloc() override;
220   void addPreEmitPass() override;
221   void addPreSched2() override;
222 };
223 } // namespace
224 
225 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
226   return new X86PassConfig(this, PM);
227 }
228 
229 void X86PassConfig::addIRPasses() {
230   addPass(createAtomicExpandPass(&getX86TargetMachine()));
231 
232   TargetPassConfig::addIRPasses();
233 }
234 
235 bool X86PassConfig::addInstSelector() {
236   // Install an instruction selector.
237   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
238 
239   // For ELF, cleanup any local-dynamic TLS accesses.
240   if (TM->getTargetTriple().isOSBinFormatELF() &&
241       getOptLevel() != CodeGenOpt::None)
242     addPass(createCleanupLocalDynamicTLSPass());
243 
244   addPass(createX86GlobalBaseRegPass());
245 
246   return false;
247 }
248 
249 bool X86PassConfig::addILPOpts() {
250   addPass(&EarlyIfConverterID);
251   if (EnableMachineCombinerPass)
252     addPass(&MachineCombinerID);
253   return true;
254 }
255 
256 bool X86PassConfig::addPreISel() {
257   // Only add this pass for 32-bit x86 Windows.
258   const Triple &TT = TM->getTargetTriple();
259   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
260     addPass(createX86WinEHStatePass());
261   return true;
262 }
263 
264 void X86PassConfig::addPreRegAlloc() {
265   if (getOptLevel() != CodeGenOpt::None)
266     addPass(createX86OptimizeLEAs());
267 
268   addPass(createX86CallFrameOptimization());
269 }
270 
271 void X86PassConfig::addPostRegAlloc() {
272   addPass(createX86FloatingPointStackifierPass());
273 }
274 
275 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
276 
277 void X86PassConfig::addPreEmitPass() {
278   if (getOptLevel() != CodeGenOpt::None)
279     addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
280 
281   if (UseVZeroUpper)
282     addPass(createX86IssueVZeroUpperPass());
283 
284   if (getOptLevel() != CodeGenOpt::None) {
285     addPass(createX86FixupBWInsts());
286     addPass(createX86PadShortFunctions());
287     addPass(createX86FixupLEAs());
288   }
289 }
290