1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/Host.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/SmallVector.h"
25 
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "X86GenSubtargetInfo.inc"
29 
30 using namespace llvm;
31 
32 #if defined(_MSC_VER)
33 #include <intrin.h>
34 #endif
35 
36 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
37 /// current subtarget according to how we should reference it in a non-pcrel
38 /// context.
39 unsigned char X86Subtarget::
40 ClassifyBlockAddressReference() const {
41   if (isPICStyleGOT())    // 32-bit ELF targets.
42     return X86II::MO_GOTOFF;
43 
44   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
45     return X86II::MO_PIC_BASE_OFFSET;
46 
47   // Direct static reference to label.
48   return X86II::MO_NO_FLAG;
49 }
50 
51 /// ClassifyGlobalReference - Classify a global variable reference for the
52 /// current subtarget according to how we should reference it in a non-pcrel
53 /// context.
54 unsigned char X86Subtarget::
55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56   // DLLImport only exists on windows, it is implemented as a load from a
57   // DLLIMPORT stub.
58   if (GV->hasDLLImportLinkage())
59     return X86II::MO_DLLIMPORT;
60 
61   // Determine whether this is a reference to a definition or a declaration.
62   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63   // load from stub.
64   bool isDecl = GV->hasAvailableExternallyLinkage();
65   if (GV->isDeclaration() && !GV->isMaterializable())
66     isDecl = true;
67 
68   // X86-64 in PIC mode.
69   if (isPICStyleRIPRel()) {
70     // Large model never uses stubs.
71     if (TM.getCodeModel() == CodeModel::Large)
72       return X86II::MO_NO_FLAG;
73 
74     if (isTargetDarwin()) {
75       // If symbol visibility is hidden, the extra load is not needed if
76       // target is x86-64 or the symbol is definitely defined in the current
77       // translation unit.
78       if (GV->hasDefaultVisibility() &&
79           (isDecl || GV->isWeakForLinker()))
80         return X86II::MO_GOTPCREL;
81     } else if (!isTargetWin64()) {
82       assert(isTargetELF() && "Unknown rip-relative target");
83 
84       // Extra load is needed for all externally visible.
85       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86         return X86II::MO_GOTPCREL;
87     }
88 
89     return X86II::MO_NO_FLAG;
90   }
91 
92   if (isPICStyleGOT()) {   // 32-bit ELF targets.
93     // Extra load is needed for all externally visible.
94     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95       return X86II::MO_GOTOFF;
96     return X86II::MO_GOT;
97   }
98 
99   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
100     // Determine whether we have a stub reference and/or whether the reference
101     // is relative to the PIC base or not.
102 
103     // If this is a strong reference to a definition, it is definitely not
104     // through a stub.
105     if (!isDecl && !GV->isWeakForLinker())
106       return X86II::MO_PIC_BASE_OFFSET;
107 
108     // Unless we have a symbol with hidden visibility, we have to go through a
109     // normal $non_lazy_ptr stub because this symbol might be resolved late.
110     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
111       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112 
113     // If symbol visibility is hidden, we have a stub for common symbol
114     // references and external declarations.
115     if (isDecl || GV->hasCommonLinkage()) {
116       // Hidden $non_lazy_ptr reference.
117       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
118     }
119 
120     // Otherwise, no stub.
121     return X86II::MO_PIC_BASE_OFFSET;
122   }
123 
124   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
125     // Determine whether we have a stub reference.
126 
127     // If this is a strong reference to a definition, it is definitely not
128     // through a stub.
129     if (!isDecl && !GV->isWeakForLinker())
130       return X86II::MO_NO_FLAG;
131 
132     // Unless we have a symbol with hidden visibility, we have to go through a
133     // normal $non_lazy_ptr stub because this symbol might be resolved late.
134     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
135       return X86II::MO_DARWIN_NONLAZY;
136 
137     // Otherwise, no stub.
138     return X86II::MO_NO_FLAG;
139   }
140 
141   // Direct static reference to global.
142   return X86II::MO_NO_FLAG;
143 }
144 
145 
146 /// getBZeroEntry - This function returns the name of a function which has an
147 /// interface like the non-standard bzero function, if such a function exists on
148 /// the current subtarget and it is considered prefereable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151   // Darwin 10 has a __bzero entry point for this purpose.
152   if (getTargetTriple().isMacOSX() &&
153       !getTargetTriple().isMacOSXVersionLT(10, 6))
154     return "__bzero";
155 
156   return 0;
157 }
158 
159 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
160 /// to immediate address.
161 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
162   if (In64BitMode)
163     return false;
164   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
165 }
166 
167 /// getSpecialAddressLatency - For targets where it is beneficial to
168 /// backschedule instructions that compute addresses, return a value
169 /// indicating the number of scheduling cycles of backscheduling that
170 /// should be attempted.
171 unsigned X86Subtarget::getSpecialAddressLatency() const {
172   // For x86 out-of-order targets, back-schedule address computations so
173   // that loads and stores aren't blocked.
174   // This value was chosen arbitrarily.
175   return 200;
176 }
177 
178 void X86Subtarget::AutoDetectSubtargetFeatures() {
179   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
180   unsigned MaxLevel;
181   union {
182     unsigned u[3];
183     char     c[12];
184   } text;
185 
186   if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
187       MaxLevel < 1)
188     return;
189 
190   X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
191 
192   if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
193   if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
194   if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
195   if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
196   if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
197   if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
198   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
199   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
200   // FIXME: AVX codegen support is not ready.
201   //if ((ECX >> 28) & 1) { X86SSELevel = AVX;  ToggleFeature(X86::FeatureAVX); }
202 
203   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
204   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
205 
206   if (IsIntel && ((ECX >> 1) & 0x1)) {
207     HasCLMUL = true;
208     ToggleFeature(X86::FeatureCLMUL);
209   }
210   if (IsIntel && ((ECX >> 12) & 0x1)) {
211     HasFMA3 = true;
212     ToggleFeature(X86::FeatureFMA3);
213   }
214   if (IsIntel && ((ECX >> 22) & 0x1)) {
215     HasMOVBE = true;
216     ToggleFeature(X86::FeatureMOVBE);
217   }
218   if (IsIntel && ((ECX >> 23) & 0x1)) {
219     HasPOPCNT = true;
220     ToggleFeature(X86::FeaturePOPCNT);
221   }
222   if (IsIntel && ((ECX >> 25) & 0x1)) {
223     HasAES = true;
224     ToggleFeature(X86::FeatureAES);
225   }
226   if (IsIntel && ((ECX >> 29) & 0x1)) {
227     HasF16C = true;
228     ToggleFeature(X86::FeatureF16C);
229   }
230   if (IsIntel && ((ECX >> 30) & 0x1)) {
231     HasRDRAND = true;
232     ToggleFeature(X86::FeatureRDRAND);
233   }
234 
235   if ((ECX >> 13) & 0x1) {
236     HasCmpxchg16b = true;
237     ToggleFeature(X86::FeatureCMPXCHG16B);
238   }
239 
240   if (IsIntel || IsAMD) {
241     // Determine if bit test memory instructions are slow.
242     unsigned Family = 0;
243     unsigned Model  = 0;
244     X86_MC::DetectFamilyModel(EAX, Family, Model);
245     if (IsAMD || (Family == 6 && Model >= 13)) {
246       IsBTMemSlow = true;
247       ToggleFeature(X86::FeatureSlowBTMem);
248     }
249 
250     // If it's Nehalem, unaligned memory access is fast.
251     // FIXME: Nehalem is family 6. Also include Westmere and later processors?
252     if (Family == 15 && Model == 26) {
253       IsUAMemFast = true;
254       ToggleFeature(X86::FeatureFastUAMem);
255     }
256 
257     // Set processor type. Currently only Atom is detected.
258     if (Family == 6 && Model == 28) {
259       X86ProcFamily = IntelAtom;
260       ToggleFeature(X86::FeatureLeaForSP);
261     }
262 
263     unsigned MaxExtLevel;
264     X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
265 
266     if (MaxExtLevel >= 0x80000001) {
267       X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
268       if ((EDX >> 29) & 0x1) {
269         HasX86_64 = true;
270         ToggleFeature(X86::Feature64Bit);
271       }
272       if ((ECX >> 5) & 0x1) {
273         HasLZCNT = true;
274         ToggleFeature(X86::FeatureLZCNT);
275       }
276       if (IsAMD) {
277         if ((ECX >> 6) & 0x1) {
278           HasSSE4A = true;
279           ToggleFeature(X86::FeatureSSE4A);
280         }
281         if ((ECX >> 11) & 0x1) {
282           HasXOP = true;
283           ToggleFeature(X86::FeatureXOP);
284         }
285         if ((ECX >> 16) & 0x1) {
286           HasFMA4 = true;
287           ToggleFeature(X86::FeatureFMA4);
288         }
289       }
290     }
291   }
292 
293   if (IsIntel && MaxLevel >= 7) {
294     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
295       if (EBX & 0x1) {
296         HasFSGSBase = true;
297         ToggleFeature(X86::FeatureFSGSBase);
298       }
299       if ((EBX >> 3) & 0x1) {
300         HasBMI = true;
301         ToggleFeature(X86::FeatureBMI);
302       }
303       // FIXME: AVX2 codegen support is not ready.
304       //if ((EBX >> 5) & 0x1) {
305       //  X86SSELevel = AVX2;;
306       //  ToggleFeature(X86::FeatureAVX2);
307       //}
308       if ((EBX >> 8) & 0x1) {
309         HasBMI2 = true;
310         ToggleFeature(X86::FeatureBMI2);
311       }
312     }
313   }
314 }
315 
316 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
317                            const std::string &FS,
318                            unsigned StackAlignOverride, bool is64Bit)
319   : X86GenSubtargetInfo(TT, CPU, FS)
320   , X86ProcFamily(Others)
321   , PICStyle(PICStyles::None)
322   , X86SSELevel(NoMMXSSE)
323   , X863DNowLevel(NoThreeDNow)
324   , HasCMov(false)
325   , HasX86_64(false)
326   , HasPOPCNT(false)
327   , HasSSE4A(false)
328   , HasAES(false)
329   , HasCLMUL(false)
330   , HasFMA3(false)
331   , HasFMA4(false)
332   , HasXOP(false)
333   , HasMOVBE(false)
334   , HasRDRAND(false)
335   , HasF16C(false)
336   , HasFSGSBase(false)
337   , HasLZCNT(false)
338   , HasBMI(false)
339   , HasBMI2(false)
340   , IsBTMemSlow(false)
341   , IsUAMemFast(false)
342   , HasVectorUAMem(false)
343   , HasCmpxchg16b(false)
344   , UseLeaForSP(false)
345   , PostRAScheduler(false)
346   , stackAlignment(4)
347   // FIXME: this is a known good value for Yonah. How about others?
348   , MaxInlineSizeThreshold(128)
349   , TargetTriple(TT)
350   , In64BitMode(is64Bit) {
351   // Determine default and user specified characteristics
352   std::string CPUName = CPU;
353   if (!FS.empty() || !CPU.empty()) {
354     if (CPUName.empty()) {
355 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
356     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
357       CPUName = sys::getHostCPUName();
358 #else
359       CPUName = "generic";
360 #endif
361     }
362 
363     // Make sure 64-bit features are available in 64-bit mode. (But make sure
364     // SSE2 can be turned off explicitly.)
365     std::string FullFS = FS;
366     if (In64BitMode) {
367       if (!FullFS.empty())
368         FullFS = "+64bit,+sse2," + FullFS;
369       else
370         FullFS = "+64bit,+sse2";
371     }
372 
373     // If feature string is not empty, parse features string.
374     ParseSubtargetFeatures(CPUName, FullFS);
375   } else {
376     if (CPUName.empty()) {
377 #if defined (__x86_64__) || defined(__i386__)
378       CPUName = sys::getHostCPUName();
379 #else
380       CPUName = "generic";
381 #endif
382     }
383     // Otherwise, use CPUID to auto-detect feature set.
384     AutoDetectSubtargetFeatures();
385 
386     // Make sure 64-bit features are available in 64-bit mode.
387     if (In64BitMode) {
388       HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
389       HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
390 
391       if (X86SSELevel < SSE2) {
392         X86SSELevel = SSE2;
393         ToggleFeature(X86::FeatureSSE1);
394         ToggleFeature(X86::FeatureSSE2);
395       }
396     }
397   }
398 
399   if (X86ProcFamily == IntelAtom) {
400     PostRAScheduler = true;
401     InstrItins = getInstrItineraryForCPU(CPUName);
402   }
403 
404   // It's important to keep the MCSubtargetInfo feature bits in sync with
405   // target data structure which is shared with MC code emitter, etc.
406   if (In64BitMode)
407     ToggleFeature(X86::Mode64Bit);
408 
409   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
410                << ", 3DNowLevel " << X863DNowLevel
411                << ", 64bit " << HasX86_64 << "\n");
412   assert((!In64BitMode || HasX86_64) &&
413          "64-bit code requested on a subtarget that doesn't support it!");
414 
415   // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
416   // 32 and 64 bit) and for all 64-bit targets.
417   if (StackAlignOverride)
418     stackAlignment = StackAlignOverride;
419   else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
420            isTargetSolaris() || In64BitMode)
421     stackAlignment = 16;
422 }
423 
424 bool X86Subtarget::enablePostRAScheduler(
425            CodeGenOpt::Level OptLevel,
426            TargetSubtargetInfo::AntiDepBreakMode& Mode,
427            RegClassVector& CriticalPathRCs) const {
428   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
429   CriticalPathRCs.clear();
430   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
431 }
432