1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86Subtarget.h"
14 #include "MCTargetDesc/X86BaseInfo.h"
15 #include "X86.h"
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86MacroFusion.h"
19 #include "X86RegisterBankInfo.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/IR/Attributes.h"
25 #include "llvm/IR/ConstantRange.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/CodeGen.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 
36 #if defined(_MSC_VER)
37 #include <intrin.h>
38 #endif
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "subtarget"
43 
44 #define GET_SUBTARGETINFO_TARGET_DESC
45 #define GET_SUBTARGETINFO_CTOR
46 #include "X86GenSubtargetInfo.inc"
47 
48 // Temporary option to control early if-conversion for x86 while adding machine
49 // models.
50 static cl::opt<bool>
51 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
52                cl::desc("Enable early if-conversion on X86"));
53 
54 
55 /// Classify a blockaddress reference for the current subtarget according to how
56 /// we should reference it in a non-pcrel context.
57 unsigned char X86Subtarget::classifyBlockAddressReference() const {
58   return classifyLocalReference(nullptr);
59 }
60 
61 /// Classify a global variable reference for the current subtarget according to
62 /// how we should reference it in a non-pcrel context.
63 unsigned char
64 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
65   return classifyGlobalReference(GV, *GV->getParent());
66 }
67 
68 unsigned char
69 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
70   // If we're not PIC, it's not very interesting.
71   if (!isPositionIndependent())
72     return X86II::MO_NO_FLAG;
73 
74   if (is64Bit()) {
75     // 64-bit ELF PIC local references may use GOTOFF relocations.
76     if (isTargetELF()) {
77       switch (TM.getCodeModel()) {
78       // 64-bit small code model is simple: All rip-relative.
79       case CodeModel::Tiny:
80         llvm_unreachable("Tiny codesize model not supported on X86");
81       case CodeModel::Small:
82       case CodeModel::Kernel:
83         return X86II::MO_NO_FLAG;
84 
85       // The large PIC code model uses GOTOFF.
86       case CodeModel::Large:
87         return X86II::MO_GOTOFF;
88 
89       // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data.
90       case CodeModel::Medium:
91         if (isa<Function>(GV))
92           return X86II::MO_NO_FLAG; // All code is RIP-relative
93         return X86II::MO_GOTOFF;    // Local symbols use GOTOFF.
94       }
95       llvm_unreachable("invalid code model");
96     }
97 
98     // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq,
99     // both of which use MO_NO_FLAG.
100     return X86II::MO_NO_FLAG;
101   }
102 
103   // The COFF dynamic linker just patches the executable sections.
104   if (isTargetCOFF())
105     return X86II::MO_NO_FLAG;
106 
107   if (isTargetDarwin()) {
108     // 32 bit macho has no relocation for a-b if a is undefined, even if
109     // b is in the section that is being relocated.
110     // This means we have to use o load even for GVs that are known to be
111     // local to the dso.
112     if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
113       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
114 
115     return X86II::MO_PIC_BASE_OFFSET;
116   }
117 
118   return X86II::MO_GOTOFF;
119 }
120 
121 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
122                                                     const Module &M) const {
123   // The static large model never uses stubs.
124   if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent())
125     return X86II::MO_NO_FLAG;
126 
127   // Absolute symbols can be referenced directly.
128   if (GV) {
129     if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
130       // See if we can use the 8-bit immediate form. Note that some instructions
131       // will sign extend the immediate operand, so to be conservative we only
132       // accept the range [0,128).
133       if (CR->getUnsignedMax().ult(128))
134         return X86II::MO_ABS8;
135       else
136         return X86II::MO_NO_FLAG;
137     }
138   }
139 
140   if (TM.shouldAssumeDSOLocal(M, GV))
141     return classifyLocalReference(GV);
142 
143   if (isTargetCOFF()) {
144     if (GV->hasDLLImportStorageClass())
145       return X86II::MO_DLLIMPORT;
146     return X86II::MO_COFFSTUB;
147   }
148   // Some JIT users use *-win32-elf triples; these shouldn't use GOT tables.
149   if (isOSWindows())
150     return X86II::MO_NO_FLAG;
151 
152   if (is64Bit()) {
153     // ELF supports a large, truly PIC code model with non-PC relative GOT
154     // references. Other object file formats do not. Use the no-flag, 64-bit
155     // reference for them.
156     if (TM.getCodeModel() == CodeModel::Large)
157       return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG;
158     return X86II::MO_GOTPCREL;
159   }
160 
161   if (isTargetDarwin()) {
162     if (!isPositionIndependent())
163       return X86II::MO_DARWIN_NONLAZY;
164     return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
165   }
166 
167   return X86II::MO_GOT;
168 }
169 
170 unsigned char
171 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
172   return classifyGlobalFunctionReference(GV, *GV->getParent());
173 }
174 
175 unsigned char
176 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
177                                               const Module &M) const {
178   if (TM.shouldAssumeDSOLocal(M, GV))
179     return X86II::MO_NO_FLAG;
180 
181   // Functions on COFF can be non-DSO local for two reasons:
182   // - They are marked dllimport
183   // - They are extern_weak, and a stub is needed
184   if (isTargetCOFF()) {
185     if (GV->hasDLLImportStorageClass())
186       return X86II::MO_DLLIMPORT;
187     return X86II::MO_COFFSTUB;
188   }
189 
190   const Function *F = dyn_cast_or_null<Function>(GV);
191 
192   if (isTargetELF()) {
193     if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
194       // According to psABI, PLT stub clobbers XMM8-XMM15.
195       // In Regcall calling convention those registers are used for passing
196       // parameters. Thus we need to prevent lazy binding in Regcall.
197       return X86II::MO_GOTPCREL;
198     // If PLT must be avoided then the call should be via GOTPCREL.
199     if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
200          (!F && M.getRtLibUseGOT())) &&
201         is64Bit())
202        return X86II::MO_GOTPCREL;
203     return X86II::MO_PLT;
204   }
205 
206   if (is64Bit()) {
207     if (F && F->hasFnAttribute(Attribute::NonLazyBind))
208       // If the function is marked as non-lazy, generate an indirect call
209       // which loads from the GOT directly. This avoids runtime overhead
210       // at the cost of eager binding (and one extra byte of encoding).
211       return X86II::MO_GOTPCREL;
212     return X86II::MO_NO_FLAG;
213   }
214 
215   return X86II::MO_NO_FLAG;
216 }
217 
218 /// Return true if the subtarget allows calls to immediate address.
219 bool X86Subtarget::isLegalToCallImmediateAddr() const {
220   // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
221   // but WinCOFFObjectWriter::RecordRelocation cannot emit them.  Once it does,
222   // the following check for Win32 should be removed.
223   if (In64BitMode || isTargetWin32())
224     return false;
225   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
226 }
227 
228 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
229   std::string CPUName = std::string(CPU);
230   if (CPUName.empty())
231     CPUName = "generic";
232 
233   std::string FullFS = std::string(FS);
234   if (In64BitMode) {
235     // SSE2 should default to enabled in 64-bit mode, but can be turned off
236     // explicitly.
237     if (!FullFS.empty())
238       FullFS = "+sse2," + FullFS;
239     else
240       FullFS = "+sse2";
241 
242     // If no CPU was specified, enable 64bit feature to satisy later check.
243     if (CPUName == "generic") {
244       if (!FullFS.empty())
245         FullFS = "+64bit," + FullFS;
246       else
247         FullFS = "+64bit";
248     }
249   }
250 
251   // LAHF/SAHF are always supported in non-64-bit mode.
252   if (!In64BitMode) {
253     if (!FullFS.empty())
254       FullFS = "+sahf," + FullFS;
255     else
256       FullFS = "+sahf";
257   }
258 
259   // Parse features string and set the CPU.
260   ParseSubtargetFeatures(CPUName, FullFS);
261 
262   // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
263   // 16-bytes and under that are reasonably fast. These features were
264   // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
265   // micro-architectures respectively.
266   if (hasSSE42() || hasSSE4A())
267     IsUAMem16Slow = false;
268 
269   // It's important to keep the MCSubtargetInfo feature bits in sync with
270   // target data structure which is shared with MC code emitter, etc.
271   if (In64BitMode)
272     ToggleFeature(X86::Mode64Bit);
273   else if (In32BitMode)
274     ToggleFeature(X86::Mode32Bit);
275   else if (In16BitMode)
276     ToggleFeature(X86::Mode16Bit);
277   else
278     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
279 
280   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
281                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
282                     << HasX86_64 << "\n");
283   if (In64BitMode && !HasX86_64)
284     report_fatal_error("64-bit code requested on a subtarget that doesn't "
285                        "support it!");
286 
287   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
288   // 32 and 64 bit) and for all 64-bit targets.
289   if (StackAlignOverride)
290     stackAlignment = *StackAlignOverride;
291   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
292            isTargetKFreeBSD() || In64BitMode)
293     stackAlignment = Align(16);
294 
295   // Some CPUs have more overhead for gather. The specified overhead is relative
296   // to the Load operation. "2" is the number provided by Intel architects. This
297   // parameter is used for cost estimation of Gather Op and comparison with
298   // other alternatives.
299   // TODO: Remove the explicit hasAVX512()?, That would mean we would only
300   // enable gather with a -march.
301   if (hasAVX512() || (hasAVX2() && hasFastGather()))
302     GatherOverhead = 2;
303   if (hasAVX512())
304     ScatterOverhead = 2;
305 
306   // Consume the vector width attribute or apply any target specific limit.
307   if (PreferVectorWidthOverride)
308     PreferVectorWidth = PreferVectorWidthOverride;
309   else if (Prefer128Bit)
310     PreferVectorWidth = 128;
311   else if (Prefer256Bit)
312     PreferVectorWidth = 256;
313 }
314 
315 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
316                                                             StringRef FS) {
317   initSubtargetFeatures(CPU, FS);
318   return *this;
319 }
320 
321 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
322                            const X86TargetMachine &TM,
323                            MaybeAlign StackAlignOverride,
324                            unsigned PreferVectorWidthOverride,
325                            unsigned RequiredVectorWidth)
326     : X86GenSubtargetInfo(TT, CPU, FS), PICStyle(PICStyles::Style::None),
327       TM(TM), TargetTriple(TT), StackAlignOverride(StackAlignOverride),
328       PreferVectorWidthOverride(PreferVectorWidthOverride),
329       RequiredVectorWidth(RequiredVectorWidth),
330       In64BitMode(TargetTriple.getArch() == Triple::x86_64),
331       In32BitMode(TargetTriple.getArch() == Triple::x86 &&
332                   TargetTriple.getEnvironment() != Triple::CODE16),
333       In16BitMode(TargetTriple.getArch() == Triple::x86 &&
334                   TargetTriple.getEnvironment() == Triple::CODE16),
335       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
336       FrameLowering(*this, getStackAlignment()) {
337   // Determine the PICStyle based on the target selected.
338   if (!isPositionIndependent())
339     setPICStyle(PICStyles::Style::None);
340   else if (is64Bit())
341     setPICStyle(PICStyles::Style::RIPRel);
342   else if (isTargetCOFF())
343     setPICStyle(PICStyles::Style::None);
344   else if (isTargetDarwin())
345     setPICStyle(PICStyles::Style::StubPIC);
346   else if (isTargetELF())
347     setPICStyle(PICStyles::Style::GOT);
348 
349   CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
350   Legalizer.reset(new X86LegalizerInfo(*this, TM));
351 
352   auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
353   RegBankInfo.reset(RBI);
354   InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
355 }
356 
357 const CallLowering *X86Subtarget::getCallLowering() const {
358   return CallLoweringInfo.get();
359 }
360 
361 InstructionSelector *X86Subtarget::getInstructionSelector() const {
362   return InstSelector.get();
363 }
364 
365 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
366   return Legalizer.get();
367 }
368 
369 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
370   return RegBankInfo.get();
371 }
372 
373 bool X86Subtarget::enableEarlyIfConversion() const {
374   return hasCMov() && X86EarlyIfConv;
375 }
376 
377 void X86Subtarget::getPostRAMutations(
378     std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
379   Mutations.push_back(createX86MacroFusionDAGMutation());
380 }
381 
382 bool X86Subtarget::isPositionIndependent() const {
383   return TM.isPositionIndependent();
384 }
385