1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Host.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetOptions.h"
26 
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "X86GenSubtargetInfo.inc"
30 
31 using namespace llvm;
32 
33 #if defined(_MSC_VER)
34 #include <intrin.h>
35 #endif
36 
37 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
38 /// current subtarget according to how we should reference it in a non-pcrel
39 /// context.
40 unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
41   if (isPICStyleGOT())    // 32-bit ELF targets.
42     return X86II::MO_GOTOFF;
43 
44   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
45     return X86II::MO_PIC_BASE_OFFSET;
46 
47   // Direct static reference to label.
48   return X86II::MO_NO_FLAG;
49 }
50 
51 /// ClassifyGlobalReference - Classify a global variable reference for the
52 /// current subtarget according to how we should reference it in a non-pcrel
53 /// context.
54 unsigned char X86Subtarget::
55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56   // DLLImport only exists on windows, it is implemented as a load from a
57   // DLLIMPORT stub.
58   if (GV->hasDLLImportStorageClass())
59     return X86II::MO_DLLIMPORT;
60 
61   // Determine whether this is a reference to a definition or a declaration.
62   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63   // load from stub.
64   bool isDecl = GV->hasAvailableExternallyLinkage();
65   if (GV->isDeclaration() && !GV->isMaterializable())
66     isDecl = true;
67 
68   // X86-64 in PIC mode.
69   if (isPICStyleRIPRel()) {
70     // Large model never uses stubs.
71     if (TM.getCodeModel() == CodeModel::Large)
72       return X86II::MO_NO_FLAG;
73 
74     if (isTargetDarwin()) {
75       // If symbol visibility is hidden, the extra load is not needed if
76       // target is x86-64 or the symbol is definitely defined in the current
77       // translation unit.
78       if (GV->hasDefaultVisibility() &&
79           (isDecl || GV->isWeakForLinker()))
80         return X86II::MO_GOTPCREL;
81     } else if (!isTargetWin64()) {
82       assert(isTargetELF() && "Unknown rip-relative target");
83 
84       // Extra load is needed for all externally visible.
85       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86         return X86II::MO_GOTPCREL;
87     }
88 
89     return X86II::MO_NO_FLAG;
90   }
91 
92   if (isPICStyleGOT()) {   // 32-bit ELF targets.
93     // Extra load is needed for all externally visible.
94     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95       return X86II::MO_GOTOFF;
96     return X86II::MO_GOT;
97   }
98 
99   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
100     // Determine whether we have a stub reference and/or whether the reference
101     // is relative to the PIC base or not.
102 
103     // If this is a strong reference to a definition, it is definitely not
104     // through a stub.
105     if (!isDecl && !GV->isWeakForLinker())
106       return X86II::MO_PIC_BASE_OFFSET;
107 
108     // Unless we have a symbol with hidden visibility, we have to go through a
109     // normal $non_lazy_ptr stub because this symbol might be resolved late.
110     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
111       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112 
113     // If symbol visibility is hidden, we have a stub for common symbol
114     // references and external declarations.
115     if (isDecl || GV->hasCommonLinkage()) {
116       // Hidden $non_lazy_ptr reference.
117       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
118     }
119 
120     // Otherwise, no stub.
121     return X86II::MO_PIC_BASE_OFFSET;
122   }
123 
124   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
125     // Determine whether we have a stub reference.
126 
127     // If this is a strong reference to a definition, it is definitely not
128     // through a stub.
129     if (!isDecl && !GV->isWeakForLinker())
130       return X86II::MO_NO_FLAG;
131 
132     // Unless we have a symbol with hidden visibility, we have to go through a
133     // normal $non_lazy_ptr stub because this symbol might be resolved late.
134     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
135       return X86II::MO_DARWIN_NONLAZY;
136 
137     // Otherwise, no stub.
138     return X86II::MO_NO_FLAG;
139   }
140 
141   // Direct static reference to global.
142   return X86II::MO_NO_FLAG;
143 }
144 
145 
146 /// getBZeroEntry - This function returns the name of a function which has an
147 /// interface like the non-standard bzero function, if such a function exists on
148 /// the current subtarget and it is considered prefereable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151   // Darwin 10 has a __bzero entry point for this purpose.
152   if (getTargetTriple().isMacOSX() &&
153       !getTargetTriple().isMacOSXVersionLT(10, 6))
154     return "__bzero";
155 
156   return 0;
157 }
158 
159 bool X86Subtarget::hasSinCos() const {
160   return getTargetTriple().isMacOSX() &&
161     !getTargetTriple().isMacOSXVersionLT(10, 9) &&
162     is64Bit();
163 }
164 
165 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
166 /// to immediate address.
167 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
168   if (In64BitMode)
169     return false;
170   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
171 }
172 
173 static bool OSHasAVXSupport() {
174 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
175     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
176 #if defined(__GNUC__)
177   // Check xgetbv; this uses a .byte sequence instead of the instruction
178   // directly because older assemblers do not include support for xgetbv and
179   // there is no easy way to conditionally compile based on the assembler used.
180   int rEAX, rEDX;
181   __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
182 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
183   unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
184 #else
185   int rEAX = 0; // Ensures we return false
186 #endif
187   return (rEAX & 6) == 6;
188 #else
189   return false;
190 #endif
191 }
192 
193 void X86Subtarget::AutoDetectSubtargetFeatures() {
194   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
195   unsigned MaxLevel;
196   union {
197     unsigned u[3];
198     char     c[12];
199   } text;
200 
201   if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
202       MaxLevel < 1)
203     return;
204 
205   X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
206 
207   if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
208   if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
209   if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
210   if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
211   if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
212   if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
213   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
214   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
215   if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
216     X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX);
217   }
218 
219   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
220   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
221 
222   if ((ECX >> 1) & 0x1) {
223     HasPCLMUL = true;
224     ToggleFeature(X86::FeaturePCLMUL);
225   }
226   if ((ECX >> 12) & 0x1) {
227     HasFMA = true;
228     ToggleFeature(X86::FeatureFMA);
229   }
230   if (IsIntel && ((ECX >> 22) & 0x1)) {
231     HasMOVBE = true;
232     ToggleFeature(X86::FeatureMOVBE);
233   }
234   if ((ECX >> 23) & 0x1) {
235     HasPOPCNT = true;
236     ToggleFeature(X86::FeaturePOPCNT);
237   }
238   if ((ECX >> 25) & 0x1) {
239     HasAES = true;
240     ToggleFeature(X86::FeatureAES);
241   }
242   if ((ECX >> 29) & 0x1) {
243     HasF16C = true;
244     ToggleFeature(X86::FeatureF16C);
245   }
246   if (IsIntel && ((ECX >> 30) & 0x1)) {
247     HasRDRAND = true;
248     ToggleFeature(X86::FeatureRDRAND);
249   }
250 
251   if ((ECX >> 13) & 0x1) {
252     HasCmpxchg16b = true;
253     ToggleFeature(X86::FeatureCMPXCHG16B);
254   }
255 
256   if (IsIntel || IsAMD) {
257     // Determine if bit test memory instructions are slow.
258     unsigned Family = 0;
259     unsigned Model  = 0;
260     X86_MC::DetectFamilyModel(EAX, Family, Model);
261     if (IsAMD || (Family == 6 && Model >= 13)) {
262       IsBTMemSlow = true;
263       ToggleFeature(X86::FeatureSlowBTMem);
264     }
265 
266     // Determine if SHLD/SHRD instructions have higher latency then the
267     // equivalent series of shifts/or instructions.
268     // FIXME: Add Intel's processors that have SHLD instructions with very
269     // poor latency.
270     if (IsAMD) {
271       IsSHLDSlow = true;
272       ToggleFeature(X86::FeatureSlowSHLD);
273     }
274 
275     // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
276     // memory access is fast. We hard code model numbers here because they
277     // aren't strictly increasing for Intel chips it seems.
278     if (IsIntel &&
279         ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
280                                            //          Jasper Froest
281          (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
282          (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
283          (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
284          (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
285          (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
286          (Family == 6 && Model == 0x2A) || // SandyBridge
287          (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
288          (Family == 6 && Model == 0x3A) || // IvyBridge
289          (Family == 6 && Model == 0x3E) || // IvyBridge EP
290          (Family == 6 && Model == 0x3C) || // Haswell
291          (Family == 6 && Model == 0x3F) || // ...
292          (Family == 6 && Model == 0x45) || // ...
293          (Family == 6 && Model == 0x46))) { // ...
294       IsUAMemFast = true;
295       ToggleFeature(X86::FeatureFastUAMem);
296     }
297 
298     // Set processor type. Currently only Atom or Silvermont (SLM) is detected.
299     if (Family == 6 &&
300         (Model == 28 || Model == 38 || Model == 39 ||
301          Model == 53 || Model == 54)) {
302       X86ProcFamily = IntelAtom;
303 
304       UseLeaForSP = true;
305       ToggleFeature(X86::FeatureLeaForSP);
306     }
307     else if (Family == 6 &&
308         (Model == 55 || Model == 74 || Model == 77)) {
309       X86ProcFamily = IntelSLM;
310     }
311 
312     unsigned MaxExtLevel;
313     X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
314 
315     if (MaxExtLevel >= 0x80000001) {
316       X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
317       if ((EDX >> 29) & 0x1) {
318         HasX86_64 = true;
319         ToggleFeature(X86::Feature64Bit);
320       }
321       if ((ECX >> 5) & 0x1) {
322         HasLZCNT = true;
323         ToggleFeature(X86::FeatureLZCNT);
324       }
325       if (IsIntel && ((ECX >> 8) & 0x1)) {
326         HasPRFCHW = true;
327         ToggleFeature(X86::FeaturePRFCHW);
328       }
329       if (IsAMD) {
330         if ((ECX >> 6) & 0x1) {
331           HasSSE4A = true;
332           ToggleFeature(X86::FeatureSSE4A);
333         }
334         if ((ECX >> 11) & 0x1) {
335           HasXOP = true;
336           ToggleFeature(X86::FeatureXOP);
337         }
338         if ((ECX >> 16) & 0x1) {
339           HasFMA4 = true;
340           ToggleFeature(X86::FeatureFMA4);
341         }
342       }
343     }
344   }
345 
346   if (MaxLevel >= 7) {
347     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
348       if (IsIntel && (EBX & 0x1)) {
349         HasFSGSBase = true;
350         ToggleFeature(X86::FeatureFSGSBase);
351       }
352       if ((EBX >> 3) & 0x1) {
353         HasBMI = true;
354         ToggleFeature(X86::FeatureBMI);
355       }
356       if ((EBX >> 4) & 0x1) {
357         HasHLE = true;
358         ToggleFeature(X86::FeatureHLE);
359       }
360       if (IsIntel && ((EBX >> 5) & 0x1)) {
361         X86SSELevel = AVX2;
362         ToggleFeature(X86::FeatureAVX2);
363       }
364       if (IsIntel && ((EBX >> 8) & 0x1)) {
365         HasBMI2 = true;
366         ToggleFeature(X86::FeatureBMI2);
367       }
368       if (IsIntel && ((EBX >> 11) & 0x1)) {
369         HasRTM = true;
370         ToggleFeature(X86::FeatureRTM);
371       }
372       if (IsIntel && ((EBX >> 16) & 0x1)) {
373         X86SSELevel = AVX512F;
374         ToggleFeature(X86::FeatureAVX512);
375       }
376       if (IsIntel && ((EBX >> 18) & 0x1)) {
377         HasRDSEED = true;
378         ToggleFeature(X86::FeatureRDSEED);
379       }
380       if (IsIntel && ((EBX >> 19) & 0x1)) {
381         HasADX = true;
382         ToggleFeature(X86::FeatureADX);
383       }
384       if (IsIntel && ((EBX >> 26) & 0x1)) {
385         HasPFI = true;
386         ToggleFeature(X86::FeaturePFI);
387       }
388       if (IsIntel && ((EBX >> 27) & 0x1)) {
389         HasERI = true;
390         ToggleFeature(X86::FeatureERI);
391       }
392       if (IsIntel && ((EBX >> 28) & 0x1)) {
393         HasCDI = true;
394         ToggleFeature(X86::FeatureCDI);
395       }
396       if (IsIntel && ((EBX >> 29) & 0x1)) {
397         HasSHA = true;
398         ToggleFeature(X86::FeatureSHA);
399       }
400     }
401     if (IsAMD && ((ECX >> 21) & 0x1)) {
402       HasTBM = true;
403       ToggleFeature(X86::FeatureTBM);
404     }
405   }
406 }
407 
408 void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
409   AttributeSet FnAttrs = MF->getFunction()->getAttributes();
410   Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
411                                            "target-cpu");
412   Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
413                                           "target-features");
414   std::string CPU =
415     !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
416   std::string FS =
417     !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
418   if (!FS.empty()) {
419     initializeEnvironment();
420     resetSubtargetFeatures(CPU, FS);
421   }
422 }
423 
424 void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
425   std::string CPUName = CPU;
426   if (!FS.empty() || !CPU.empty()) {
427     if (CPUName.empty()) {
428 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
429     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
430       CPUName = sys::getHostCPUName();
431 #else
432       CPUName = "generic";
433 #endif
434     }
435 
436     // Make sure 64-bit features are available in 64-bit mode. (But make sure
437     // SSE2 can be turned off explicitly.)
438     std::string FullFS = FS;
439     if (In64BitMode) {
440       if (!FullFS.empty())
441         FullFS = "+64bit,+sse2," + FullFS;
442       else
443         FullFS = "+64bit,+sse2";
444     }
445 
446     // If feature string is not empty, parse features string.
447     ParseSubtargetFeatures(CPUName, FullFS);
448   } else {
449     if (CPUName.empty()) {
450 #if defined (__x86_64__) || defined(__i386__)
451       CPUName = sys::getHostCPUName();
452 #else
453       CPUName = "generic";
454 #endif
455     }
456     // Otherwise, use CPUID to auto-detect feature set.
457     AutoDetectSubtargetFeatures();
458 
459     // Make sure 64-bit features are available in 64-bit mode.
460     if (In64BitMode) {
461       if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
462       if (!HasCMov)   { HasCMov   = true; ToggleFeature(X86::FeatureCMOV); }
463 
464       if (X86SSELevel < SSE2) {
465         X86SSELevel = SSE2;
466         ToggleFeature(X86::FeatureSSE1);
467         ToggleFeature(X86::FeatureSSE2);
468       }
469     }
470   }
471 
472   // CPUName may have been set by the CPU detection code. Make sure the
473   // new MCSchedModel is used.
474   InitCPUSchedModel(CPUName);
475 
476   if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
477     PostRAScheduler = true;
478 
479   InstrItins = getInstrItineraryForCPU(CPUName);
480 
481   // It's important to keep the MCSubtargetInfo feature bits in sync with
482   // target data structure which is shared with MC code emitter, etc.
483   if (In64BitMode)
484     ToggleFeature(X86::Mode64Bit);
485   else if (In32BitMode)
486     ToggleFeature(X86::Mode32Bit);
487   else if (In16BitMode)
488     ToggleFeature(X86::Mode16Bit);
489   else
490     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
491 
492   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
493                << ", 3DNowLevel " << X863DNowLevel
494                << ", 64bit " << HasX86_64 << "\n");
495   assert((!In64BitMode || HasX86_64) &&
496          "64-bit code requested on a subtarget that doesn't support it!");
497 
498   // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
499   // 32 and 64 bit) and for all 64-bit targets.
500   if (StackAlignOverride)
501     stackAlignment = StackAlignOverride;
502   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
503            In64BitMode)
504     stackAlignment = 16;
505 }
506 
507 void X86Subtarget::initializeEnvironment() {
508   X86SSELevel = NoMMXSSE;
509   X863DNowLevel = NoThreeDNow;
510   HasCMov = false;
511   HasX86_64 = false;
512   HasPOPCNT = false;
513   HasSSE4A = false;
514   HasAES = false;
515   HasPCLMUL = false;
516   HasFMA = false;
517   HasFMA4 = false;
518   HasXOP = false;
519   HasTBM = false;
520   HasMOVBE = false;
521   HasRDRAND = false;
522   HasF16C = false;
523   HasFSGSBase = false;
524   HasLZCNT = false;
525   HasBMI = false;
526   HasBMI2 = false;
527   HasRTM = false;
528   HasHLE = false;
529   HasERI = false;
530   HasCDI = false;
531   HasPFI = false;
532   HasADX = false;
533   HasSHA = false;
534   HasPRFCHW = false;
535   HasRDSEED = false;
536   IsBTMemSlow = false;
537   IsSHLDSlow = false;
538   IsUAMemFast = false;
539   HasVectorUAMem = false;
540   HasCmpxchg16b = false;
541   UseLeaForSP = false;
542   HasSlowDivide = false;
543   PostRAScheduler = false;
544   PadShortFunctions = false;
545   CallRegIndirect = false;
546   LEAUsesAG = false;
547   stackAlignment = 4;
548   // FIXME: this is a known good value for Yonah. How about others?
549   MaxInlineSizeThreshold = 128;
550 }
551 
552 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
553                            const std::string &FS,
554                            unsigned StackAlignOverride)
555   : X86GenSubtargetInfo(TT, CPU, FS)
556   , X86ProcFamily(Others)
557   , PICStyle(PICStyles::None)
558   , TargetTriple(TT)
559   , StackAlignOverride(StackAlignOverride)
560   , In64BitMode(TargetTriple.getArch() == Triple::x86_64)
561   , In32BitMode(TargetTriple.getArch() == Triple::x86 &&
562                 TargetTriple.getEnvironment() != Triple::CODE16)
563   , In16BitMode(TargetTriple.getArch() == Triple::x86 &&
564                 TargetTriple.getEnvironment() == Triple::CODE16) {
565   initializeEnvironment();
566   resetSubtargetFeatures(CPU, FS);
567 }
568 
569 bool X86Subtarget::enablePostRAScheduler(
570            CodeGenOpt::Level OptLevel,
571            TargetSubtargetInfo::AntiDepBreakMode& Mode,
572            RegClassVector& CriticalPathRCs) const {
573   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
574   CriticalPathRCs.clear();
575   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
576 }
577