1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 using namespace llvm;
23 
24 #if defined(_MSC_VER)
25     #include <intrin.h>
26 #endif
27 
28 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
30   cl::desc("Choose style of code to emit from X86 backend:"),
31   cl::values(
32     clEnumValN(X86Subtarget::ATT,   "att",   "Emit AT&T-style assembly"),
33     clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
34     clEnumValEnd));
35 
36 
37 /// True if accessing the GV requires an extra load. For Windows, dllimported
38 /// symbols are indirect, loading the value at address GV rather then the
39 /// value of GV itself. This means that the GlobalAddress must be in the base
40 /// or index register of the address, not the GV offset field.
41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
42                                        const TargetMachine& TM,
43                                        bool isDirectCall) const
44 {
45   // FIXME: PIC
46   if (TM.getRelocationModel() != Reloc::Static &&
47       TM.getCodeModel() != CodeModel::Large) {
48     if (isTargetDarwin()) {
49       if (isDirectCall)
50         return false;
51       bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
52       if (GV->hasHiddenVisibility() &&
53           (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
54         // If symbol visibility is hidden, the extra load is not needed if
55         // target is x86-64 or the symbol is definitely defined in the current
56         // translation unit.
57         return false;
58       return !isDirectCall && (isDecl || GV->isWeakForLinker());
59     } else if (isTargetELF()) {
60       // Extra load is needed for all externally visible.
61       if (isDirectCall)
62         return false;
63       if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
64         return false;
65       return true;
66     } else if (isTargetCygMing() || isTargetWindows()) {
67       return (GV->hasDLLImportLinkage());
68     }
69   }
70   return false;
71 }
72 
73 /// True if accessing the GV requires a register.  This is a superset of the
74 /// cases where GVRequiresExtraLoad is true.  Some variations of PIC require
75 /// a register, but not an extra load.
76 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
77                                       const TargetMachine& TM,
78                                       bool isDirectCall) const
79 {
80   if (GVRequiresExtraLoad(GV, TM, isDirectCall))
81     return true;
82   // Code below here need only consider cases where GVRequiresExtraLoad
83   // returns false.
84   if (TM.getRelocationModel() == Reloc::PIC_)
85     return !isDirectCall &&
86       (GV->hasLocalLinkage() || GV->hasExternalLinkage());
87   return false;
88 }
89 
90 /// getBZeroEntry - This function returns the name of a function which has an
91 /// interface like the non-standard bzero function, if such a function exists on
92 /// the current subtarget and it is considered prefereable over memset with zero
93 /// passed as the second argument. Otherwise it returns null.
94 const char *X86Subtarget::getBZeroEntry() const {
95   // Darwin 10 has a __bzero entry point for this purpose.
96   if (getDarwinVers() >= 10)
97     return "__bzero";
98 
99   return 0;
100 }
101 
102 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
103 /// to immediate address.
104 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
105   if (Is64Bit)
106     return false;
107   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
108 }
109 
110 /// getSpecialAddressLatency - For targets where it is beneficial to
111 /// backschedule instructions that compute addresses, return a value
112 /// indicating the number of scheduling cycles of backscheduling that
113 /// should be attempted.
114 unsigned X86Subtarget::getSpecialAddressLatency() const {
115   // For x86 out-of-order targets, back-schedule address computations so
116   // that loads and stores aren't blocked.
117   // This value was chosen arbitrarily.
118   return 200;
119 }
120 
121 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
122 /// specified arguments.  If we can't run cpuid on the host, return true.
123 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
124                           unsigned *rECX, unsigned *rEDX) {
125 #if defined(__x86_64__) || defined(_M_AMD64)
126   #if defined(__GNUC__)
127     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
128     asm ("movq\t%%rbx, %%rsi\n\t"
129          "cpuid\n\t"
130          "xchgq\t%%rbx, %%rsi\n\t"
131          : "=a" (*rEAX),
132            "=S" (*rEBX),
133            "=c" (*rECX),
134            "=d" (*rEDX)
135          :  "a" (value));
136     return false;
137   #elif defined(_MSC_VER)
138     int registers[4];
139     __cpuid(registers, value);
140     *rEAX = registers[0];
141     *rEBX = registers[1];
142     *rECX = registers[2];
143     *rEDX = registers[3];
144     return false;
145   #endif
146 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
147   #if defined(__GNUC__)
148     asm ("movl\t%%ebx, %%esi\n\t"
149          "cpuid\n\t"
150          "xchgl\t%%ebx, %%esi\n\t"
151          : "=a" (*rEAX),
152            "=S" (*rEBX),
153            "=c" (*rECX),
154            "=d" (*rEDX)
155          :  "a" (value));
156     return false;
157   #elif defined(_MSC_VER)
158     __asm {
159       mov   eax,value
160       cpuid
161       mov   esi,rEAX
162       mov   dword ptr [esi],eax
163       mov   esi,rEBX
164       mov   dword ptr [esi],ebx
165       mov   esi,rECX
166       mov   dword ptr [esi],ecx
167       mov   esi,rEDX
168       mov   dword ptr [esi],edx
169     }
170     return false;
171   #endif
172 #endif
173   return true;
174 }
175 
176 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
177   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
178   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
179   if (Family == 6 || Family == 0xf) {
180     if (Family == 0xf)
181       // Examine extended family ID if family ID is F.
182       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
183     // Examine extended model ID if family ID is 6 or F.
184     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
185   }
186 }
187 
188 void X86Subtarget::AutoDetectSubtargetFeatures() {
189   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
190   union {
191     unsigned u[3];
192     char     c[12];
193   } text;
194 
195   if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
196     return;
197 
198   X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
199 
200   if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
201   if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
202   if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
203   if (ECX & 0x1)         X86SSELevel = SSE3;
204   if ((ECX >> 9)  & 0x1) X86SSELevel = SSSE3;
205   if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
206   if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
207 
208   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
209   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
210 
211   HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
212   HasAVX = ((ECX >> 28) & 0x1);
213 
214   if (IsIntel || IsAMD) {
215     // Determine if bit test memory instructions are slow.
216     unsigned Family = 0;
217     unsigned Model  = 0;
218     DetectFamilyModel(EAX, Family, Model);
219     IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
220 
221     X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
222     HasX86_64 = (EDX >> 29) & 0x1;
223     HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
224     HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
225   }
226 }
227 
228 static const char *GetCurrentX86CPU() {
229   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
230   if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
231     return "generic";
232   unsigned Family = 0;
233   unsigned Model  = 0;
234   DetectFamilyModel(EAX, Family, Model);
235 
236   X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
237   bool Em64T = (EDX >> 29) & 0x1;
238   bool HasSSE3 = (ECX & 0x1);
239 
240   union {
241     unsigned u[3];
242     char     c[12];
243   } text;
244 
245   X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
246   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
247     switch (Family) {
248       case 3:
249         return "i386";
250       case 4:
251         return "i486";
252       case 5:
253         switch (Model) {
254         case 4:  return "pentium-mmx";
255         default: return "pentium";
256         }
257       case 6:
258         switch (Model) {
259         case 1:  return "pentiumpro";
260         case 3:
261         case 5:
262         case 6:  return "pentium2";
263         case 7:
264         case 8:
265         case 10:
266         case 11: return "pentium3";
267         case 9:
268         case 13: return "pentium-m";
269         case 14: return "yonah";
270         case 15:
271         case 22: // Celeron M 540
272           return "core2";
273         case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
274           return "penryn";
275         default: return "i686";
276         }
277       case 15: {
278         switch (Model) {
279         case 3:
280         case 4:
281         case 6: // same as 4, but 65nm
282           return (Em64T) ? "nocona" : "prescott";
283         case 26:
284           return "corei7";
285         case 28:
286           return "atom";
287         default:
288           return (Em64T) ? "x86-64" : "pentium4";
289         }
290       }
291 
292     default:
293       return "generic";
294     }
295   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
296     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
297     // appears to be no way to generate the wide variety of AMD-specific targets
298     // from the information returned from CPUID.
299     switch (Family) {
300       case 4:
301         return "i486";
302       case 5:
303         switch (Model) {
304         case 6:
305         case 7:  return "k6";
306         case 8:  return "k6-2";
307         case 9:
308         case 13: return "k6-3";
309         default: return "pentium";
310         }
311       case 6:
312         switch (Model) {
313         case 4:  return "athlon-tbird";
314         case 6:
315         case 7:
316         case 8:  return "athlon-mp";
317         case 10: return "athlon-xp";
318         default: return "athlon";
319         }
320       case 15:
321         if (HasSSE3) {
322           switch (Model) {
323           default: return "k8-sse3";
324           }
325         } else {
326           switch (Model) {
327           case 1:  return "opteron";
328           case 5:  return "athlon-fx"; // also opteron
329           default: return "athlon64";
330           }
331         }
332       case 16:
333         switch (Model) {
334         default: return "amdfam10";
335         }
336     default:
337       return "generic";
338     }
339   } else {
340     return "generic";
341   }
342 }
343 
344 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
345   : AsmFlavor(AsmWriterFlavor)
346   , PICStyle(PICStyles::None)
347   , X86SSELevel(NoMMXSSE)
348   , X863DNowLevel(NoThreeDNow)
349   , HasX86_64(false)
350   , HasSSE4A(false)
351   , HasAVX(false)
352   , HasFMA3(false)
353   , HasFMA4(false)
354   , IsBTMemSlow(false)
355   , DarwinVers(0)
356   , IsLinux(false)
357   , stackAlignment(8)
358   // FIXME: this is a known good value for Yonah. How about others?
359   , MaxInlineSizeThreshold(128)
360   , Is64Bit(is64Bit)
361   , TargetType(isELF) { // Default to ELF unless otherwise specified.
362 
363   // default to hard float ABI
364   if (FloatABIType == FloatABI::Default)
365     FloatABIType = FloatABI::Hard;
366 
367   // Determine default and user specified characteristics
368   if (!FS.empty()) {
369     // If feature string is not empty, parse features string.
370     std::string CPU = GetCurrentX86CPU();
371     ParseSubtargetFeatures(FS, CPU);
372     // All X86-64 CPUs also have SSE2, however user might request no SSE via
373     // -mattr, so don't force SSELevel here.
374   } else {
375     // Otherwise, use CPUID to auto-detect feature set.
376     AutoDetectSubtargetFeatures();
377     // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
378     if (Is64Bit && X86SSELevel < SSE2)
379       X86SSELevel = SSE2;
380   }
381 
382   // If requesting codegen for X86-64, make sure that 64-bit features
383   // are enabled.
384   if (Is64Bit)
385     HasX86_64 = true;
386 
387   DOUT << "Subtarget features: SSELevel " << X86SSELevel
388        << ", 3DNowLevel " << X863DNowLevel
389        << ", 64bit " << HasX86_64 << "\n";
390   assert((!Is64Bit || HasX86_64) &&
391          "64-bit code requested on a subtarget that doesn't support it!");
392 
393   // Set the boolean corresponding to the current target triple, or the default
394   // if one cannot be determined, to true.
395   const std::string& TT = M.getTargetTriple();
396   if (TT.length() > 5) {
397     size_t Pos;
398     if ((Pos = TT.find("-darwin")) != std::string::npos) {
399       TargetType = isDarwin;
400 
401       // Compute the darwin version number.
402       if (isdigit(TT[Pos+7]))
403         DarwinVers = atoi(&TT[Pos+7]);
404       else
405         DarwinVers = 8;  // Minimum supported darwin is Tiger.
406     } else if (TT.find("linux") != std::string::npos) {
407       // Linux doesn't imply ELF, but we don't currently support anything else.
408       TargetType = isELF;
409       IsLinux = true;
410     } else if (TT.find("cygwin") != std::string::npos) {
411       TargetType = isCygwin;
412     } else if (TT.find("mingw") != std::string::npos) {
413       TargetType = isMingw;
414     } else if (TT.find("win32") != std::string::npos) {
415       TargetType = isWindows;
416     } else if (TT.find("windows") != std::string::npos) {
417       TargetType = isWindows;
418     }
419     else if (TT.find("-cl") != std::string::npos) {
420       TargetType = isDarwin;
421       DarwinVers = 9;
422     }
423   } else if (TT.empty()) {
424 #if defined(__CYGWIN__)
425     TargetType = isCygwin;
426 #elif defined(__MINGW32__) || defined(__MINGW64__)
427     TargetType = isMingw;
428 #elif defined(__APPLE__)
429     TargetType = isDarwin;
430 #if __APPLE_CC__ > 5400
431     DarwinVers = 9;  // GCC 5400+ is Leopard.
432 #else
433     DarwinVers = 8;  // Minimum supported darwin is Tiger.
434 #endif
435 
436 #elif defined(_WIN32) || defined(_WIN64)
437     TargetType = isWindows;
438 #elif defined(__linux__)
439     // Linux doesn't imply ELF, but we don't currently support anything else.
440     TargetType = isELF;
441     IsLinux = true;
442 #endif
443   }
444 
445   // If the asm syntax hasn't been overridden on the command line, use whatever
446   // the target wants.
447   if (AsmFlavor == X86Subtarget::Unset) {
448     AsmFlavor = (TargetType == isWindows)
449       ? X86Subtarget::Intel : X86Subtarget::ATT;
450   }
451 
452   // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
453   // bit targets.
454   if (TargetType == isDarwin || Is64Bit)
455     stackAlignment = 16;
456 
457   if (StackAlignment)
458     stackAlignment = StackAlignment;
459 }
460