1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the X86 specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "subtarget" 15 #include "X86Subtarget.h" 16 #include "X86GenSubtarget.inc" 17 #include "llvm/Module.h" 18 #include "llvm/Support/CommandLine.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include "llvm/Target/TargetOptions.h" 22 using namespace llvm; 23 24 #if defined(_MSC_VER) 25 #include <intrin.h> 26 #endif 27 28 static cl::opt<X86Subtarget::AsmWriterFlavorTy> 29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset), 30 cl::desc("Choose style of code to emit from X86 backend:"), 31 cl::values( 32 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"), 33 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"), 34 clEnumValEnd)); 35 36 37 /// True if accessing the GV requires an extra load. For Windows, dllimported 38 /// symbols are indirect, loading the value at address GV rather then the 39 /// value of GV itself. This means that the GlobalAddress must be in the base 40 /// or index register of the address, not the GV offset field. 41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV, 42 const TargetMachine& TM, 43 bool isDirectCall) const 44 { 45 // FIXME: PIC 46 if (TM.getRelocationModel() != Reloc::Static && 47 TM.getCodeModel() != CodeModel::Large) { 48 if (isTargetDarwin()) { 49 if (isDirectCall) 50 return false; 51 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode(); 52 if (GV->hasHiddenVisibility() && 53 (Is64Bit || (!isDecl && !GV->hasCommonLinkage()))) 54 // If symbol visibility is hidden, the extra load is not needed if 55 // target is x86-64 or the symbol is definitely defined in the current 56 // translation unit. 57 return false; 58 return !isDirectCall && (isDecl || GV->isWeakForLinker()); 59 } else if (isTargetELF()) { 60 // Extra load is needed for all externally visible. 61 if (isDirectCall) 62 return false; 63 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility()) 64 return false; 65 return true; 66 } else if (isTargetCygMing() || isTargetWindows()) { 67 return (GV->hasDLLImportLinkage()); 68 } 69 } 70 return false; 71 } 72 73 /// True if accessing the GV requires a register. This is a superset of the 74 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require 75 /// a register, but not an extra load. 76 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV, 77 const TargetMachine& TM, 78 bool isDirectCall) const 79 { 80 if (GVRequiresExtraLoad(GV, TM, isDirectCall)) 81 return true; 82 // Code below here need only consider cases where GVRequiresExtraLoad 83 // returns false. 84 if (TM.getRelocationModel() == Reloc::PIC_) 85 return !isDirectCall && 86 (GV->hasLocalLinkage() || GV->hasExternalLinkage()); 87 return false; 88 } 89 90 /// getBZeroEntry - This function returns the name of a function which has an 91 /// interface like the non-standard bzero function, if such a function exists on 92 /// the current subtarget and it is considered prefereable over memset with zero 93 /// passed as the second argument. Otherwise it returns null. 94 const char *X86Subtarget::getBZeroEntry() const { 95 // Darwin 10 has a __bzero entry point for this purpose. 96 if (getDarwinVers() >= 10) 97 return "__bzero"; 98 99 return 0; 100 } 101 102 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls 103 /// to immediate address. 104 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { 105 if (Is64Bit) 106 return false; 107 return isTargetELF() || TM.getRelocationModel() == Reloc::Static; 108 } 109 110 /// getSpecialAddressLatency - For targets where it is beneficial to 111 /// backschedule instructions that compute addresses, return a value 112 /// indicating the number of scheduling cycles of backscheduling that 113 /// should be attempted. 114 unsigned X86Subtarget::getSpecialAddressLatency() const { 115 // For x86 out-of-order targets, back-schedule address computations so 116 // that loads and stores aren't blocked. 117 // This value was chosen arbitrarily. 118 return 200; 119 } 120 121 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 122 /// specified arguments. If we can't run cpuid on the host, return true. 123 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 124 unsigned *rECX, unsigned *rEDX) { 125 #if defined(__x86_64__) || defined(_M_AMD64) 126 #if defined(__GNUC__) 127 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 128 asm ("movq\t%%rbx, %%rsi\n\t" 129 "cpuid\n\t" 130 "xchgq\t%%rbx, %%rsi\n\t" 131 : "=a" (*rEAX), 132 "=S" (*rEBX), 133 "=c" (*rECX), 134 "=d" (*rEDX) 135 : "a" (value)); 136 return false; 137 #elif defined(_MSC_VER) 138 int registers[4]; 139 __cpuid(registers, value); 140 *rEAX = registers[0]; 141 *rEBX = registers[1]; 142 *rECX = registers[2]; 143 *rEDX = registers[3]; 144 return false; 145 #endif 146 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 147 #if defined(__GNUC__) 148 asm ("movl\t%%ebx, %%esi\n\t" 149 "cpuid\n\t" 150 "xchgl\t%%ebx, %%esi\n\t" 151 : "=a" (*rEAX), 152 "=S" (*rEBX), 153 "=c" (*rECX), 154 "=d" (*rEDX) 155 : "a" (value)); 156 return false; 157 #elif defined(_MSC_VER) 158 __asm { 159 mov eax,value 160 cpuid 161 mov esi,rEAX 162 mov dword ptr [esi],eax 163 mov esi,rEBX 164 mov dword ptr [esi],ebx 165 mov esi,rECX 166 mov dword ptr [esi],ecx 167 mov esi,rEDX 168 mov dword ptr [esi],edx 169 } 170 return false; 171 #endif 172 #endif 173 return true; 174 } 175 176 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { 177 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 178 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 179 if (Family == 6 || Family == 0xf) { 180 if (Family == 0xf) 181 // Examine extended family ID if family ID is F. 182 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 183 // Examine extended model ID if family ID is 6 or F. 184 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 185 } 186 } 187 188 void X86Subtarget::AutoDetectSubtargetFeatures() { 189 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 190 union { 191 unsigned u[3]; 192 char c[12]; 193 } text; 194 195 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1)) 196 return; 197 198 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 199 200 if ((EDX >> 23) & 0x1) X86SSELevel = MMX; 201 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1; 202 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2; 203 if (ECX & 0x1) X86SSELevel = SSE3; 204 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3; 205 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41; 206 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42; 207 208 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; 209 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; 210 if (IsIntel || IsAMD) { 211 // Determine if bit test memory instructions are slow. 212 unsigned Family = 0; 213 unsigned Model = 0; 214 DetectFamilyModel(EAX, Family, Model); 215 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13); 216 217 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 218 HasX86_64 = (EDX >> 29) & 0x1; 219 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1); 220 } 221 } 222 223 static const char *GetCurrentX86CPU() { 224 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 225 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 226 return "generic"; 227 unsigned Family = 0; 228 unsigned Model = 0; 229 DetectFamilyModel(EAX, Family, Model); 230 231 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 232 bool Em64T = (EDX >> 29) & 0x1; 233 bool HasSSE3 = (ECX & 0x1); 234 235 union { 236 unsigned u[3]; 237 char c[12]; 238 } text; 239 240 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1); 241 if (memcmp(text.c, "GenuineIntel", 12) == 0) { 242 switch (Family) { 243 case 3: 244 return "i386"; 245 case 4: 246 return "i486"; 247 case 5: 248 switch (Model) { 249 case 4: return "pentium-mmx"; 250 default: return "pentium"; 251 } 252 case 6: 253 switch (Model) { 254 case 1: return "pentiumpro"; 255 case 3: 256 case 5: 257 case 6: return "pentium2"; 258 case 7: 259 case 8: 260 case 10: 261 case 11: return "pentium3"; 262 case 9: 263 case 13: return "pentium-m"; 264 case 14: return "yonah"; 265 case 15: 266 case 22: // Celeron M 540 267 return "core2"; 268 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE) 269 return "penryn"; 270 default: return "i686"; 271 } 272 case 15: { 273 switch (Model) { 274 case 3: 275 case 4: 276 case 6: // same as 4, but 65nm 277 return (Em64T) ? "nocona" : "prescott"; 278 case 26: 279 return "corei7"; 280 case 28: 281 return "atom"; 282 default: 283 return (Em64T) ? "x86-64" : "pentium4"; 284 } 285 } 286 287 default: 288 return "generic"; 289 } 290 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { 291 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 292 // appears to be no way to generate the wide variety of AMD-specific targets 293 // from the information returned from CPUID. 294 switch (Family) { 295 case 4: 296 return "i486"; 297 case 5: 298 switch (Model) { 299 case 6: 300 case 7: return "k6"; 301 case 8: return "k6-2"; 302 case 9: 303 case 13: return "k6-3"; 304 default: return "pentium"; 305 } 306 case 6: 307 switch (Model) { 308 case 4: return "athlon-tbird"; 309 case 6: 310 case 7: 311 case 8: return "athlon-mp"; 312 case 10: return "athlon-xp"; 313 default: return "athlon"; 314 } 315 case 15: 316 if (HasSSE3) { 317 switch (Model) { 318 default: return "k8-sse3"; 319 } 320 } else { 321 switch (Model) { 322 case 1: return "opteron"; 323 case 5: return "athlon-fx"; // also opteron 324 default: return "athlon64"; 325 } 326 } 327 case 16: 328 switch (Model) { 329 default: return "amdfam10"; 330 } 331 default: 332 return "generic"; 333 } 334 } else { 335 return "generic"; 336 } 337 } 338 339 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit) 340 : AsmFlavor(AsmWriterFlavor) 341 , PICStyle(PICStyles::None) 342 , X86SSELevel(NoMMXSSE) 343 , X863DNowLevel(NoThreeDNow) 344 , HasX86_64(false) 345 , IsBTMemSlow(false) 346 , DarwinVers(0) 347 , IsLinux(false) 348 , stackAlignment(8) 349 // FIXME: this is a known good value for Yonah. How about others? 350 , MaxInlineSizeThreshold(128) 351 , Is64Bit(is64Bit) 352 , TargetType(isELF) { // Default to ELF unless otherwise specified. 353 354 // default to hard float ABI 355 if (FloatABIType == FloatABI::Default) 356 FloatABIType = FloatABI::Hard; 357 358 // Determine default and user specified characteristics 359 if (!FS.empty()) { 360 // If feature string is not empty, parse features string. 361 std::string CPU = GetCurrentX86CPU(); 362 ParseSubtargetFeatures(FS, CPU); 363 // All X86-64 CPUs also have SSE2, however user might request no SSE via 364 // -mattr, so don't force SSELevel here. 365 } else { 366 // Otherwise, use CPUID to auto-detect feature set. 367 AutoDetectSubtargetFeatures(); 368 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs. 369 if (Is64Bit && X86SSELevel < SSE2) 370 X86SSELevel = SSE2; 371 } 372 373 // If requesting codegen for X86-64, make sure that 64-bit features 374 // are enabled. 375 if (Is64Bit) 376 HasX86_64 = true; 377 378 DOUT << "Subtarget features: SSELevel " << X86SSELevel 379 << ", 3DNowLevel " << X863DNowLevel 380 << ", 64bit " << HasX86_64 << "\n"; 381 assert((!Is64Bit || HasX86_64) && 382 "64-bit code requested on a subtarget that doesn't support it!"); 383 384 // Set the boolean corresponding to the current target triple, or the default 385 // if one cannot be determined, to true. 386 const std::string& TT = M.getTargetTriple(); 387 if (TT.length() > 5) { 388 size_t Pos; 389 if ((Pos = TT.find("-darwin")) != std::string::npos) { 390 TargetType = isDarwin; 391 392 // Compute the darwin version number. 393 if (isdigit(TT[Pos+7])) 394 DarwinVers = atoi(&TT[Pos+7]); 395 else 396 DarwinVers = 8; // Minimum supported darwin is Tiger. 397 } else if (TT.find("linux") != std::string::npos) { 398 // Linux doesn't imply ELF, but we don't currently support anything else. 399 TargetType = isELF; 400 IsLinux = true; 401 } else if (TT.find("cygwin") != std::string::npos) { 402 TargetType = isCygwin; 403 } else if (TT.find("mingw") != std::string::npos) { 404 TargetType = isMingw; 405 } else if (TT.find("win32") != std::string::npos) { 406 TargetType = isWindows; 407 } else if (TT.find("windows") != std::string::npos) { 408 TargetType = isWindows; 409 } 410 else if (TT.find("-cl") != std::string::npos) { 411 TargetType = isDarwin; 412 DarwinVers = 9; 413 } 414 } else if (TT.empty()) { 415 #if defined(__CYGWIN__) 416 TargetType = isCygwin; 417 #elif defined(__MINGW32__) || defined(__MINGW64__) 418 TargetType = isMingw; 419 #elif defined(__APPLE__) 420 TargetType = isDarwin; 421 #if __APPLE_CC__ > 5400 422 DarwinVers = 9; // GCC 5400+ is Leopard. 423 #else 424 DarwinVers = 8; // Minimum supported darwin is Tiger. 425 #endif 426 427 #elif defined(_WIN32) || defined(_WIN64) 428 TargetType = isWindows; 429 #elif defined(__linux__) 430 // Linux doesn't imply ELF, but we don't currently support anything else. 431 TargetType = isELF; 432 IsLinux = true; 433 #endif 434 } 435 436 // If the asm syntax hasn't been overridden on the command line, use whatever 437 // the target wants. 438 if (AsmFlavor == X86Subtarget::Unset) { 439 AsmFlavor = (TargetType == isWindows) 440 ? X86Subtarget::Intel : X86Subtarget::ATT; 441 } 442 443 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64 444 // bit targets. 445 if (TargetType == isDarwin || Is64Bit) 446 stackAlignment = 16; 447 448 if (StackAlignment) 449 stackAlignment = StackAlignment; 450 } 451