1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 
16 #include "X86CallLowering.h"
17 #include "X86LegalizerInfo.h"
18 #include "X86RegisterBankInfo.h"
19 #include "X86Subtarget.h"
20 #include "MCTargetDesc/X86BaseInfo.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/IR/Attributes.h"
26 #include "llvm/IR/ConstantRange.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/CodeGen.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 
37 #if defined(_MSC_VER)
38 #include <intrin.h>
39 #endif
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "subtarget"
44 
45 #define GET_SUBTARGETINFO_TARGET_DESC
46 #define GET_SUBTARGETINFO_CTOR
47 #include "X86GenSubtargetInfo.inc"
48 
49 // Temporary option to control early if-conversion for x86 while adding machine
50 // models.
51 static cl::opt<bool>
52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
53                cl::desc("Enable early if-conversion on X86"));
54 
55 
56 /// Classify a blockaddress reference for the current subtarget according to how
57 /// we should reference it in a non-pcrel context.
58 unsigned char X86Subtarget::classifyBlockAddressReference() const {
59   return classifyLocalReference(nullptr);
60 }
61 
62 /// Classify a global variable reference for the current subtarget according to
63 /// how we should reference it in a non-pcrel context.
64 unsigned char
65 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const {
66   return classifyGlobalReference(GV, *GV->getParent());
67 }
68 
69 unsigned char
70 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const {
71   // If we're not PIC, it's not very interesting.
72   if (!isPositionIndependent())
73     return X86II::MO_NO_FLAG;
74 
75   // For 64-bit, we need to consider the code model.
76   if (is64Bit()) {
77     switch (TM.getCodeModel()) {
78     // 64-bit small code model is simple: All rip-relative.
79     case CodeModel::Small:
80     case CodeModel::Kernel:
81       return X86II::MO_NO_FLAG;
82 
83     // The large PIC code model uses GOTOFF.
84     case CodeModel::Large:
85       return X86II::MO_GOTOFF;
86 
87     // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data.
88     case CodeModel::Medium:
89       if (isa<Function>(GV))
90         return X86II::MO_NO_FLAG; // All code is RIP-relative
91       return X86II::MO_GOTOFF;    // Local symbols use GOTOFF.
92     }
93     llvm_unreachable("invalid code model");
94   }
95 
96   // The COFF dynamic linker just patches the executable sections.
97   if (isTargetCOFF())
98     return X86II::MO_NO_FLAG;
99 
100   if (isTargetDarwin()) {
101     // 32 bit macho has no relocation for a-b if a is undefined, even if
102     // b is in the section that is being relocated.
103     // This means we have to use o load even for GVs that are known to be
104     // local to the dso.
105     if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
106       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
107 
108     return X86II::MO_PIC_BASE_OFFSET;
109   }
110 
111   return X86II::MO_GOTOFF;
112 }
113 
114 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV,
115                                                     const Module &M) const {
116   // The static large model never uses stubs.
117   if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent())
118     return X86II::MO_NO_FLAG;
119 
120   // Absolute symbols can be referenced directly.
121   if (GV) {
122     if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) {
123       // See if we can use the 8-bit immediate form. Note that some instructions
124       // will sign extend the immediate operand, so to be conservative we only
125       // accept the range [0,128).
126       if (CR->getUnsignedMax().ult(128))
127         return X86II::MO_ABS8;
128       else
129         return X86II::MO_NO_FLAG;
130     }
131   }
132 
133   if (TM.shouldAssumeDSOLocal(M, GV))
134     return classifyLocalReference(GV);
135 
136   if (isTargetCOFF())
137     return X86II::MO_DLLIMPORT;
138 
139   if (is64Bit() && TM.getCodeModel() != CodeModel::Large)
140     return X86II::MO_GOTPCREL;
141 
142   if (isTargetDarwin()) {
143     if (!isPositionIndependent())
144       return X86II::MO_DARWIN_NONLAZY;
145     return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
146   }
147 
148   return X86II::MO_GOT;
149 }
150 
151 unsigned char
152 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const {
153   return classifyGlobalFunctionReference(GV, *GV->getParent());
154 }
155 
156 unsigned char
157 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
158                                               const Module &M) const {
159   if (TM.shouldAssumeDSOLocal(M, GV))
160     return X86II::MO_NO_FLAG;
161 
162   if (isTargetCOFF()) {
163     assert(GV->hasDLLImportStorageClass() &&
164            "shouldAssumeDSOLocal gave inconsistent answer");
165     return X86II::MO_DLLIMPORT;
166   }
167 
168   const Function *F = dyn_cast_or_null<Function>(GV);
169 
170   if (isTargetELF()) {
171     if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv()))
172       // According to psABI, PLT stub clobbers XMM8-XMM15.
173       // In Regcall calling convention those registers are used for passing
174       // parameters. Thus we need to prevent lazy binding in Regcall.
175       return X86II::MO_GOTPCREL;
176     // If PLT must be avoided then the call should be via GOTPCREL.
177     if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) ||
178          (!F && M.getRtLibUseGOT())) &&
179         is64Bit())
180        return X86II::MO_GOTPCREL;
181     return X86II::MO_PLT;
182   }
183 
184   if (is64Bit()) {
185     if (F && F->hasFnAttribute(Attribute::NonLazyBind))
186       // If the function is marked as non-lazy, generate an indirect call
187       // which loads from the GOT directly. This avoids runtime overhead
188       // at the cost of eager binding (and one extra byte of encoding).
189       return X86II::MO_GOTPCREL;
190     return X86II::MO_NO_FLAG;
191   }
192 
193   return X86II::MO_NO_FLAG;
194 }
195 
196 /// Return true if the subtarget allows calls to immediate address.
197 bool X86Subtarget::isLegalToCallImmediateAddr() const {
198   // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
199   // but WinCOFFObjectWriter::RecordRelocation cannot emit them.  Once it does,
200   // the following check for Win32 should be removed.
201   if (In64BitMode || isTargetWin32())
202     return false;
203   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
204 }
205 
206 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
207   std::string CPUName = CPU;
208   if (CPUName.empty())
209     CPUName = "generic";
210 
211   // Make sure 64-bit features are available in 64-bit mode. (But make sure
212   // SSE2 can be turned off explicitly.)
213   std::string FullFS = FS;
214   if (In64BitMode) {
215     if (!FullFS.empty())
216       FullFS = "+64bit,+sse2," + FullFS;
217     else
218       FullFS = "+64bit,+sse2";
219   }
220 
221   // LAHF/SAHF are always supported in non-64-bit mode.
222   if (!In64BitMode) {
223     if (!FullFS.empty())
224       FullFS = "+sahf," + FullFS;
225     else
226       FullFS = "+sahf";
227   }
228 
229   // Parse features string and set the CPU.
230   ParseSubtargetFeatures(CPUName, FullFS);
231 
232   // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
233   // 16-bytes and under that are reasonably fast. These features were
234   // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
235   // micro-architectures respectively.
236   if (hasSSE42() || hasSSE4A())
237     IsUAMem16Slow = false;
238 
239   // It's important to keep the MCSubtargetInfo feature bits in sync with
240   // target data structure which is shared with MC code emitter, etc.
241   if (In64BitMode)
242     ToggleFeature(X86::Mode64Bit);
243   else if (In32BitMode)
244     ToggleFeature(X86::Mode32Bit);
245   else if (In16BitMode)
246     ToggleFeature(X86::Mode16Bit);
247   else
248     llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
249 
250   LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
251                     << ", 3DNowLevel " << X863DNowLevel << ", 64bit "
252                     << HasX86_64 << "\n");
253   assert((!In64BitMode || HasX86_64) &&
254          "64-bit code requested on a subtarget that doesn't support it!");
255 
256   // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
257   // 32 and 64 bit) and for all 64-bit targets.
258   if (StackAlignOverride)
259     stackAlignment = StackAlignOverride;
260   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
261            isTargetKFreeBSD() || In64BitMode)
262     stackAlignment = 16;
263 
264   // Some CPUs have more overhead for gather. The specified overhead is relative
265   // to the Load operation. "2" is the number provided by Intel architects. This
266   // parameter is used for cost estimation of Gather Op and comparison with
267   // other alternatives.
268   // TODO: Remove the explicit hasAVX512()?, That would mean we would only
269   // enable gather with a -march.
270   if (hasAVX512() || (hasAVX2() && hasFastGather()))
271     GatherOverhead = 2;
272   if (hasAVX512())
273     ScatterOverhead = 2;
274 
275   // Consume the vector width attribute or apply any target specific limit.
276   if (PreferVectorWidthOverride)
277     PreferVectorWidth = PreferVectorWidthOverride;
278   else if (Prefer256Bit)
279     PreferVectorWidth = 256;
280 }
281 
282 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
283                                                             StringRef FS) {
284   initSubtargetFeatures(CPU, FS);
285   return *this;
286 }
287 
288 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
289                            const X86TargetMachine &TM,
290                            unsigned StackAlignOverride,
291                            unsigned PreferVectorWidthOverride,
292                            unsigned RequiredVectorWidth)
293     : X86GenSubtargetInfo(TT, CPU, FS),
294       PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
295       StackAlignOverride(StackAlignOverride),
296       PreferVectorWidthOverride(PreferVectorWidthOverride),
297       RequiredVectorWidth(RequiredVectorWidth),
298       In64BitMode(TargetTriple.getArch() == Triple::x86_64),
299       In32BitMode(TargetTriple.getArch() == Triple::x86 &&
300                   TargetTriple.getEnvironment() != Triple::CODE16),
301       In16BitMode(TargetTriple.getArch() == Triple::x86 &&
302                   TargetTriple.getEnvironment() == Triple::CODE16),
303       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
304       FrameLowering(*this, getStackAlignment()) {
305   // Determine the PICStyle based on the target selected.
306   if (!isPositionIndependent())
307     setPICStyle(PICStyles::None);
308   else if (is64Bit())
309     setPICStyle(PICStyles::RIPRel);
310   else if (isTargetCOFF())
311     setPICStyle(PICStyles::None);
312   else if (isTargetDarwin())
313     setPICStyle(PICStyles::StubPIC);
314   else if (isTargetELF())
315     setPICStyle(PICStyles::GOT);
316 
317   CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering()));
318   Legalizer.reset(new X86LegalizerInfo(*this, TM));
319 
320   auto *RBI = new X86RegisterBankInfo(*getRegisterInfo());
321   RegBankInfo.reset(RBI);
322   InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI));
323 }
324 
325 const CallLowering *X86Subtarget::getCallLowering() const {
326   return CallLoweringInfo.get();
327 }
328 
329 const InstructionSelector *X86Subtarget::getInstructionSelector() const {
330   return InstSelector.get();
331 }
332 
333 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
334   return Legalizer.get();
335 }
336 
337 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
338   return RegBankInfo.get();
339 }
340 
341 bool X86Subtarget::enableEarlyIfConversion() const {
342   return hasCMov() && X86EarlyIfConv;
343 }
344