1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 using namespace llvm;
23 
24 #if defined(_MSC_VER)
25     #include <intrin.h>
26 #endif
27 
28 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
30   cl::desc("Choose style of code to emit from X86 backend:"),
31   cl::values(
32     clEnumValN(X86Subtarget::ATT,   "att",   "Emit AT&T-style assembly"),
33     clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
34     clEnumValEnd));
35 
36 
37 /// True if accessing the GV requires an extra load. For Windows, dllimported
38 /// symbols are indirect, loading the value at address GV rather then the
39 /// value of GV itself. This means that the GlobalAddress must be in the base
40 /// or index register of the address, not the GV offset field.
41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
42                                        const TargetMachine& TM,
43                                        bool isDirectCall) const {
44   // Windows targets only require an extra load for DLLImport linkage values,
45   // and they need these regardless of whether we're in PIC mode or not.
46   if (isTargetCygMing() || isTargetWindows())
47     return GV->hasDLLImportLinkage();
48 
49   if (TM.getRelocationModel() == Reloc::Static ||
50       TM.getCodeModel() == CodeModel::Large)
51     return false;
52 
53   if (isTargetDarwin()) {
54     if (isDirectCall)
55       return false;
56     bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
57     if (GV->hasHiddenVisibility() &&
58         (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
59       // If symbol visibility is hidden, the extra load is not needed if
60       // target is x86-64 or the symbol is definitely defined in the current
61       // translation unit.
62       return false;
63     return !isDirectCall && (isDecl || GV->isWeakForLinker());
64   } else if (isTargetELF()) {
65     // Extra load is needed for all externally visible.
66     if (isDirectCall)
67       return false;
68     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
69       return false;
70     return true;
71   }
72   return false;
73 }
74 
75 /// True if accessing the GV requires a register.  This is a superset of the
76 /// cases where GVRequiresExtraLoad is true.  Some variations of PIC require
77 /// a register, but not an extra load.
78 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
79                                       const TargetMachine& TM,
80                                       bool isDirectCall) const {
81   if (GVRequiresExtraLoad(GV, TM, isDirectCall))
82     return true;
83   // Code below here need only consider cases where GVRequiresExtraLoad
84   // returns false.
85   if (TM.getRelocationModel() == Reloc::PIC_)
86     return !isDirectCall &&
87       (GV->hasLocalLinkage() || GV->hasExternalLinkage());
88   return false;
89 }
90 
91 /// getBZeroEntry - This function returns the name of a function which has an
92 /// interface like the non-standard bzero function, if such a function exists on
93 /// the current subtarget and it is considered prefereable over memset with zero
94 /// passed as the second argument. Otherwise it returns null.
95 const char *X86Subtarget::getBZeroEntry() const {
96   // Darwin 10 has a __bzero entry point for this purpose.
97   if (getDarwinVers() >= 10)
98     return "__bzero";
99 
100   return 0;
101 }
102 
103 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
104 /// to immediate address.
105 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
106   if (Is64Bit)
107     return false;
108   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
109 }
110 
111 /// getSpecialAddressLatency - For targets where it is beneficial to
112 /// backschedule instructions that compute addresses, return a value
113 /// indicating the number of scheduling cycles of backscheduling that
114 /// should be attempted.
115 unsigned X86Subtarget::getSpecialAddressLatency() const {
116   // For x86 out-of-order targets, back-schedule address computations so
117   // that loads and stores aren't blocked.
118   // This value was chosen arbitrarily.
119   return 200;
120 }
121 
122 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
123 /// specified arguments.  If we can't run cpuid on the host, return true.
124 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
125                           unsigned *rECX, unsigned *rEDX) {
126 #if defined(__x86_64__) || defined(_M_AMD64)
127   #if defined(__GNUC__)
128     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129     asm ("movq\t%%rbx, %%rsi\n\t"
130          "cpuid\n\t"
131          "xchgq\t%%rbx, %%rsi\n\t"
132          : "=a" (*rEAX),
133            "=S" (*rEBX),
134            "=c" (*rECX),
135            "=d" (*rEDX)
136          :  "a" (value));
137     return false;
138   #elif defined(_MSC_VER)
139     int registers[4];
140     __cpuid(registers, value);
141     *rEAX = registers[0];
142     *rEBX = registers[1];
143     *rECX = registers[2];
144     *rEDX = registers[3];
145     return false;
146   #endif
147 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
148   #if defined(__GNUC__)
149     asm ("movl\t%%ebx, %%esi\n\t"
150          "cpuid\n\t"
151          "xchgl\t%%ebx, %%esi\n\t"
152          : "=a" (*rEAX),
153            "=S" (*rEBX),
154            "=c" (*rECX),
155            "=d" (*rEDX)
156          :  "a" (value));
157     return false;
158   #elif defined(_MSC_VER)
159     __asm {
160       mov   eax,value
161       cpuid
162       mov   esi,rEAX
163       mov   dword ptr [esi],eax
164       mov   esi,rEBX
165       mov   dword ptr [esi],ebx
166       mov   esi,rECX
167       mov   dword ptr [esi],ecx
168       mov   esi,rEDX
169       mov   dword ptr [esi],edx
170     }
171     return false;
172   #endif
173 #endif
174   return true;
175 }
176 
177 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
178   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
179   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
180   if (Family == 6 || Family == 0xf) {
181     if (Family == 0xf)
182       // Examine extended family ID if family ID is F.
183       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
184     // Examine extended model ID if family ID is 6 or F.
185     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
186   }
187 }
188 
189 void X86Subtarget::AutoDetectSubtargetFeatures() {
190   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
191   union {
192     unsigned u[3];
193     char     c[12];
194   } text;
195 
196   if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
197     return;
198 
199   X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
200 
201   if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
202   if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
203   if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
204   if (ECX & 0x1)         X86SSELevel = SSE3;
205   if ((ECX >> 9)  & 0x1) X86SSELevel = SSSE3;
206   if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
207   if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
208 
209   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
210   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
211 
212   HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
213   HasAVX = ((ECX >> 28) & 0x1);
214 
215   if (IsIntel || IsAMD) {
216     // Determine if bit test memory instructions are slow.
217     unsigned Family = 0;
218     unsigned Model  = 0;
219     DetectFamilyModel(EAX, Family, Model);
220     IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
221 
222     X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
223     HasX86_64 = (EDX >> 29) & 0x1;
224     HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
225     HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
226   }
227 }
228 
229 static const char *GetCurrentX86CPU() {
230   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
231   if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
232     return "generic";
233   unsigned Family = 0;
234   unsigned Model  = 0;
235   DetectFamilyModel(EAX, Family, Model);
236 
237   X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
238   bool Em64T = (EDX >> 29) & 0x1;
239   bool HasSSE3 = (ECX & 0x1);
240 
241   union {
242     unsigned u[3];
243     char     c[12];
244   } text;
245 
246   X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
247   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
248     switch (Family) {
249       case 3:
250         return "i386";
251       case 4:
252         return "i486";
253       case 5:
254         switch (Model) {
255         case 4:  return "pentium-mmx";
256         default: return "pentium";
257         }
258       case 6:
259         switch (Model) {
260         case 1:  return "pentiumpro";
261         case 3:
262         case 5:
263         case 6:  return "pentium2";
264         case 7:
265         case 8:
266         case 10:
267         case 11: return "pentium3";
268         case 9:
269         case 13: return "pentium-m";
270         case 14: return "yonah";
271         case 15:
272         case 22: // Celeron M 540
273           return "core2";
274         case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
275           return "penryn";
276         default: return "i686";
277         }
278       case 15: {
279         switch (Model) {
280         case 3:
281         case 4:
282         case 6: // same as 4, but 65nm
283           return (Em64T) ? "nocona" : "prescott";
284         case 26:
285           return "corei7";
286         case 28:
287           return "atom";
288         default:
289           return (Em64T) ? "x86-64" : "pentium4";
290         }
291       }
292 
293     default:
294       return "generic";
295     }
296   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
297     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
298     // appears to be no way to generate the wide variety of AMD-specific targets
299     // from the information returned from CPUID.
300     switch (Family) {
301       case 4:
302         return "i486";
303       case 5:
304         switch (Model) {
305         case 6:
306         case 7:  return "k6";
307         case 8:  return "k6-2";
308         case 9:
309         case 13: return "k6-3";
310         default: return "pentium";
311         }
312       case 6:
313         switch (Model) {
314         case 4:  return "athlon-tbird";
315         case 6:
316         case 7:
317         case 8:  return "athlon-mp";
318         case 10: return "athlon-xp";
319         default: return "athlon";
320         }
321       case 15:
322         if (HasSSE3) {
323           switch (Model) {
324           default: return "k8-sse3";
325           }
326         } else {
327           switch (Model) {
328           case 1:  return "opteron";
329           case 5:  return "athlon-fx"; // also opteron
330           default: return "athlon64";
331           }
332         }
333       case 16:
334         switch (Model) {
335         default: return "amdfam10";
336         }
337     default:
338       return "generic";
339     }
340   } else {
341     return "generic";
342   }
343 }
344 
345 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
346   : AsmFlavor(AsmWriterFlavor)
347   , PICStyle(PICStyles::None)
348   , X86SSELevel(NoMMXSSE)
349   , X863DNowLevel(NoThreeDNow)
350   , HasX86_64(false)
351   , HasSSE4A(false)
352   , HasAVX(false)
353   , HasFMA3(false)
354   , HasFMA4(false)
355   , IsBTMemSlow(false)
356   , DarwinVers(0)
357   , IsLinux(false)
358   , stackAlignment(8)
359   // FIXME: this is a known good value for Yonah. How about others?
360   , MaxInlineSizeThreshold(128)
361   , Is64Bit(is64Bit)
362   , TargetType(isELF) { // Default to ELF unless otherwise specified.
363 
364   // default to hard float ABI
365   if (FloatABIType == FloatABI::Default)
366     FloatABIType = FloatABI::Hard;
367 
368   // Determine default and user specified characteristics
369   if (!FS.empty()) {
370     // If feature string is not empty, parse features string.
371     std::string CPU = GetCurrentX86CPU();
372     ParseSubtargetFeatures(FS, CPU);
373     // All X86-64 CPUs also have SSE2, however user might request no SSE via
374     // -mattr, so don't force SSELevel here.
375   } else {
376     // Otherwise, use CPUID to auto-detect feature set.
377     AutoDetectSubtargetFeatures();
378     // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
379     if (Is64Bit && X86SSELevel < SSE2)
380       X86SSELevel = SSE2;
381   }
382 
383   // If requesting codegen for X86-64, make sure that 64-bit features
384   // are enabled.
385   if (Is64Bit)
386     HasX86_64 = true;
387 
388   DOUT << "Subtarget features: SSELevel " << X86SSELevel
389        << ", 3DNowLevel " << X863DNowLevel
390        << ", 64bit " << HasX86_64 << "\n";
391   assert((!Is64Bit || HasX86_64) &&
392          "64-bit code requested on a subtarget that doesn't support it!");
393 
394   // Set the boolean corresponding to the current target triple, or the default
395   // if one cannot be determined, to true.
396   const std::string& TT = M.getTargetTriple();
397   if (TT.length() > 5) {
398     size_t Pos;
399     if ((Pos = TT.find("-darwin")) != std::string::npos) {
400       TargetType = isDarwin;
401 
402       // Compute the darwin version number.
403       if (isdigit(TT[Pos+7]))
404         DarwinVers = atoi(&TT[Pos+7]);
405       else
406         DarwinVers = 8;  // Minimum supported darwin is Tiger.
407     } else if (TT.find("linux") != std::string::npos) {
408       // Linux doesn't imply ELF, but we don't currently support anything else.
409       TargetType = isELF;
410       IsLinux = true;
411     } else if (TT.find("cygwin") != std::string::npos) {
412       TargetType = isCygwin;
413     } else if (TT.find("mingw") != std::string::npos) {
414       TargetType = isMingw;
415     } else if (TT.find("win32") != std::string::npos) {
416       TargetType = isWindows;
417     } else if (TT.find("windows") != std::string::npos) {
418       TargetType = isWindows;
419     }
420     else if (TT.find("-cl") != std::string::npos) {
421       TargetType = isDarwin;
422       DarwinVers = 9;
423     }
424   } else if (TT.empty()) {
425 #if defined(__CYGWIN__)
426     TargetType = isCygwin;
427 #elif defined(__MINGW32__) || defined(__MINGW64__)
428     TargetType = isMingw;
429 #elif defined(__APPLE__)
430     TargetType = isDarwin;
431 #if __APPLE_CC__ > 5400
432     DarwinVers = 9;  // GCC 5400+ is Leopard.
433 #else
434     DarwinVers = 8;  // Minimum supported darwin is Tiger.
435 #endif
436 
437 #elif defined(_WIN32) || defined(_WIN64)
438     TargetType = isWindows;
439 #elif defined(__linux__)
440     // Linux doesn't imply ELF, but we don't currently support anything else.
441     TargetType = isELF;
442     IsLinux = true;
443 #endif
444   }
445 
446   // If the asm syntax hasn't been overridden on the command line, use whatever
447   // the target wants.
448   if (AsmFlavor == X86Subtarget::Unset) {
449     AsmFlavor = (TargetType == isWindows)
450       ? X86Subtarget::Intel : X86Subtarget::ATT;
451   }
452 
453   // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
454   // bit targets.
455   if (TargetType == isDarwin || Is64Bit)
456     stackAlignment = 16;
457 
458   if (StackAlignment)
459     stackAlignment = StackAlignment;
460 }
461