1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "llvm/GlobalValue.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Support/Host.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetOptions.h"
24 
25 #define GET_SUBTARGETINFO_TARGET_DESC
26 #define GET_SUBTARGETINFO_CTOR
27 #include "X86GenSubtargetInfo.inc"
28 
29 using namespace llvm;
30 
31 #if defined(_MSC_VER)
32 #include <intrin.h>
33 #endif
34 
35 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
36 /// current subtarget according to how we should reference it in a non-pcrel
37 /// context.
38 unsigned char X86Subtarget::
39 ClassifyBlockAddressReference() const {
40   if (isPICStyleGOT())    // 32-bit ELF targets.
41     return X86II::MO_GOTOFF;
42 
43   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
44     return X86II::MO_PIC_BASE_OFFSET;
45 
46   // Direct static reference to label.
47   return X86II::MO_NO_FLAG;
48 }
49 
50 /// ClassifyGlobalReference - Classify a global variable reference for the
51 /// current subtarget according to how we should reference it in a non-pcrel
52 /// context.
53 unsigned char X86Subtarget::
54 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
55   // DLLImport only exists on windows, it is implemented as a load from a
56   // DLLIMPORT stub.
57   if (GV->hasDLLImportLinkage())
58     return X86II::MO_DLLIMPORT;
59 
60   // Determine whether this is a reference to a definition or a declaration.
61   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
62   // load from stub.
63   bool isDecl = GV->hasAvailableExternallyLinkage();
64   if (GV->isDeclaration() && !GV->isMaterializable())
65     isDecl = true;
66 
67   // X86-64 in PIC mode.
68   if (isPICStyleRIPRel()) {
69     // Large model never uses stubs.
70     if (TM.getCodeModel() == CodeModel::Large)
71       return X86II::MO_NO_FLAG;
72 
73     if (isTargetDarwin()) {
74       // If symbol visibility is hidden, the extra load is not needed if
75       // target is x86-64 or the symbol is definitely defined in the current
76       // translation unit.
77       if (GV->hasDefaultVisibility() &&
78           (isDecl || GV->isWeakForLinker()))
79         return X86II::MO_GOTPCREL;
80     } else if (!isTargetWin64()) {
81       assert(isTargetELF() && "Unknown rip-relative target");
82 
83       // Extra load is needed for all externally visible.
84       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
85         return X86II::MO_GOTPCREL;
86     }
87 
88     return X86II::MO_NO_FLAG;
89   }
90 
91   if (isPICStyleGOT()) {   // 32-bit ELF targets.
92     // Extra load is needed for all externally visible.
93     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
94       return X86II::MO_GOTOFF;
95     return X86II::MO_GOT;
96   }
97 
98   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
99     // Determine whether we have a stub reference and/or whether the reference
100     // is relative to the PIC base or not.
101 
102     // If this is a strong reference to a definition, it is definitely not
103     // through a stub.
104     if (!isDecl && !GV->isWeakForLinker())
105       return X86II::MO_PIC_BASE_OFFSET;
106 
107     // Unless we have a symbol with hidden visibility, we have to go through a
108     // normal $non_lazy_ptr stub because this symbol might be resolved late.
109     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
110       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
111 
112     // If symbol visibility is hidden, we have a stub for common symbol
113     // references and external declarations.
114     if (isDecl || GV->hasCommonLinkage()) {
115       // Hidden $non_lazy_ptr reference.
116       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
117     }
118 
119     // Otherwise, no stub.
120     return X86II::MO_PIC_BASE_OFFSET;
121   }
122 
123   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
124     // Determine whether we have a stub reference.
125 
126     // If this is a strong reference to a definition, it is definitely not
127     // through a stub.
128     if (!isDecl && !GV->isWeakForLinker())
129       return X86II::MO_NO_FLAG;
130 
131     // Unless we have a symbol with hidden visibility, we have to go through a
132     // normal $non_lazy_ptr stub because this symbol might be resolved late.
133     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
134       return X86II::MO_DARWIN_NONLAZY;
135 
136     // Otherwise, no stub.
137     return X86II::MO_NO_FLAG;
138   }
139 
140   // Direct static reference to global.
141   return X86II::MO_NO_FLAG;
142 }
143 
144 
145 /// getBZeroEntry - This function returns the name of a function which has an
146 /// interface like the non-standard bzero function, if such a function exists on
147 /// the current subtarget and it is considered prefereable over memset with zero
148 /// passed as the second argument. Otherwise it returns null.
149 const char *X86Subtarget::getBZeroEntry() const {
150   // Darwin 10 has a __bzero entry point for this purpose.
151   if (getTargetTriple().isMacOSX() &&
152       !getTargetTriple().isMacOSXVersionLT(10, 6))
153     return "__bzero";
154 
155   return 0;
156 }
157 
158 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
159 /// to immediate address.
160 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
161   if (In64BitMode)
162     return false;
163   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
164 }
165 
166 /// getSpecialAddressLatency - For targets where it is beneficial to
167 /// backschedule instructions that compute addresses, return a value
168 /// indicating the number of scheduling cycles of backscheduling that
169 /// should be attempted.
170 unsigned X86Subtarget::getSpecialAddressLatency() const {
171   // For x86 out-of-order targets, back-schedule address computations so
172   // that loads and stores aren't blocked.
173   // This value was chosen arbitrarily.
174   return 200;
175 }
176 
177 void X86Subtarget::AutoDetectSubtargetFeatures() {
178   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
179   unsigned MaxLevel;
180   union {
181     unsigned u[3];
182     char     c[12];
183   } text;
184 
185   if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
186       MaxLevel < 1)
187     return;
188 
189   X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
190 
191   if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
192   if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
193   if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
194   if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
195   if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
196   if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
197   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
198   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
199   if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }
200 
201   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
202   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
203 
204   if ((ECX >> 1) & 0x1) {
205     HasPCLMUL = true;
206     ToggleFeature(X86::FeaturePCLMUL);
207   }
208   if ((ECX >> 12) & 0x1) {
209     HasFMA = true;
210     ToggleFeature(X86::FeatureFMA);
211   }
212   if (IsIntel && ((ECX >> 22) & 0x1)) {
213     HasMOVBE = true;
214     ToggleFeature(X86::FeatureMOVBE);
215   }
216   if ((ECX >> 23) & 0x1) {
217     HasPOPCNT = true;
218     ToggleFeature(X86::FeaturePOPCNT);
219   }
220   if ((ECX >> 25) & 0x1) {
221     HasAES = true;
222     ToggleFeature(X86::FeatureAES);
223   }
224   if ((ECX >> 29) & 0x1) {
225     HasF16C = true;
226     ToggleFeature(X86::FeatureF16C);
227   }
228   if (IsIntel && ((ECX >> 30) & 0x1)) {
229     HasRDRAND = true;
230     ToggleFeature(X86::FeatureRDRAND);
231   }
232 
233   if ((ECX >> 13) & 0x1) {
234     HasCmpxchg16b = true;
235     ToggleFeature(X86::FeatureCMPXCHG16B);
236   }
237 
238   if (IsIntel || IsAMD) {
239     // Determine if bit test memory instructions are slow.
240     unsigned Family = 0;
241     unsigned Model  = 0;
242     X86_MC::DetectFamilyModel(EAX, Family, Model);
243     if (IsAMD || (Family == 6 && Model >= 13)) {
244       IsBTMemSlow = true;
245       ToggleFeature(X86::FeatureSlowBTMem);
246     }
247 
248     // If it's Nehalem, unaligned memory access is fast.
249     // FIXME: Nehalem is family 6. Also include Westmere and later processors?
250     if (Family == 15 && Model == 26) {
251       IsUAMemFast = true;
252       ToggleFeature(X86::FeatureFastUAMem);
253     }
254 
255     // Set processor type. Currently only Atom is detected.
256     if (Family == 6 &&
257         (Model == 28 || Model == 38 || Model == 39
258          || Model == 53 || Model == 54)) {
259       X86ProcFamily = IntelAtom;
260 
261       UseLeaForSP = true;
262       ToggleFeature(X86::FeatureLeaForSP);
263     }
264 
265     unsigned MaxExtLevel;
266     X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
267 
268     if (MaxExtLevel >= 0x80000001) {
269       X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
270       if ((EDX >> 29) & 0x1) {
271         HasX86_64 = true;
272         ToggleFeature(X86::Feature64Bit);
273       }
274       if ((ECX >> 5) & 0x1) {
275         HasLZCNT = true;
276         ToggleFeature(X86::FeatureLZCNT);
277       }
278       if (IsAMD) {
279         if ((ECX >> 6) & 0x1) {
280           HasSSE4A = true;
281           ToggleFeature(X86::FeatureSSE4A);
282         }
283         if ((ECX >> 11) & 0x1) {
284           HasXOP = true;
285           ToggleFeature(X86::FeatureXOP);
286         }
287         if ((ECX >> 16) & 0x1) {
288           HasFMA4 = true;
289           ToggleFeature(X86::FeatureFMA4);
290         }
291       }
292     }
293   }
294 
295   if (MaxLevel >= 7) {
296     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
297       if (IsIntel && (EBX & 0x1)) {
298         HasFSGSBase = true;
299         ToggleFeature(X86::FeatureFSGSBase);
300       }
301       if ((EBX >> 3) & 0x1) {
302         HasBMI = true;
303         ToggleFeature(X86::FeatureBMI);
304       }
305       if (IsIntel && ((EBX >> 5) & 0x1)) {
306         X86SSELevel = AVX2;
307         ToggleFeature(X86::FeatureAVX2);
308       }
309       if (IsIntel && ((EBX >> 8) & 0x1)) {
310         HasBMI2 = true;
311         ToggleFeature(X86::FeatureBMI2);
312       }
313     }
314   }
315 }
316 
317 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
318                            const std::string &FS,
319                            unsigned StackAlignOverride, bool is64Bit)
320   : X86GenSubtargetInfo(TT, CPU, FS)
321   , X86ProcFamily(Others)
322   , PICStyle(PICStyles::None)
323   , X86SSELevel(NoMMXSSE)
324   , X863DNowLevel(NoThreeDNow)
325   , HasCMov(false)
326   , HasX86_64(false)
327   , HasPOPCNT(false)
328   , HasSSE4A(false)
329   , HasAES(false)
330   , HasPCLMUL(false)
331   , HasFMA(false)
332   , HasFMA4(false)
333   , HasXOP(false)
334   , HasMOVBE(false)
335   , HasRDRAND(false)
336   , HasF16C(false)
337   , HasFSGSBase(false)
338   , HasLZCNT(false)
339   , HasBMI(false)
340   , HasBMI2(false)
341   , IsBTMemSlow(false)
342   , IsUAMemFast(false)
343   , HasVectorUAMem(false)
344   , HasCmpxchg16b(false)
345   , UseLeaForSP(false)
346   , PostRAScheduler(false)
347   , stackAlignment(4)
348   // FIXME: this is a known good value for Yonah. How about others?
349   , MaxInlineSizeThreshold(128)
350   , TargetTriple(TT)
351   , In64BitMode(is64Bit) {
352   // Determine default and user specified characteristics
353   std::string CPUName = CPU;
354   if (!FS.empty() || !CPU.empty()) {
355     if (CPUName.empty()) {
356 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
357     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
358       CPUName = sys::getHostCPUName();
359 #else
360       CPUName = "generic";
361 #endif
362     }
363 
364     // Make sure 64-bit features are available in 64-bit mode. (But make sure
365     // SSE2 can be turned off explicitly.)
366     std::string FullFS = FS;
367     if (In64BitMode) {
368       if (!FullFS.empty())
369         FullFS = "+64bit,+sse2," + FullFS;
370       else
371         FullFS = "+64bit,+sse2";
372     }
373 
374     // If feature string is not empty, parse features string.
375     ParseSubtargetFeatures(CPUName, FullFS);
376   } else {
377     if (CPUName.empty()) {
378 #if defined (__x86_64__) || defined(__i386__)
379       CPUName = sys::getHostCPUName();
380 #else
381       CPUName = "generic";
382 #endif
383     }
384     // Otherwise, use CPUID to auto-detect feature set.
385     AutoDetectSubtargetFeatures();
386 
387     // Make sure 64-bit features are available in 64-bit mode.
388     if (In64BitMode) {
389       HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
390       HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
391 
392       if (X86SSELevel < SSE2) {
393         X86SSELevel = SSE2;
394         ToggleFeature(X86::FeatureSSE1);
395         ToggleFeature(X86::FeatureSSE2);
396       }
397     }
398   }
399 
400   if (X86ProcFamily == IntelAtom) {
401     PostRAScheduler = true;
402     InstrItins = getInstrItineraryForCPU(CPUName);
403   }
404 
405   // It's important to keep the MCSubtargetInfo feature bits in sync with
406   // target data structure which is shared with MC code emitter, etc.
407   if (In64BitMode)
408     ToggleFeature(X86::Mode64Bit);
409 
410   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
411                << ", 3DNowLevel " << X863DNowLevel
412                << ", 64bit " << HasX86_64 << "\n");
413   assert((!In64BitMode || HasX86_64) &&
414          "64-bit code requested on a subtarget that doesn't support it!");
415 
416   // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
417   // 32 and 64 bit) and for all 64-bit targets.
418   if (StackAlignOverride)
419     stackAlignment = StackAlignOverride;
420   else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
421            isTargetSolaris() || In64BitMode)
422     stackAlignment = 16;
423 }
424 
425 bool X86Subtarget::enablePostRAScheduler(
426            CodeGenOpt::Level OptLevel,
427            TargetSubtargetInfo::AntiDepBreakMode& Mode,
428            RegClassVector& CriticalPathRCs) const {
429   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
430   CriticalPathRCs.clear();
431   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
432 }
433