1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/MachineValueType.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 
41 using namespace llvm;
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
45 
46 cl::opt<bool>
47 ForceStackAlign("force-align-stack",
48                  cl::desc("Force align the stack to the minimum alignment"
49                            " needed for the function."),
50                  cl::init(false), cl::Hidden);
51 
52 static cl::opt<bool>
53 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
54           cl::desc("Enable use of a base pointer for complex stack frames"));
55 
56 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
57     : X86GenRegisterInfo(
58           (STI.is64Bit() ? X86::RIP : X86::EIP),
59           X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
60           X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
61           (STI.is64Bit() ? X86::RIP : X86::EIP)),
62       Subtarget(STI) {
63   X86_MC::InitLLVM2SEHRegisterMapping(this);
64 
65   // Cache some information.
66   Is64Bit = Subtarget.is64Bit();
67   IsWin64 = Subtarget.isTargetWin64();
68 
69   // Use a callee-saved register as the base pointer.  These registers must
70   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
71   // requires GOT in the EBX register before function calls via PLT GOT pointer.
72   if (Is64Bit) {
73     SlotSize = 8;
74     bool Use64BitReg =
75       Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
76     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
77     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
78     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
79   } else {
80     SlotSize = 4;
81     StackPtr = X86::ESP;
82     FramePtr = X86::EBP;
83     BasePtr = X86::ESI;
84   }
85 }
86 
87 bool
88 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
89   // ExeDepsFixer and PostRAScheduler require liveness.
90   return true;
91 }
92 
93 int
94 X86RegisterInfo::getSEHRegNum(unsigned i) const {
95   return getEncodingValue(i);
96 }
97 
98 const TargetRegisterClass *
99 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
100                                        unsigned Idx) const {
101   // The sub_8bit sub-register index is more constrained in 32-bit mode.
102   // It behaves just like the sub_8bit_hi index.
103   if (!Is64Bit && Idx == X86::sub_8bit)
104     Idx = X86::sub_8bit_hi;
105 
106   // Forward to TableGen's default version.
107   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
108 }
109 
110 const TargetRegisterClass *
111 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
112                                           const TargetRegisterClass *B,
113                                           unsigned SubIdx) const {
114   // The sub_8bit sub-register index is more constrained in 32-bit mode.
115   if (!Is64Bit && SubIdx == X86::sub_8bit) {
116     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
117     if (!A)
118       return nullptr;
119   }
120   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
121 }
122 
123 const TargetRegisterClass*
124 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
125   // Don't allow super-classes of GR8_NOREX.  This class is only used after
126   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
127   // to the full GR8 register class in 64-bit mode, so we cannot allow the
128   // reigster class inflation.
129   //
130   // The GR8_NOREX class is always used in a way that won't be constrained to a
131   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
132   // full GR8 class.
133   if (RC == &X86::GR8_NOREXRegClass)
134     return RC;
135 
136   const TargetRegisterClass *Super = RC;
137   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
138   do {
139     switch (Super->getID()) {
140     case X86::GR8RegClassID:
141     case X86::GR16RegClassID:
142     case X86::GR32RegClassID:
143     case X86::GR64RegClassID:
144     case X86::FR32RegClassID:
145     case X86::FR64RegClassID:
146     case X86::RFP32RegClassID:
147     case X86::RFP64RegClassID:
148     case X86::RFP80RegClassID:
149     case X86::VR128RegClassID:
150     case X86::VR256RegClassID:
151       // Don't return a super-class that would shrink the spill size.
152       // That can happen with the vector and float classes.
153       if (Super->getSize() == RC->getSize())
154         return Super;
155     }
156     Super = *I++;
157   } while (Super);
158   return RC;
159 }
160 
161 const TargetRegisterClass *
162 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
163                                     unsigned Kind) const {
164   switch (Kind) {
165   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
166   case 0: // Normal GPRs.
167     if (Subtarget.isTarget64BitLP64())
168       return &X86::GR64RegClass;
169     return &X86::GR32RegClass;
170   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
171     if (Subtarget.isTarget64BitLP64())
172       return &X86::GR64_NOSPRegClass;
173     return &X86::GR32_NOSPRegClass;
174   case 2: // Available for tailcall (not callee-saved GPRs).
175     if (Subtarget.isTargetWin64())
176       return &X86::GR64_TCW64RegClass;
177     else if (Subtarget.is64Bit())
178       return &X86::GR64_TCRegClass;
179 
180     const Function *F = MF.getFunction();
181     bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
182     if (hasHipeCC)
183       return &X86::GR32RegClass;
184     return &X86::GR32_TCRegClass;
185   }
186 }
187 
188 const TargetRegisterClass *
189 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
190   if (RC == &X86::CCRRegClass) {
191     if (Is64Bit)
192       return &X86::GR64RegClass;
193     else
194       return &X86::GR32RegClass;
195   }
196   return RC;
197 }
198 
199 unsigned
200 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
201                                      MachineFunction &MF) const {
202   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
203 
204   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
205   switch (RC->getID()) {
206   default:
207     return 0;
208   case X86::GR32RegClassID:
209     return 4 - FPDiff;
210   case X86::GR64RegClassID:
211     return 12 - FPDiff;
212   case X86::VR128RegClassID:
213     return Subtarget.is64Bit() ? 10 : 4;
214   case X86::VR64RegClassID:
215     return 4;
216   }
217 }
218 
219 const MCPhysReg *
220 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
221   bool HasAVX = Subtarget.hasAVX();
222   bool HasAVX512 = Subtarget.hasAVX512();
223 
224   assert(MF && "MachineFunction required");
225   switch (MF->getFunction()->getCallingConv()) {
226   case CallingConv::GHC:
227   case CallingConv::HiPE:
228     return CSR_NoRegs_SaveList;
229   case CallingConv::AnyReg:
230     if (HasAVX)
231       return CSR_64_AllRegs_AVX_SaveList;
232     return CSR_64_AllRegs_SaveList;
233   case CallingConv::PreserveMost:
234     return CSR_64_RT_MostRegs_SaveList;
235   case CallingConv::PreserveAll:
236     if (HasAVX)
237       return CSR_64_RT_AllRegs_AVX_SaveList;
238     return CSR_64_RT_AllRegs_SaveList;
239   case CallingConv::Intel_OCL_BI: {
240     if (HasAVX512 && IsWin64)
241       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
242     if (HasAVX512 && Is64Bit)
243       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
244     if (HasAVX && IsWin64)
245       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
246     if (HasAVX && Is64Bit)
247       return CSR_64_Intel_OCL_BI_AVX_SaveList;
248     if (!HasAVX && !IsWin64 && Is64Bit)
249       return CSR_64_Intel_OCL_BI_SaveList;
250     break;
251   }
252   case CallingConv::Cold:
253     if (Is64Bit)
254       return CSR_64_MostRegs_SaveList;
255     break;
256   default:
257     break;
258   }
259 
260   bool CallsEHReturn = MF->getMMI().callsEHReturn();
261   if (Is64Bit) {
262     if (IsWin64)
263       return CSR_Win64_SaveList;
264     if (CallsEHReturn)
265       return CSR_64EHRet_SaveList;
266     return CSR_64_SaveList;
267   }
268   if (CallsEHReturn)
269     return CSR_32EHRet_SaveList;
270   return CSR_32_SaveList;
271 }
272 
273 const uint32_t*
274 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
275   bool HasAVX = Subtarget.hasAVX();
276   bool HasAVX512 = Subtarget.hasAVX512();
277 
278   switch (CC) {
279   case CallingConv::GHC:
280   case CallingConv::HiPE:
281     return CSR_NoRegs_RegMask;
282   case CallingConv::AnyReg:
283     if (HasAVX)
284       return CSR_64_AllRegs_AVX_RegMask;
285     return CSR_64_AllRegs_RegMask;
286   case CallingConv::PreserveMost:
287     return CSR_64_RT_MostRegs_RegMask;
288   case CallingConv::PreserveAll:
289     if (HasAVX)
290       return CSR_64_RT_AllRegs_AVX_RegMask;
291     return CSR_64_RT_AllRegs_RegMask;
292   case CallingConv::Intel_OCL_BI: {
293     if (HasAVX512 && IsWin64)
294       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
295     if (HasAVX512 && Is64Bit)
296       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
297     if (HasAVX && IsWin64)
298       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
299     if (HasAVX && Is64Bit)
300       return CSR_64_Intel_OCL_BI_AVX_RegMask;
301     if (!HasAVX && !IsWin64 && Is64Bit)
302       return CSR_64_Intel_OCL_BI_RegMask;
303     break;
304   }
305   case CallingConv::Cold:
306     if (Is64Bit)
307       return CSR_64_MostRegs_RegMask;
308     break;
309   default:
310     break;
311   }
312 
313   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
314   // callsEHReturn().
315   if (Is64Bit) {
316     if (IsWin64)
317       return CSR_Win64_RegMask;
318     return CSR_64_RegMask;
319   }
320   return CSR_32_RegMask;
321 }
322 
323 const uint32_t*
324 X86RegisterInfo::getNoPreservedMask() const {
325   return CSR_NoRegs_RegMask;
326 }
327 
328 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
329   BitVector Reserved(getNumRegs());
330   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
331 
332   // Set the stack-pointer register and its aliases as reserved.
333   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
334        ++I)
335     Reserved.set(*I);
336 
337   // Set the instruction pointer register and its aliases as reserved.
338   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
339        ++I)
340     Reserved.set(*I);
341 
342   // Set the frame-pointer register and its aliases as reserved if needed.
343   if (TFI->hasFP(MF)) {
344     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
345          ++I)
346       Reserved.set(*I);
347   }
348 
349   // Set the base-pointer register and its aliases as reserved if needed.
350   if (hasBasePointer(MF)) {
351     CallingConv::ID CC = MF.getFunction()->getCallingConv();
352     const uint32_t* RegMask = getCallPreservedMask(CC);
353     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
354       report_fatal_error(
355         "Stack realignment in presence of dynamic allocas is not supported with"
356         "this calling convention.");
357 
358     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
359                                               false);
360     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
361          I.isValid(); ++I)
362       Reserved.set(*I);
363   }
364 
365   // Mark the segment registers as reserved.
366   Reserved.set(X86::CS);
367   Reserved.set(X86::SS);
368   Reserved.set(X86::DS);
369   Reserved.set(X86::ES);
370   Reserved.set(X86::FS);
371   Reserved.set(X86::GS);
372 
373   // Mark the floating point stack registers as reserved.
374   for (unsigned n = 0; n != 8; ++n)
375     Reserved.set(X86::ST0 + n);
376 
377   // Reserve the registers that only exist in 64-bit mode.
378   if (!Is64Bit) {
379     // These 8-bit registers are part of the x86-64 extension even though their
380     // super-registers are old 32-bits.
381     Reserved.set(X86::SIL);
382     Reserved.set(X86::DIL);
383     Reserved.set(X86::BPL);
384     Reserved.set(X86::SPL);
385 
386     for (unsigned n = 0; n != 8; ++n) {
387       // R8, R9, ...
388       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
389         Reserved.set(*AI);
390 
391       // XMM8, XMM9, ...
392       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
393         Reserved.set(*AI);
394     }
395   }
396   if (!Is64Bit || !Subtarget.hasAVX512()) {
397     for (unsigned n = 16; n != 32; ++n) {
398       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
399         Reserved.set(*AI);
400     }
401   }
402 
403   return Reserved;
404 }
405 
406 //===----------------------------------------------------------------------===//
407 // Stack Frame Processing methods
408 //===----------------------------------------------------------------------===//
409 
410 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
411    const MachineFrameInfo *MFI = MF.getFrameInfo();
412 
413    if (!EnableBasePointer)
414      return false;
415 
416    // When we need stack realignment, we can't address the stack from the frame
417    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
418    // can't address variables from the stack pointer.  MS inline asm can
419    // reference locals while also adjusting the stack pointer.  When we can't
420    // use both the SP and the FP, we need a separate base pointer register.
421    bool CantUseFP = needsStackRealignment(MF);
422    bool CantUseSP =
423        MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
424    return CantUseFP && CantUseSP;
425 }
426 
427 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
428   if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
429     return false;
430 
431   const MachineFrameInfo *MFI = MF.getFrameInfo();
432   const MachineRegisterInfo *MRI = &MF.getRegInfo();
433 
434   // Stack realignment requires a frame pointer.  If we already started
435   // register allocation with frame pointer elimination, it is too late now.
436   if (!MRI->canReserveReg(FramePtr))
437     return false;
438 
439   // If a base pointer is necessary.  Check that it isn't too late to reserve
440   // it.
441   if (MFI->hasVarSizedObjects())
442     return MRI->canReserveReg(BasePtr);
443   return true;
444 }
445 
446 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
447   const MachineFrameInfo *MFI = MF.getFrameInfo();
448   const Function *F = MF.getFunction();
449   unsigned StackAlign =
450     MF.getSubtarget().getFrameLowering()->getStackAlignment();
451   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
452                               F->hasFnAttribute(Attribute::StackAlignment));
453 
454   // If we've requested that we force align the stack do so now.
455   if (ForceStackAlign)
456     return canRealignStack(MF);
457 
458   return requiresRealignment && canRealignStack(MF);
459 }
460 
461 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
462                                            unsigned Reg, int &FrameIdx) const {
463   // Since X86 defines assignCalleeSavedSpillSlots which always return true
464   // this function neither used nor tested.
465   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
466 }
467 
468 void
469 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
470                                      int SPAdj, unsigned FIOperandNum,
471                                      RegScavenger *RS) const {
472   MachineInstr &MI = *II;
473   MachineFunction &MF = *MI.getParent()->getParent();
474   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
475   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
476   unsigned BasePtr;
477 
478   unsigned Opc = MI.getOpcode();
479   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
480   if (hasBasePointer(MF))
481     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
482   else if (needsStackRealignment(MF))
483     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
484   else if (AfterFPPop)
485     BasePtr = StackPtr;
486   else
487     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
488 
489   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
490   // register as source operand, semantic is the same and destination is
491   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
492   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
493     BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
494 
495   // This must be part of a four operand memory reference.  Replace the
496   // FrameIndex with base register with EBP.  Add an offset to the offset.
497   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
498 
499   // Now add the frame object offset to the offset from EBP.
500   int FIOffset;
501   if (AfterFPPop) {
502     // Tail call jmp happens after FP is popped.
503     const MachineFrameInfo *MFI = MF.getFrameInfo();
504     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
505   } else
506     FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
507 
508   if (BasePtr == StackPtr)
509     FIOffset += SPAdj;
510 
511   // The frame index format for stackmaps and patchpoints is different from the
512   // X86 format. It only has a FI and an offset.
513   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
514     assert(BasePtr == FramePtr && "Expected the FP as base register");
515     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
516     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
517     return;
518   }
519 
520   if (MI.getOperand(FIOperandNum+3).isImm()) {
521     // Offset is a 32-bit integer.
522     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
523     int Offset = FIOffset + Imm;
524     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
525            "Requesting 64-bit offset in 32-bit immediate!");
526     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
527   } else {
528     // Offset is symbolic. This is extremely rare.
529     uint64_t Offset = FIOffset +
530       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
531     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
532   }
533 }
534 
535 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
536   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
537   return TFI->hasFP(MF) ? FramePtr : StackPtr;
538 }
539 
540 unsigned X86RegisterInfo::getPtrSizedFrameRegister(
541     const MachineFunction &MF) const {
542   unsigned FrameReg = getFrameRegister(MF);
543   if (Subtarget.isTarget64BitILP32())
544     FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
545   return FrameReg;
546 }
547 
548 namespace llvm {
549 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
550                                 bool High) {
551   switch (VT) {
552   default: llvm_unreachable("Unexpected VT");
553   case MVT::i8:
554     if (High) {
555       switch (Reg) {
556       default: return getX86SubSuperRegister(Reg, MVT::i64);
557       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
558         return X86::SI;
559       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
560         return X86::DI;
561       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
562         return X86::BP;
563       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
564         return X86::SP;
565       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
566         return X86::AH;
567       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
568         return X86::DH;
569       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
570         return X86::CH;
571       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
572         return X86::BH;
573       }
574     } else {
575       switch (Reg) {
576       default: llvm_unreachable("Unexpected register");
577       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
578         return X86::AL;
579       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
580         return X86::DL;
581       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
582         return X86::CL;
583       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
584         return X86::BL;
585       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
586         return X86::SIL;
587       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
588         return X86::DIL;
589       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
590         return X86::BPL;
591       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
592         return X86::SPL;
593       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
594         return X86::R8B;
595       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
596         return X86::R9B;
597       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
598         return X86::R10B;
599       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
600         return X86::R11B;
601       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
602         return X86::R12B;
603       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
604         return X86::R13B;
605       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
606         return X86::R14B;
607       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
608         return X86::R15B;
609       }
610     }
611   case MVT::i16:
612     switch (Reg) {
613     default: llvm_unreachable("Unexpected register");
614     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
615       return X86::AX;
616     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
617       return X86::DX;
618     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
619       return X86::CX;
620     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
621       return X86::BX;
622     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
623       return X86::SI;
624     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
625       return X86::DI;
626     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
627       return X86::BP;
628     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
629       return X86::SP;
630     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
631       return X86::R8W;
632     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
633       return X86::R9W;
634     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
635       return X86::R10W;
636     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
637       return X86::R11W;
638     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
639       return X86::R12W;
640     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
641       return X86::R13W;
642     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
643       return X86::R14W;
644     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
645       return X86::R15W;
646     }
647   case MVT::i32:
648     switch (Reg) {
649     default: llvm_unreachable("Unexpected register");
650     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
651       return X86::EAX;
652     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
653       return X86::EDX;
654     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
655       return X86::ECX;
656     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
657       return X86::EBX;
658     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
659       return X86::ESI;
660     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
661       return X86::EDI;
662     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
663       return X86::EBP;
664     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
665       return X86::ESP;
666     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
667       return X86::R8D;
668     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
669       return X86::R9D;
670     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
671       return X86::R10D;
672     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
673       return X86::R11D;
674     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
675       return X86::R12D;
676     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
677       return X86::R13D;
678     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
679       return X86::R14D;
680     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
681       return X86::R15D;
682     }
683   case MVT::i64:
684     switch (Reg) {
685     default: llvm_unreachable("Unexpected register");
686     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
687       return X86::RAX;
688     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
689       return X86::RDX;
690     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
691       return X86::RCX;
692     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
693       return X86::RBX;
694     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
695       return X86::RSI;
696     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
697       return X86::RDI;
698     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
699       return X86::RBP;
700     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
701       return X86::RSP;
702     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
703       return X86::R8;
704     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
705       return X86::R9;
706     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
707       return X86::R10;
708     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
709       return X86::R11;
710     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
711       return X86::R12;
712     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
713       return X86::R13;
714     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
715       return X86::R14;
716     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
717       return X86::R15;
718     }
719   }
720 }
721 
722 unsigned get512BitSuperRegister(unsigned Reg) {
723   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
724     return X86::ZMM0 + (Reg - X86::XMM0);
725   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
726     return X86::ZMM0 + (Reg - X86::YMM0);
727   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
728     return Reg;
729   llvm_unreachable("Unexpected SIMD register");
730 }
731 
732 }
733