1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
46 
47 static cl::opt<bool>
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49           cl::desc("Enable use of a base pointer for complex stack frames"));
50 
51 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53                          X86_MC::getDwarfRegFlavour(TT, false),
54                          X86_MC::getDwarfRegFlavour(TT, true),
55                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56   X86_MC::InitLLVM2SEHRegisterMapping(this);
57 
58   // Cache some information.
59   Is64Bit = TT.isArch64Bit();
60   IsWin64 = Is64Bit && TT.isOSWindows();
61 
62   // Use a callee-saved register as the base pointer.  These registers must
63   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
64   // requires GOT in the EBX register before function calls via PLT GOT pointer.
65   if (Is64Bit) {
66     SlotSize = 8;
67     // This matches the simplified 32-bit pointer code in the data layout
68     // computation.
69     // FIXME: Should use the data layout?
70     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
74   } else {
75     SlotSize = 4;
76     StackPtr = X86::ESP;
77     FramePtr = X86::EBP;
78     BasePtr = X86::ESI;
79   }
80 }
81 
82 bool
83 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84   // ExeDepsFixer and PostRAScheduler require liveness.
85   return true;
86 }
87 
88 int
89 X86RegisterInfo::getSEHRegNum(unsigned i) const {
90   return getEncodingValue(i);
91 }
92 
93 const TargetRegisterClass *
94 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95                                        unsigned Idx) const {
96   // The sub_8bit sub-register index is more constrained in 32-bit mode.
97   // It behaves just like the sub_8bit_hi index.
98   if (!Is64Bit && Idx == X86::sub_8bit)
99     Idx = X86::sub_8bit_hi;
100 
101   // Forward to TableGen's default version.
102   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
103 }
104 
105 const TargetRegisterClass *
106 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107                                           const TargetRegisterClass *B,
108                                           unsigned SubIdx) const {
109   // The sub_8bit sub-register index is more constrained in 32-bit mode.
110   if (!Is64Bit && SubIdx == X86::sub_8bit) {
111     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
112     if (!A)
113       return nullptr;
114   }
115   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
116 }
117 
118 const TargetRegisterClass *
119 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120                                            const MachineFunction &MF) const {
121   // Don't allow super-classes of GR8_NOREX.  This class is only used after
122   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
123   // to the full GR8 register class in 64-bit mode, so we cannot allow the
124   // reigster class inflation.
125   //
126   // The GR8_NOREX class is always used in a way that won't be constrained to a
127   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128   // full GR8 class.
129   if (RC == &X86::GR8_NOREXRegClass)
130     return RC;
131 
132   const TargetRegisterClass *Super = RC;
133   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
134   do {
135     switch (Super->getID()) {
136     case X86::GR8RegClassID:
137     case X86::GR16RegClassID:
138     case X86::GR32RegClassID:
139     case X86::GR64RegClassID:
140     case X86::FR32RegClassID:
141     case X86::FR64RegClassID:
142     case X86::RFP32RegClassID:
143     case X86::RFP64RegClassID:
144     case X86::RFP80RegClassID:
145     case X86::VR128RegClassID:
146     case X86::VR256RegClassID:
147       // Don't return a super-class that would shrink the spill size.
148       // That can happen with the vector and float classes.
149       if (Super->getSize() == RC->getSize())
150         return Super;
151     }
152     Super = *I++;
153   } while (Super);
154   return RC;
155 }
156 
157 const TargetRegisterClass *
158 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159                                     unsigned Kind) const {
160   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
161   switch (Kind) {
162   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163   case 0: // Normal GPRs.
164     if (Subtarget.isTarget64BitLP64())
165       return &X86::GR64RegClass;
166     return &X86::GR32RegClass;
167   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168     if (Subtarget.isTarget64BitLP64())
169       return &X86::GR64_NOSPRegClass;
170     return &X86::GR32_NOSPRegClass;
171   case 2: // NOREX GPRs.
172     if (Subtarget.isTarget64BitLP64())
173       return &X86::GR64_NOREXRegClass;
174     return &X86::GR32_NOREXRegClass;
175   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
176     if (Subtarget.isTarget64BitLP64())
177       return &X86::GR64_NOREX_NOSPRegClass;
178     return &X86::GR32_NOREX_NOSPRegClass;
179   case 4: // Available for tailcall (not callee-saved GPRs).
180     const Function *F = MF.getFunction();
181     if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
182       return &X86::GR64_TCW64RegClass;
183     else if (Is64Bit)
184       return &X86::GR64_TCRegClass;
185 
186     bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
187     if (hasHipeCC)
188       return &X86::GR32RegClass;
189     return &X86::GR32_TCRegClass;
190   }
191 }
192 
193 const TargetRegisterClass *
194 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
195   if (RC == &X86::CCRRegClass) {
196     if (Is64Bit)
197       return &X86::GR64RegClass;
198     else
199       return &X86::GR32RegClass;
200   }
201   return RC;
202 }
203 
204 unsigned
205 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
206                                      MachineFunction &MF) const {
207   const X86FrameLowering *TFI = getFrameLowering(MF);
208 
209   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
210   switch (RC->getID()) {
211   default:
212     return 0;
213   case X86::GR32RegClassID:
214     return 4 - FPDiff;
215   case X86::GR64RegClassID:
216     return 12 - FPDiff;
217   case X86::VR128RegClassID:
218     return Is64Bit ? 10 : 4;
219   case X86::VR64RegClassID:
220     return 4;
221   }
222 }
223 
224 const MCPhysReg *
225 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
226   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
227   bool HasAVX = Subtarget.hasAVX();
228   bool HasAVX512 = Subtarget.hasAVX512();
229   bool CallsEHReturn = MF->getMMI().callsEHReturn();
230 
231   assert(MF && "MachineFunction required");
232   switch (MF->getFunction()->getCallingConv()) {
233   case CallingConv::GHC:
234   case CallingConv::HiPE:
235     return CSR_NoRegs_SaveList;
236   case CallingConv::AnyReg:
237     if (HasAVX)
238       return CSR_64_AllRegs_AVX_SaveList;
239     return CSR_64_AllRegs_SaveList;
240   case CallingConv::PreserveMost:
241     return CSR_64_RT_MostRegs_SaveList;
242   case CallingConv::PreserveAll:
243     if (HasAVX)
244       return CSR_64_RT_AllRegs_AVX_SaveList;
245     return CSR_64_RT_AllRegs_SaveList;
246   case CallingConv::Intel_OCL_BI: {
247     if (HasAVX512 && IsWin64)
248       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
249     if (HasAVX512 && Is64Bit)
250       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
251     if (HasAVX && IsWin64)
252       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
253     if (HasAVX && Is64Bit)
254       return CSR_64_Intel_OCL_BI_AVX_SaveList;
255     if (!HasAVX && !IsWin64 && Is64Bit)
256       return CSR_64_Intel_OCL_BI_SaveList;
257     break;
258   }
259   case CallingConv::HHVM:
260     return CSR_64_HHVM_SaveList;
261   case CallingConv::Cold:
262     if (Is64Bit)
263       return CSR_64_MostRegs_SaveList;
264     break;
265   case CallingConv::X86_64_Win64:
266     return CSR_Win64_SaveList;
267   case CallingConv::X86_64_SysV:
268     if (CallsEHReturn)
269       return CSR_64EHRet_SaveList;
270     return CSR_64_SaveList;
271   default:
272     break;
273   }
274 
275   if (Is64Bit) {
276     if (IsWin64)
277       return CSR_Win64_SaveList;
278     if (CallsEHReturn)
279       return CSR_64EHRet_SaveList;
280     return CSR_64_SaveList;
281   }
282   if (CallsEHReturn)
283     return CSR_32EHRet_SaveList;
284   return CSR_32_SaveList;
285 }
286 
287 const uint32_t *
288 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
289                                       CallingConv::ID CC) const {
290   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
291   bool HasAVX = Subtarget.hasAVX();
292   bool HasAVX512 = Subtarget.hasAVX512();
293 
294   switch (CC) {
295   case CallingConv::GHC:
296   case CallingConv::HiPE:
297     return CSR_NoRegs_RegMask;
298   case CallingConv::AnyReg:
299     if (HasAVX)
300       return CSR_64_AllRegs_AVX_RegMask;
301     return CSR_64_AllRegs_RegMask;
302   case CallingConv::PreserveMost:
303     return CSR_64_RT_MostRegs_RegMask;
304   case CallingConv::PreserveAll:
305     if (HasAVX)
306       return CSR_64_RT_AllRegs_AVX_RegMask;
307     return CSR_64_RT_AllRegs_RegMask;
308   case CallingConv::Intel_OCL_BI: {
309     if (HasAVX512 && IsWin64)
310       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
311     if (HasAVX512 && Is64Bit)
312       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
313     if (HasAVX && IsWin64)
314       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
315     if (HasAVX && Is64Bit)
316       return CSR_64_Intel_OCL_BI_AVX_RegMask;
317     if (!HasAVX && !IsWin64 && Is64Bit)
318       return CSR_64_Intel_OCL_BI_RegMask;
319     break;
320   }
321   case CallingConv::HHVM:
322     return CSR_64_HHVM_RegMask;
323   case CallingConv::Cold:
324     if (Is64Bit)
325       return CSR_64_MostRegs_RegMask;
326     break;
327   default:
328     break;
329   case CallingConv::X86_64_Win64:
330     return CSR_Win64_RegMask;
331   case CallingConv::X86_64_SysV:
332     return CSR_64_RegMask;
333   }
334 
335   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
336   // callsEHReturn().
337   if (Is64Bit) {
338     if (IsWin64)
339       return CSR_Win64_RegMask;
340     return CSR_64_RegMask;
341   }
342   return CSR_32_RegMask;
343 }
344 
345 const uint32_t*
346 X86RegisterInfo::getNoPreservedMask() const {
347   return CSR_NoRegs_RegMask;
348 }
349 
350 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
351   BitVector Reserved(getNumRegs());
352   const X86FrameLowering *TFI = getFrameLowering(MF);
353 
354   // Set the stack-pointer register and its aliases as reserved.
355   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
356        ++I)
357     Reserved.set(*I);
358 
359   // Set the instruction pointer register and its aliases as reserved.
360   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
361        ++I)
362     Reserved.set(*I);
363 
364   // Set the frame-pointer register and its aliases as reserved if needed.
365   if (TFI->hasFP(MF)) {
366     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
367          ++I)
368       Reserved.set(*I);
369   }
370 
371   // Set the base-pointer register and its aliases as reserved if needed.
372   if (hasBasePointer(MF)) {
373     CallingConv::ID CC = MF.getFunction()->getCallingConv();
374     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
375     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
376       report_fatal_error(
377         "Stack realignment in presence of dynamic allocas is not supported with"
378         "this calling convention.");
379 
380     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
381                                               false);
382     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
383          I.isValid(); ++I)
384       Reserved.set(*I);
385   }
386 
387   // Mark the segment registers as reserved.
388   Reserved.set(X86::CS);
389   Reserved.set(X86::SS);
390   Reserved.set(X86::DS);
391   Reserved.set(X86::ES);
392   Reserved.set(X86::FS);
393   Reserved.set(X86::GS);
394 
395   // Mark the floating point stack registers as reserved.
396   for (unsigned n = 0; n != 8; ++n)
397     Reserved.set(X86::ST0 + n);
398 
399   // Reserve the registers that only exist in 64-bit mode.
400   if (!Is64Bit) {
401     // These 8-bit registers are part of the x86-64 extension even though their
402     // super-registers are old 32-bits.
403     Reserved.set(X86::SIL);
404     Reserved.set(X86::DIL);
405     Reserved.set(X86::BPL);
406     Reserved.set(X86::SPL);
407 
408     for (unsigned n = 0; n != 8; ++n) {
409       // R8, R9, ...
410       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
411         Reserved.set(*AI);
412 
413       // XMM8, XMM9, ...
414       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
415         Reserved.set(*AI);
416     }
417   }
418   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
419     for (unsigned n = 16; n != 32; ++n) {
420       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
421         Reserved.set(*AI);
422     }
423   }
424 
425   return Reserved;
426 }
427 
428 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
429   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
430   // because the calling convention defines the EFLAGS register as NOT
431   // preserved.
432   //
433   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
434   // an assert to track this and clear the register afterwards to avoid
435   // unnecessary crashes during release builds.
436   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
437          "EFLAGS are not live-out from a patchpoint.");
438 
439   // Also clean other registers that don't need preserving (IP).
440   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
441     Mask[Reg / 32] &= ~(1U << (Reg % 32));
442 }
443 
444 //===----------------------------------------------------------------------===//
445 // Stack Frame Processing methods
446 //===----------------------------------------------------------------------===//
447 
448 static bool CantUseSP(const MachineFrameInfo *MFI) {
449   return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
450 }
451 
452 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
453    const MachineFrameInfo *MFI = MF.getFrameInfo();
454 
455    if (!EnableBasePointer)
456      return false;
457 
458    // When we need stack realignment, we can't address the stack from the frame
459    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
460    // can't address variables from the stack pointer.  MS inline asm can
461    // reference locals while also adjusting the stack pointer.  When we can't
462    // use both the SP and the FP, we need a separate base pointer register.
463    bool CantUseFP = needsStackRealignment(MF);
464    return CantUseFP && CantUseSP(MFI);
465 }
466 
467 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
468   if (!TargetRegisterInfo::canRealignStack(MF))
469     return false;
470 
471   const MachineFrameInfo *MFI = MF.getFrameInfo();
472   const MachineRegisterInfo *MRI = &MF.getRegInfo();
473 
474   // Stack realignment requires a frame pointer.  If we already started
475   // register allocation with frame pointer elimination, it is too late now.
476   if (!MRI->canReserveReg(FramePtr))
477     return false;
478 
479   // If a base pointer is necessary.  Check that it isn't too late to reserve
480   // it.
481   if (CantUseSP(MFI))
482     return MRI->canReserveReg(BasePtr);
483   return true;
484 }
485 
486 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
487                                            unsigned Reg, int &FrameIdx) const {
488   // Since X86 defines assignCalleeSavedSpillSlots which always return true
489   // this function neither used nor tested.
490   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
491 }
492 
493 void
494 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
495                                      int SPAdj, unsigned FIOperandNum,
496                                      RegScavenger *RS) const {
497   MachineInstr &MI = *II;
498   MachineFunction &MF = *MI.getParent()->getParent();
499   const X86FrameLowering *TFI = getFrameLowering(MF);
500   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
501   unsigned BasePtr;
502 
503   unsigned Opc = MI.getOpcode();
504   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
505                     Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
506 
507   if (hasBasePointer(MF))
508     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
509   else if (needsStackRealignment(MF))
510     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
511   else if (AfterFPPop)
512     BasePtr = StackPtr;
513   else
514     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
515 
516   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
517   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
518   // offset is from the traditional base pointer location.  On 64-bit, the
519   // offset is from the SP at the end of the prologue, not the FP location. This
520   // matches the behavior of llvm.frameaddress.
521   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
522     MachineOperand &FI = MI.getOperand(FIOperandNum);
523     bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
524     int Offset;
525     unsigned IgnoredFrameReg;
526     if (IsWinEH)
527       Offset =
528           TFI->getFrameIndexReferenceFromSP(MF, FrameIndex, IgnoredFrameReg);
529     else
530       Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
531     FI.ChangeToImmediate(Offset);
532     return;
533   }
534 
535   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
536   // register as source operand, semantic is the same and destination is
537   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
538   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
539     BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
540 
541   // This must be part of a four operand memory reference.  Replace the
542   // FrameIndex with base register with EBP.  Add an offset to the offset.
543   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
544 
545   // Now add the frame object offset to the offset from EBP.
546   int FIOffset;
547   unsigned IgnoredFrameReg;
548   if (AfterFPPop) {
549     // Tail call jmp happens after FP is popped.
550     const MachineFrameInfo *MFI = MF.getFrameInfo();
551     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
552   } else
553     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
554 
555   if (BasePtr == StackPtr)
556     FIOffset += SPAdj;
557 
558   // The frame index format for stackmaps and patchpoints is different from the
559   // X86 format. It only has a FI and an offset.
560   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
561     assert(BasePtr == FramePtr && "Expected the FP as base register");
562     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
563     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
564     return;
565   }
566 
567   if (MI.getOperand(FIOperandNum+3).isImm()) {
568     // Offset is a 32-bit integer.
569     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
570     int Offset = FIOffset + Imm;
571     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
572            "Requesting 64-bit offset in 32-bit immediate!");
573     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
574   } else {
575     // Offset is symbolic. This is extremely rare.
576     uint64_t Offset = FIOffset +
577       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
578     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
579   }
580 }
581 
582 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
583   const X86FrameLowering *TFI = getFrameLowering(MF);
584   return TFI->hasFP(MF) ? FramePtr : StackPtr;
585 }
586 
587 unsigned
588 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
589   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
590   unsigned FrameReg = getFrameRegister(MF);
591   if (Subtarget.isTarget64BitILP32())
592     FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
593   return FrameReg;
594 }
595 
596 namespace llvm {
597 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
598                                       bool High) {
599   switch (VT) {
600   default: return 0;
601   case MVT::i8:
602     if (High) {
603       switch (Reg) {
604       default: return getX86SubSuperRegister(Reg, MVT::i64);
605       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
606         return X86::SI;
607       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
608         return X86::DI;
609       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
610         return X86::BP;
611       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
612         return X86::SP;
613       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
614         return X86::AH;
615       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
616         return X86::DH;
617       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
618         return X86::CH;
619       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
620         return X86::BH;
621       }
622     } else {
623       switch (Reg) {
624       default: return 0;
625       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
626         return X86::AL;
627       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
628         return X86::DL;
629       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
630         return X86::CL;
631       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
632         return X86::BL;
633       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
634         return X86::SIL;
635       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
636         return X86::DIL;
637       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
638         return X86::BPL;
639       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
640         return X86::SPL;
641       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
642         return X86::R8B;
643       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
644         return X86::R9B;
645       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
646         return X86::R10B;
647       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
648         return X86::R11B;
649       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
650         return X86::R12B;
651       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
652         return X86::R13B;
653       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
654         return X86::R14B;
655       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
656         return X86::R15B;
657       }
658     }
659   case MVT::i16:
660     switch (Reg) {
661     default: return 0;
662     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
663       return X86::AX;
664     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
665       return X86::DX;
666     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
667       return X86::CX;
668     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
669       return X86::BX;
670     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
671       return X86::SI;
672     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
673       return X86::DI;
674     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
675       return X86::BP;
676     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
677       return X86::SP;
678     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
679       return X86::R8W;
680     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
681       return X86::R9W;
682     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
683       return X86::R10W;
684     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
685       return X86::R11W;
686     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
687       return X86::R12W;
688     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
689       return X86::R13W;
690     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
691       return X86::R14W;
692     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
693       return X86::R15W;
694     }
695   case MVT::i32:
696     switch (Reg) {
697     default: return 0;
698     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
699       return X86::EAX;
700     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
701       return X86::EDX;
702     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
703       return X86::ECX;
704     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
705       return X86::EBX;
706     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
707       return X86::ESI;
708     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
709       return X86::EDI;
710     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
711       return X86::EBP;
712     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
713       return X86::ESP;
714     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
715       return X86::R8D;
716     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
717       return X86::R9D;
718     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
719       return X86::R10D;
720     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
721       return X86::R11D;
722     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
723       return X86::R12D;
724     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
725       return X86::R13D;
726     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
727       return X86::R14D;
728     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
729       return X86::R15D;
730     }
731   case MVT::i64:
732     switch (Reg) {
733     default: return 0;
734     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
735       return X86::RAX;
736     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
737       return X86::RDX;
738     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
739       return X86::RCX;
740     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
741       return X86::RBX;
742     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
743       return X86::RSI;
744     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
745       return X86::RDI;
746     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
747       return X86::RBP;
748     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
749       return X86::RSP;
750     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
751       return X86::R8;
752     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
753       return X86::R9;
754     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
755       return X86::R10;
756     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
757       return X86::R11;
758     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
759       return X86::R12;
760     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
761       return X86::R13;
762     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
763       return X86::R14;
764     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
765       return X86::R15;
766     }
767   }
768 }
769 
770 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
771                                 bool High) {
772   unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
773   if (Res == 0)
774     llvm_unreachable("Unexpected register or VT");
775   return Res;
776 }
777 
778 unsigned get512BitSuperRegister(unsigned Reg) {
779   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
780     return X86::ZMM0 + (Reg - X86::XMM0);
781   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
782     return X86::ZMM0 + (Reg - X86::YMM0);
783   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
784     return Reg;
785   llvm_unreachable("Unexpected SIMD register");
786 }
787 
788 }
789