1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
11 // on X86.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/TargetFrameLowering.h"
27 #include "llvm/CodeGen/TargetInstrInfo.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 
36 using namespace llvm;
37 
38 #define GET_REGINFO_TARGET_DESC
39 #include "X86GenRegisterInfo.inc"
40 
41 static cl::opt<bool>
42 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
43           cl::desc("Enable use of a base pointer for complex stack frames"));
44 
45 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
46     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
47                          X86_MC::getDwarfRegFlavour(TT, false),
48                          X86_MC::getDwarfRegFlavour(TT, true),
49                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
50   X86_MC::initLLVMToSEHAndCVRegMapping(this);
51 
52   // Cache some information.
53   Is64Bit = TT.isArch64Bit();
54   IsWin64 = Is64Bit && TT.isOSWindows();
55 
56   // Use a callee-saved register as the base pointer.  These registers must
57   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
58   // requires GOT in the EBX register before function calls via PLT GOT pointer.
59   if (Is64Bit) {
60     SlotSize = 8;
61     // This matches the simplified 32-bit pointer code in the data layout
62     // computation.
63     // FIXME: Should use the data layout?
64     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
65     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
66     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
67     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
68   } else {
69     SlotSize = 4;
70     StackPtr = X86::ESP;
71     FramePtr = X86::EBP;
72     BasePtr = X86::ESI;
73   }
74 }
75 
76 int
77 X86RegisterInfo::getSEHRegNum(unsigned i) const {
78   return getEncodingValue(i);
79 }
80 
81 const TargetRegisterClass *
82 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
83                                        unsigned Idx) const {
84   // The sub_8bit sub-register index is more constrained in 32-bit mode.
85   // It behaves just like the sub_8bit_hi index.
86   if (!Is64Bit && Idx == X86::sub_8bit)
87     Idx = X86::sub_8bit_hi;
88 
89   // Forward to TableGen's default version.
90   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
91 }
92 
93 const TargetRegisterClass *
94 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
95                                           const TargetRegisterClass *B,
96                                           unsigned SubIdx) const {
97   // The sub_8bit sub-register index is more constrained in 32-bit mode.
98   if (!Is64Bit && SubIdx == X86::sub_8bit) {
99     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
100     if (!A)
101       return nullptr;
102   }
103   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
104 }
105 
106 const TargetRegisterClass *
107 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
108                                            const MachineFunction &MF) const {
109   // Don't allow super-classes of GR8_NOREX.  This class is only used after
110   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
111   // to the full GR8 register class in 64-bit mode, so we cannot allow the
112   // reigster class inflation.
113   //
114   // The GR8_NOREX class is always used in a way that won't be constrained to a
115   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
116   // full GR8 class.
117   if (RC == &X86::GR8_NOREXRegClass)
118     return RC;
119 
120   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
121 
122   const TargetRegisterClass *Super = RC;
123   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
124   do {
125     switch (Super->getID()) {
126     case X86::FR32RegClassID:
127     case X86::FR64RegClassID:
128       // If AVX-512 isn't supported we should only inflate to these classes.
129       if (!Subtarget.hasAVX512() &&
130           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
131         return Super;
132       break;
133     case X86::VR128RegClassID:
134     case X86::VR256RegClassID:
135       // If VLX isn't supported we should only inflate to these classes.
136       if (!Subtarget.hasVLX() &&
137           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
138         return Super;
139       break;
140     case X86::VR128XRegClassID:
141     case X86::VR256XRegClassID:
142       // If VLX isn't support we shouldn't inflate to these classes.
143       if (Subtarget.hasVLX() &&
144           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
145         return Super;
146       break;
147     case X86::FR32XRegClassID:
148     case X86::FR64XRegClassID:
149       // If AVX-512 isn't support we shouldn't inflate to these classes.
150       if (Subtarget.hasAVX512() &&
151           getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
152         return Super;
153       break;
154     case X86::GR8RegClassID:
155     case X86::GR16RegClassID:
156     case X86::GR32RegClassID:
157     case X86::GR64RegClassID:
158     case X86::RFP32RegClassID:
159     case X86::RFP64RegClassID:
160     case X86::RFP80RegClassID:
161     case X86::VR512_0_15RegClassID:
162     case X86::VR512RegClassID:
163       // Don't return a super-class that would shrink the spill size.
164       // That can happen with the vector and float classes.
165       if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
166         return Super;
167     }
168     Super = *I++;
169   } while (Super);
170   return RC;
171 }
172 
173 const TargetRegisterClass *
174 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
175                                     unsigned Kind) const {
176   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
177   switch (Kind) {
178   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
179   case 0: // Normal GPRs.
180     if (Subtarget.isTarget64BitLP64())
181       return &X86::GR64RegClass;
182     // If the target is 64bit but we have been told to use 32bit addresses,
183     // we can still use 64-bit register as long as we know the high bits
184     // are zeros.
185     // Reflect that in the returned register class.
186     if (Is64Bit) {
187       // When the target also allows 64-bit frame pointer and we do have a
188       // frame, this is fine to use it for the address accesses as well.
189       const X86FrameLowering *TFI = getFrameLowering(MF);
190       return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
191                  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
192                  : &X86::LOW32_ADDR_ACCESSRegClass;
193     }
194     return &X86::GR32RegClass;
195   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
196     if (Subtarget.isTarget64BitLP64())
197       return &X86::GR64_NOSPRegClass;
198     // NOSP does not contain RIP, so no special case here.
199     return &X86::GR32_NOSPRegClass;
200   case 2: // NOREX GPRs.
201     if (Subtarget.isTarget64BitLP64())
202       return &X86::GR64_NOREXRegClass;
203     return &X86::GR32_NOREXRegClass;
204   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
205     if (Subtarget.isTarget64BitLP64())
206       return &X86::GR64_NOREX_NOSPRegClass;
207     // NOSP does not contain RIP, so no special case here.
208     return &X86::GR32_NOREX_NOSPRegClass;
209   case 4: // Available for tailcall (not callee-saved GPRs).
210     return getGPRsForTailCall(MF);
211   }
212 }
213 
214 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
215                                            unsigned DefSubReg,
216                                            const TargetRegisterClass *SrcRC,
217                                            unsigned SrcSubReg) const {
218   // Prevent rewriting a copy where the destination size is larger than the
219   // input size. See PR41619.
220   // FIXME: Should this be factored into the base implementation somehow.
221   if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
222       SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
223     return false;
224 
225   return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
226                                                   SrcRC, SrcSubReg);
227 }
228 
229 const TargetRegisterClass *
230 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
231   const Function &F = MF.getFunction();
232   if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
233     return &X86::GR64_TCW64RegClass;
234   else if (Is64Bit)
235     return &X86::GR64_TCRegClass;
236 
237   bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
238   if (hasHipeCC)
239     return &X86::GR32RegClass;
240   return &X86::GR32_TCRegClass;
241 }
242 
243 const TargetRegisterClass *
244 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
245   if (RC == &X86::CCRRegClass) {
246     if (Is64Bit)
247       return &X86::GR64RegClass;
248     else
249       return &X86::GR32RegClass;
250   }
251   return RC;
252 }
253 
254 unsigned
255 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
256                                      MachineFunction &MF) const {
257   const X86FrameLowering *TFI = getFrameLowering(MF);
258 
259   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
260   switch (RC->getID()) {
261   default:
262     return 0;
263   case X86::GR32RegClassID:
264     return 4 - FPDiff;
265   case X86::GR64RegClassID:
266     return 12 - FPDiff;
267   case X86::VR128RegClassID:
268     return Is64Bit ? 10 : 4;
269   case X86::VR64RegClassID:
270     return 4;
271   }
272 }
273 
274 const MCPhysReg *
275 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
276   assert(MF && "MachineFunction required");
277 
278   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
279   const Function &F = MF->getFunction();
280   bool HasSSE = Subtarget.hasSSE1();
281   bool HasAVX = Subtarget.hasAVX();
282   bool HasAVX512 = Subtarget.hasAVX512();
283   bool CallsEHReturn = MF->callsEHReturn();
284 
285   CallingConv::ID CC = F.getCallingConv();
286 
287   // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
288   // convention because it has the CSR list.
289   if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
290     CC = CallingConv::X86_INTR;
291 
292   switch (CC) {
293   case CallingConv::GHC:
294   case CallingConv::HiPE:
295     return CSR_NoRegs_SaveList;
296   case CallingConv::AnyReg:
297     if (HasAVX)
298       return CSR_64_AllRegs_AVX_SaveList;
299     return CSR_64_AllRegs_SaveList;
300   case CallingConv::PreserveMost:
301     return CSR_64_RT_MostRegs_SaveList;
302   case CallingConv::PreserveAll:
303     if (HasAVX)
304       return CSR_64_RT_AllRegs_AVX_SaveList;
305     return CSR_64_RT_AllRegs_SaveList;
306   case CallingConv::CXX_FAST_TLS:
307     if (Is64Bit)
308       return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
309              CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
310     break;
311   case CallingConv::Intel_OCL_BI: {
312     if (HasAVX512 && IsWin64)
313       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
314     if (HasAVX512 && Is64Bit)
315       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
316     if (HasAVX && IsWin64)
317       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
318     if (HasAVX && Is64Bit)
319       return CSR_64_Intel_OCL_BI_AVX_SaveList;
320     if (!HasAVX && !IsWin64 && Is64Bit)
321       return CSR_64_Intel_OCL_BI_SaveList;
322     break;
323   }
324   case CallingConv::HHVM:
325     return CSR_64_HHVM_SaveList;
326   case CallingConv::X86_RegCall:
327     if (Is64Bit) {
328       if (IsWin64) {
329         return (HasSSE ? CSR_Win64_RegCall_SaveList :
330                          CSR_Win64_RegCall_NoSSE_SaveList);
331       } else {
332         return (HasSSE ? CSR_SysV64_RegCall_SaveList :
333                          CSR_SysV64_RegCall_NoSSE_SaveList);
334       }
335     } else {
336       return (HasSSE ? CSR_32_RegCall_SaveList :
337                        CSR_32_RegCall_NoSSE_SaveList);
338     }
339   case CallingConv::CFGuard_Check:
340     assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
341     return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
342                    : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
343   case CallingConv::Cold:
344     if (Is64Bit)
345       return CSR_64_MostRegs_SaveList;
346     break;
347   case CallingConv::Win64:
348     if (!HasSSE)
349       return CSR_Win64_NoSSE_SaveList;
350     return CSR_Win64_SaveList;
351   case CallingConv::X86_64_SysV:
352     if (CallsEHReturn)
353       return CSR_64EHRet_SaveList;
354     return CSR_64_SaveList;
355   case CallingConv::X86_INTR:
356     if (Is64Bit) {
357       if (HasAVX512)
358         return CSR_64_AllRegs_AVX512_SaveList;
359       if (HasAVX)
360         return CSR_64_AllRegs_AVX_SaveList;
361       if (HasSSE)
362         return CSR_64_AllRegs_SaveList;
363       return CSR_64_AllRegs_NoSSE_SaveList;
364     } else {
365       if (HasAVX512)
366         return CSR_32_AllRegs_AVX512_SaveList;
367       if (HasAVX)
368         return CSR_32_AllRegs_AVX_SaveList;
369       if (HasSSE)
370         return CSR_32_AllRegs_SSE_SaveList;
371       return CSR_32_AllRegs_SaveList;
372     }
373   default:
374     break;
375   }
376 
377   if (Is64Bit) {
378     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
379                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
380     if (IsSwiftCC)
381       return IsWin64 ? CSR_Win64_SwiftError_SaveList
382                      : CSR_64_SwiftError_SaveList;
383 
384     if (IsWin64)
385       return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
386     if (CallsEHReturn)
387       return CSR_64EHRet_SaveList;
388     return CSR_64_SaveList;
389   }
390 
391   return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
392 }
393 
394 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
395     const MachineFunction *MF) const {
396   assert(MF && "Invalid MachineFunction pointer.");
397   if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
398       MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
399     return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
400   return nullptr;
401 }
402 
403 const uint32_t *
404 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
405                                       CallingConv::ID CC) const {
406   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
407   bool HasSSE = Subtarget.hasSSE1();
408   bool HasAVX = Subtarget.hasAVX();
409   bool HasAVX512 = Subtarget.hasAVX512();
410 
411   switch (CC) {
412   case CallingConv::GHC:
413   case CallingConv::HiPE:
414     return CSR_NoRegs_RegMask;
415   case CallingConv::AnyReg:
416     if (HasAVX)
417       return CSR_64_AllRegs_AVX_RegMask;
418     return CSR_64_AllRegs_RegMask;
419   case CallingConv::PreserveMost:
420     return CSR_64_RT_MostRegs_RegMask;
421   case CallingConv::PreserveAll:
422     if (HasAVX)
423       return CSR_64_RT_AllRegs_AVX_RegMask;
424     return CSR_64_RT_AllRegs_RegMask;
425   case CallingConv::CXX_FAST_TLS:
426     if (Is64Bit)
427       return CSR_64_TLS_Darwin_RegMask;
428     break;
429   case CallingConv::Intel_OCL_BI: {
430     if (HasAVX512 && IsWin64)
431       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
432     if (HasAVX512 && Is64Bit)
433       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
434     if (HasAVX && IsWin64)
435       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
436     if (HasAVX && Is64Bit)
437       return CSR_64_Intel_OCL_BI_AVX_RegMask;
438     if (!HasAVX && !IsWin64 && Is64Bit)
439       return CSR_64_Intel_OCL_BI_RegMask;
440     break;
441   }
442   case CallingConv::HHVM:
443     return CSR_64_HHVM_RegMask;
444   case CallingConv::X86_RegCall:
445     if (Is64Bit) {
446       if (IsWin64) {
447         return (HasSSE ? CSR_Win64_RegCall_RegMask :
448                          CSR_Win64_RegCall_NoSSE_RegMask);
449       } else {
450         return (HasSSE ? CSR_SysV64_RegCall_RegMask :
451                          CSR_SysV64_RegCall_NoSSE_RegMask);
452       }
453     } else {
454       return (HasSSE ? CSR_32_RegCall_RegMask :
455                        CSR_32_RegCall_NoSSE_RegMask);
456     }
457   case CallingConv::CFGuard_Check:
458     assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
459     return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
460                    : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
461   case CallingConv::Cold:
462     if (Is64Bit)
463       return CSR_64_MostRegs_RegMask;
464     break;
465   case CallingConv::Win64:
466     return CSR_Win64_RegMask;
467   case CallingConv::X86_64_SysV:
468     return CSR_64_RegMask;
469   case CallingConv::X86_INTR:
470     if (Is64Bit) {
471       if (HasAVX512)
472         return CSR_64_AllRegs_AVX512_RegMask;
473       if (HasAVX)
474         return CSR_64_AllRegs_AVX_RegMask;
475       if (HasSSE)
476         return CSR_64_AllRegs_RegMask;
477       return CSR_64_AllRegs_NoSSE_RegMask;
478     } else {
479       if (HasAVX512)
480         return CSR_32_AllRegs_AVX512_RegMask;
481       if (HasAVX)
482         return CSR_32_AllRegs_AVX_RegMask;
483       if (HasSSE)
484         return CSR_32_AllRegs_SSE_RegMask;
485       return CSR_32_AllRegs_RegMask;
486     }
487   default:
488     break;
489   }
490 
491   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
492   // callsEHReturn().
493   if (Is64Bit) {
494     const Function &F = MF.getFunction();
495     bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
496                      F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
497     if (IsSwiftCC)
498       return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
499     return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
500   }
501 
502   return CSR_32_RegMask;
503 }
504 
505 const uint32_t*
506 X86RegisterInfo::getNoPreservedMask() const {
507   return CSR_NoRegs_RegMask;
508 }
509 
510 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
511   return CSR_64_TLS_Darwin_RegMask;
512 }
513 
514 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
515   BitVector Reserved(getNumRegs());
516   const X86FrameLowering *TFI = getFrameLowering(MF);
517 
518   // Set the floating point control register as reserved.
519   Reserved.set(X86::FPCW);
520 
521   // Set the floating point status register as reserved.
522   Reserved.set(X86::FPSW);
523 
524   // Set the SIMD floating point control register as reserved.
525   Reserved.set(X86::MXCSR);
526 
527   // Set the stack-pointer register and its aliases as reserved.
528   for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
529     Reserved.set(SubReg);
530 
531   // Set the Shadow Stack Pointer as reserved.
532   Reserved.set(X86::SSP);
533 
534   // Set the instruction pointer register and its aliases as reserved.
535   for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
536     Reserved.set(SubReg);
537 
538   // Set the frame-pointer register and its aliases as reserved if needed.
539   if (TFI->hasFP(MF)) {
540     for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
541       Reserved.set(SubReg);
542   }
543 
544   // Set the base-pointer register and its aliases as reserved if needed.
545   if (hasBasePointer(MF)) {
546     CallingConv::ID CC = MF.getFunction().getCallingConv();
547     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
548     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
549       report_fatal_error(
550         "Stack realignment in presence of dynamic allocas is not supported with"
551         "this calling convention.");
552 
553     Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
554     for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
555       Reserved.set(SubReg);
556   }
557 
558   // Mark the segment registers as reserved.
559   Reserved.set(X86::CS);
560   Reserved.set(X86::SS);
561   Reserved.set(X86::DS);
562   Reserved.set(X86::ES);
563   Reserved.set(X86::FS);
564   Reserved.set(X86::GS);
565 
566   // Mark the floating point stack registers as reserved.
567   for (unsigned n = 0; n != 8; ++n)
568     Reserved.set(X86::ST0 + n);
569 
570   // Reserve the registers that only exist in 64-bit mode.
571   if (!Is64Bit) {
572     // These 8-bit registers are part of the x86-64 extension even though their
573     // super-registers are old 32-bits.
574     Reserved.set(X86::SIL);
575     Reserved.set(X86::DIL);
576     Reserved.set(X86::BPL);
577     Reserved.set(X86::SPL);
578     Reserved.set(X86::SIH);
579     Reserved.set(X86::DIH);
580     Reserved.set(X86::BPH);
581     Reserved.set(X86::SPH);
582 
583     for (unsigned n = 0; n != 8; ++n) {
584       // R8, R9, ...
585       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
586         Reserved.set(*AI);
587 
588       // XMM8, XMM9, ...
589       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
590         Reserved.set(*AI);
591     }
592   }
593   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
594     for (unsigned n = 16; n != 32; ++n) {
595       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
596         Reserved.set(*AI);
597     }
598   }
599 
600   assert(checkAllSuperRegsMarked(Reserved,
601                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
602                                   X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
603   return Reserved;
604 }
605 
606 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
607   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
608   // because the calling convention defines the EFLAGS register as NOT
609   // preserved.
610   //
611   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
612   // an assert to track this and clear the register afterwards to avoid
613   // unnecessary crashes during release builds.
614   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
615          "EFLAGS are not live-out from a patchpoint.");
616 
617   // Also clean other registers that don't need preserving (IP).
618   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
619     Mask[Reg / 32] &= ~(1U << (Reg % 32));
620 }
621 
622 //===----------------------------------------------------------------------===//
623 // Stack Frame Processing methods
624 //===----------------------------------------------------------------------===//
625 
626 static bool CantUseSP(const MachineFrameInfo &MFI) {
627   return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
628 }
629 
630 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
631   const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
632   if (X86FI->hasPreallocatedCall())
633     return true;
634 
635   const MachineFrameInfo &MFI = MF.getFrameInfo();
636 
637   if (!EnableBasePointer)
638     return false;
639 
640   // When we need stack realignment, we can't address the stack from the frame
641   // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
642   // can't address variables from the stack pointer.  MS inline asm can
643   // reference locals while also adjusting the stack pointer.  When we can't
644   // use both the SP and the FP, we need a separate base pointer register.
645   bool CantUseFP = needsStackRealignment(MF);
646   return CantUseFP && CantUseSP(MFI);
647 }
648 
649 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
650   if (!TargetRegisterInfo::canRealignStack(MF))
651     return false;
652 
653   const MachineFrameInfo &MFI = MF.getFrameInfo();
654   const MachineRegisterInfo *MRI = &MF.getRegInfo();
655 
656   // Stack realignment requires a frame pointer.  If we already started
657   // register allocation with frame pointer elimination, it is too late now.
658   if (!MRI->canReserveReg(FramePtr))
659     return false;
660 
661   // If a base pointer is necessary.  Check that it isn't too late to reserve
662   // it.
663   if (CantUseSP(MFI))
664     return MRI->canReserveReg(BasePtr);
665   return true;
666 }
667 
668 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
669 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
670 // TODO: In this case we should be really trying first to entirely eliminate
671 // this instruction which is a plain copy.
672 static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
673   MachineInstr &MI = *II;
674   unsigned Opc = II->getOpcode();
675   // Check if this is a LEA of the form 'lea (%esp), %ebx'
676   if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
677       MI.getOperand(2).getImm() != 1 ||
678       MI.getOperand(3).getReg() != X86::NoRegister ||
679       MI.getOperand(4).getImm() != 0 ||
680       MI.getOperand(5).getReg() != X86::NoRegister)
681     return false;
682   Register BasePtr = MI.getOperand(1).getReg();
683   // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
684   // be replaced with a 32-bit operand MOV which will zero extend the upper
685   // 32-bits of the super register.
686   if (Opc == X86::LEA64_32r)
687     BasePtr = getX86SubSuperRegister(BasePtr, 32);
688   Register NewDestReg = MI.getOperand(0).getReg();
689   const X86InstrInfo *TII =
690       MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
691   TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
692                    MI.getOperand(1).isKill());
693   MI.eraseFromParent();
694   return true;
695 }
696 
697 static bool isFuncletReturnInstr(MachineInstr &MI) {
698   switch (MI.getOpcode()) {
699   case X86::CATCHRET:
700   case X86::CLEANUPRET:
701     return true;
702   default:
703     return false;
704   }
705   llvm_unreachable("impossible");
706 }
707 
708 void
709 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
710                                      int SPAdj, unsigned FIOperandNum,
711                                      RegScavenger *RS) const {
712   MachineInstr &MI = *II;
713   MachineBasicBlock &MBB = *MI.getParent();
714   MachineFunction &MF = *MBB.getParent();
715   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
716   bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
717                                                : isFuncletReturnInstr(*MBBI);
718   const X86FrameLowering *TFI = getFrameLowering(MF);
719   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
720 
721   // Determine base register and offset.
722   int FIOffset;
723   Register BasePtr;
724   if (MI.isReturn()) {
725     assert((!needsStackRealignment(MF) ||
726            MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
727            "Return instruction can only reference SP relative frame objects");
728     FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
729   } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
730     FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr);
731   } else {
732     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
733   }
734 
735   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
736   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
737   // offset is from the traditional base pointer location.  On 64-bit, the
738   // offset is from the SP at the end of the prologue, not the FP location. This
739   // matches the behavior of llvm.frameaddress.
740   unsigned Opc = MI.getOpcode();
741   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
742     MachineOperand &FI = MI.getOperand(FIOperandNum);
743     FI.ChangeToImmediate(FIOffset);
744     return;
745   }
746 
747   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
748   // register as source operand, semantic is the same and destination is
749   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
750   // Don't change BasePtr since it is used later for stack adjustment.
751   Register MachineBasePtr = BasePtr;
752   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
753     MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
754 
755   // This must be part of a four operand memory reference.  Replace the
756   // FrameIndex with base register.  Add an offset to the offset.
757   MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
758 
759   if (BasePtr == StackPtr)
760     FIOffset += SPAdj;
761 
762   // The frame index format for stackmaps and patchpoints is different from the
763   // X86 format. It only has a FI and an offset.
764   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
765     assert(BasePtr == FramePtr && "Expected the FP as base register");
766     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
767     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
768     return;
769   }
770 
771   if (MI.getOperand(FIOperandNum+3).isImm()) {
772     // Offset is a 32-bit integer.
773     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
774     int Offset = FIOffset + Imm;
775     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
776            "Requesting 64-bit offset in 32-bit immediate!");
777     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
778       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
779   } else {
780     // Offset is symbolic. This is extremely rare.
781     uint64_t Offset = FIOffset +
782       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
783     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
784   }
785 }
786 
787 unsigned X86RegisterInfo::findDeadCallerSavedReg(
788     MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const {
789   const MachineFunction *MF = MBB.getParent();
790   if (MF->callsEHReturn())
791     return 0;
792 
793   const TargetRegisterClass &AvailableRegs = *getGPRsForTailCall(*MF);
794 
795   if (MBBI == MBB.end())
796     return 0;
797 
798   switch (MBBI->getOpcode()) {
799   default:
800     return 0;
801   case TargetOpcode::PATCHABLE_RET:
802   case X86::RET:
803   case X86::RETL:
804   case X86::RETQ:
805   case X86::RETIL:
806   case X86::RETIQ:
807   case X86::TCRETURNdi:
808   case X86::TCRETURNri:
809   case X86::TCRETURNmi:
810   case X86::TCRETURNdi64:
811   case X86::TCRETURNri64:
812   case X86::TCRETURNmi64:
813   case X86::EH_RETURN:
814   case X86::EH_RETURN64: {
815     SmallSet<uint16_t, 8> Uses;
816     for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
817       MachineOperand &MO = MBBI->getOperand(I);
818       if (!MO.isReg() || MO.isDef())
819         continue;
820       Register Reg = MO.getReg();
821       if (!Reg)
822         continue;
823       for (MCRegAliasIterator AI(Reg, this, true); AI.isValid(); ++AI)
824         Uses.insert(*AI);
825     }
826 
827     for (auto CS : AvailableRegs)
828       if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
829         return CS;
830   }
831   }
832 
833   return 0;
834 }
835 
836 Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
837   const X86FrameLowering *TFI = getFrameLowering(MF);
838   return TFI->hasFP(MF) ? FramePtr : StackPtr;
839 }
840 
841 unsigned
842 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
843   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
844   Register FrameReg = getFrameRegister(MF);
845   if (Subtarget.isTarget64BitILP32())
846     FrameReg = getX86SubSuperRegister(FrameReg, 32);
847   return FrameReg;
848 }
849 
850 unsigned
851 X86RegisterInfo::getPtrSizedStackRegister(const MachineFunction &MF) const {
852   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
853   Register StackReg = getStackRegister();
854   if (Subtarget.isTarget64BitILP32())
855     StackReg = getX86SubSuperRegister(StackReg, 32);
856   return StackReg;
857 }
858