1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 
41 using namespace llvm;
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
45 
46 static cl::opt<bool>
47 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
48           cl::desc("Enable use of a base pointer for complex stack frames"));
49 
50 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
51     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
52                          X86_MC::getDwarfRegFlavour(TT, false),
53                          X86_MC::getDwarfRegFlavour(TT, true),
54                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
55   X86_MC::initLLVMToSEHAndCVRegMapping(this);
56 
57   // Cache some information.
58   Is64Bit = TT.isArch64Bit();
59   IsWin64 = Is64Bit && TT.isOSWindows();
60 
61   // Use a callee-saved register as the base pointer.  These registers must
62   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
63   // requires GOT in the EBX register before function calls via PLT GOT pointer.
64   if (Is64Bit) {
65     SlotSize = 8;
66     // This matches the simplified 32-bit pointer code in the data layout
67     // computation.
68     // FIXME: Should use the data layout?
69     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
70     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
71     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
72     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
73   } else {
74     SlotSize = 4;
75     StackPtr = X86::ESP;
76     FramePtr = X86::EBP;
77     BasePtr = X86::ESI;
78   }
79 }
80 
81 bool
82 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
83   // ExeDepsFixer and PostRAScheduler require liveness.
84   return true;
85 }
86 
87 int
88 X86RegisterInfo::getSEHRegNum(unsigned i) const {
89   return getEncodingValue(i);
90 }
91 
92 const TargetRegisterClass *
93 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
94                                        unsigned Idx) const {
95   // The sub_8bit sub-register index is more constrained in 32-bit mode.
96   // It behaves just like the sub_8bit_hi index.
97   if (!Is64Bit && Idx == X86::sub_8bit)
98     Idx = X86::sub_8bit_hi;
99 
100   // Forward to TableGen's default version.
101   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
102 }
103 
104 const TargetRegisterClass *
105 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
106                                           const TargetRegisterClass *B,
107                                           unsigned SubIdx) const {
108   // The sub_8bit sub-register index is more constrained in 32-bit mode.
109   if (!Is64Bit && SubIdx == X86::sub_8bit) {
110     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
111     if (!A)
112       return nullptr;
113   }
114   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
115 }
116 
117 const TargetRegisterClass *
118 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
119                                            const MachineFunction &MF) const {
120   // Don't allow super-classes of GR8_NOREX.  This class is only used after
121   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
122   // to the full GR8 register class in 64-bit mode, so we cannot allow the
123   // reigster class inflation.
124   //
125   // The GR8_NOREX class is always used in a way that won't be constrained to a
126   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
127   // full GR8 class.
128   if (RC == &X86::GR8_NOREXRegClass)
129     return RC;
130 
131   const TargetRegisterClass *Super = RC;
132   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
133   do {
134     switch (Super->getID()) {
135     case X86::GR8RegClassID:
136     case X86::GR16RegClassID:
137     case X86::GR32RegClassID:
138     case X86::GR64RegClassID:
139     case X86::FR32RegClassID:
140     case X86::FR64RegClassID:
141     case X86::RFP32RegClassID:
142     case X86::RFP64RegClassID:
143     case X86::RFP80RegClassID:
144     case X86::VR128RegClassID:
145     case X86::VR256RegClassID:
146       // Don't return a super-class that would shrink the spill size.
147       // That can happen with the vector and float classes.
148       if (Super->getSize() == RC->getSize())
149         return Super;
150     }
151     Super = *I++;
152   } while (Super);
153   return RC;
154 }
155 
156 const TargetRegisterClass *
157 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
158                                     unsigned Kind) const {
159   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
160   switch (Kind) {
161   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
162   case 0: // Normal GPRs.
163     if (Subtarget.isTarget64BitLP64())
164       return &X86::GR64RegClass;
165     return &X86::GR32RegClass;
166   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
167     if (Subtarget.isTarget64BitLP64())
168       return &X86::GR64_NOSPRegClass;
169     return &X86::GR32_NOSPRegClass;
170   case 2: // NOREX GPRs.
171     if (Subtarget.isTarget64BitLP64())
172       return &X86::GR64_NOREXRegClass;
173     return &X86::GR32_NOREXRegClass;
174   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
175     if (Subtarget.isTarget64BitLP64())
176       return &X86::GR64_NOREX_NOSPRegClass;
177     return &X86::GR32_NOREX_NOSPRegClass;
178   case 4: // Available for tailcall (not callee-saved GPRs).
179     return getGPRsForTailCall(MF);
180   }
181 }
182 
183 const TargetRegisterClass *
184 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
185   const Function *F = MF.getFunction();
186   if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
187     return &X86::GR64_TCW64RegClass;
188   else if (Is64Bit)
189     return &X86::GR64_TCRegClass;
190 
191   bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
192   if (hasHipeCC)
193     return &X86::GR32RegClass;
194   return &X86::GR32_TCRegClass;
195 }
196 
197 const TargetRegisterClass *
198 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
199   if (RC == &X86::CCRRegClass) {
200     if (Is64Bit)
201       return &X86::GR64RegClass;
202     else
203       return &X86::GR32RegClass;
204   }
205   return RC;
206 }
207 
208 unsigned
209 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
210                                      MachineFunction &MF) const {
211   const X86FrameLowering *TFI = getFrameLowering(MF);
212 
213   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
214   switch (RC->getID()) {
215   default:
216     return 0;
217   case X86::GR32RegClassID:
218     return 4 - FPDiff;
219   case X86::GR64RegClassID:
220     return 12 - FPDiff;
221   case X86::VR128RegClassID:
222     return Is64Bit ? 10 : 4;
223   case X86::VR64RegClassID:
224     return 4;
225   }
226 }
227 
228 const MCPhysReg *
229 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
230   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
231   bool HasSSE = Subtarget.hasSSE1();
232   bool HasAVX = Subtarget.hasAVX();
233   bool HasAVX512 = Subtarget.hasAVX512();
234   bool CallsEHReturn = MF->getMMI().callsEHReturn();
235 
236   assert(MF && "MachineFunction required");
237   switch (MF->getFunction()->getCallingConv()) {
238   case CallingConv::GHC:
239   case CallingConv::HiPE:
240     return CSR_NoRegs_SaveList;
241   case CallingConv::AnyReg:
242     if (HasAVX)
243       return CSR_64_AllRegs_AVX_SaveList;
244     return CSR_64_AllRegs_SaveList;
245   case CallingConv::PreserveMost:
246     return CSR_64_RT_MostRegs_SaveList;
247   case CallingConv::PreserveAll:
248     if (HasAVX)
249       return CSR_64_RT_AllRegs_AVX_SaveList;
250     return CSR_64_RT_AllRegs_SaveList;
251   case CallingConv::CXX_FAST_TLS:
252     if (Is64Bit)
253       return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
254              CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
255     break;
256   case CallingConv::Intel_OCL_BI: {
257     if (HasAVX512 && IsWin64)
258       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
259     if (HasAVX512 && Is64Bit)
260       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
261     if (HasAVX && IsWin64)
262       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
263     if (HasAVX && Is64Bit)
264       return CSR_64_Intel_OCL_BI_AVX_SaveList;
265     if (!HasAVX && !IsWin64 && Is64Bit)
266       return CSR_64_Intel_OCL_BI_SaveList;
267     break;
268   }
269   case CallingConv::HHVM:
270     return CSR_64_HHVM_SaveList;
271   case CallingConv::Cold:
272     if (Is64Bit)
273       return CSR_64_MostRegs_SaveList;
274     break;
275   case CallingConv::X86_64_Win64:
276     return CSR_Win64_SaveList;
277   case CallingConv::X86_64_SysV:
278     if (CallsEHReturn)
279       return CSR_64EHRet_SaveList;
280     return CSR_64_SaveList;
281   case CallingConv::X86_INTR:
282     if (Is64Bit) {
283       if (HasAVX)
284         return CSR_64_AllRegs_AVX_SaveList;
285       else
286         return CSR_64_AllRegs_SaveList;
287     } else {
288       if (HasSSE)
289         return CSR_32_AllRegs_SSE_SaveList;
290       else
291         return CSR_32_AllRegs_SaveList;
292     }
293   default:
294     break;
295   }
296 
297   if (Is64Bit) {
298     if (IsWin64)
299       return CSR_Win64_SaveList;
300     if (CallsEHReturn)
301       return CSR_64EHRet_SaveList;
302     if (Subtarget.getTargetLowering()->supportSwiftError() &&
303         MF->getFunction()->getAttributes().hasAttrSomewhere(
304             Attribute::SwiftError))
305       return CSR_64_SwiftError_SaveList;
306     return CSR_64_SaveList;
307   }
308   if (CallsEHReturn)
309     return CSR_32EHRet_SaveList;
310   return CSR_32_SaveList;
311 }
312 
313 const MCPhysReg *X86RegisterInfo::getCalleeSavedRegsViaCopy(
314     const MachineFunction *MF) const {
315   assert(MF && "Invalid MachineFunction pointer.");
316   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
317       MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
318     return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
319   return nullptr;
320 }
321 
322 const uint32_t *
323 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
324                                       CallingConv::ID CC) const {
325   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
326   bool HasSSE = Subtarget.hasSSE1();
327   bool HasAVX = Subtarget.hasAVX();
328   bool HasAVX512 = Subtarget.hasAVX512();
329 
330   switch (CC) {
331   case CallingConv::GHC:
332   case CallingConv::HiPE:
333     return CSR_NoRegs_RegMask;
334   case CallingConv::AnyReg:
335     if (HasAVX)
336       return CSR_64_AllRegs_AVX_RegMask;
337     return CSR_64_AllRegs_RegMask;
338   case CallingConv::PreserveMost:
339     return CSR_64_RT_MostRegs_RegMask;
340   case CallingConv::PreserveAll:
341     if (HasAVX)
342       return CSR_64_RT_AllRegs_AVX_RegMask;
343     return CSR_64_RT_AllRegs_RegMask;
344   case CallingConv::CXX_FAST_TLS:
345     if (Is64Bit)
346       return CSR_64_TLS_Darwin_RegMask;
347     break;
348   case CallingConv::Intel_OCL_BI: {
349     if (HasAVX512 && IsWin64)
350       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
351     if (HasAVX512 && Is64Bit)
352       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
353     if (HasAVX && IsWin64)
354       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
355     if (HasAVX && Is64Bit)
356       return CSR_64_Intel_OCL_BI_AVX_RegMask;
357     if (!HasAVX && !IsWin64 && Is64Bit)
358       return CSR_64_Intel_OCL_BI_RegMask;
359     break;
360   }
361   case CallingConv::HHVM:
362     return CSR_64_HHVM_RegMask;
363   case CallingConv::Cold:
364     if (Is64Bit)
365       return CSR_64_MostRegs_RegMask;
366     break;
367   case CallingConv::X86_64_Win64:
368     return CSR_Win64_RegMask;
369   case CallingConv::X86_64_SysV:
370     return CSR_64_RegMask;
371   case CallingConv::X86_INTR:
372     if (Is64Bit) {
373       if (HasAVX)
374         return CSR_64_AllRegs_AVX_RegMask;
375       else
376         return CSR_64_AllRegs_RegMask;
377     } else {
378       if (HasSSE)
379         return CSR_32_AllRegs_SSE_RegMask;
380       else
381         return CSR_32_AllRegs_RegMask;
382     }
383     default:
384       break;
385   }
386 
387   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
388   // callsEHReturn().
389   if (Is64Bit) {
390     if (IsWin64)
391       return CSR_Win64_RegMask;
392     if (Subtarget.getTargetLowering()->supportSwiftError() &&
393         MF.getFunction()->getAttributes().hasAttrSomewhere(
394             Attribute::SwiftError))
395       return CSR_64_SwiftError_RegMask;
396     return CSR_64_RegMask;
397   }
398   return CSR_32_RegMask;
399 }
400 
401 const uint32_t*
402 X86RegisterInfo::getNoPreservedMask() const {
403   return CSR_NoRegs_RegMask;
404 }
405 
406 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
407   return CSR_64_TLS_Darwin_RegMask;
408 }
409 
410 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
411   BitVector Reserved(getNumRegs());
412   const X86FrameLowering *TFI = getFrameLowering(MF);
413 
414   // Set the stack-pointer register and its aliases as reserved.
415   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
416        ++I)
417     Reserved.set(*I);
418 
419   // Set the instruction pointer register and its aliases as reserved.
420   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
421        ++I)
422     Reserved.set(*I);
423 
424   // Set the frame-pointer register and its aliases as reserved if needed.
425   if (TFI->hasFP(MF)) {
426     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
427          ++I)
428       Reserved.set(*I);
429   }
430 
431   // Set the base-pointer register and its aliases as reserved if needed.
432   if (hasBasePointer(MF)) {
433     CallingConv::ID CC = MF.getFunction()->getCallingConv();
434     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
435     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
436       report_fatal_error(
437         "Stack realignment in presence of dynamic allocas is not supported with"
438         "this calling convention.");
439 
440     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
441     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
442          I.isValid(); ++I)
443       Reserved.set(*I);
444   }
445 
446   // Mark the segment registers as reserved.
447   Reserved.set(X86::CS);
448   Reserved.set(X86::SS);
449   Reserved.set(X86::DS);
450   Reserved.set(X86::ES);
451   Reserved.set(X86::FS);
452   Reserved.set(X86::GS);
453 
454   // Mark the floating point stack registers as reserved.
455   for (unsigned n = 0; n != 8; ++n)
456     Reserved.set(X86::ST0 + n);
457 
458   // Reserve the registers that only exist in 64-bit mode.
459   if (!Is64Bit) {
460     // These 8-bit registers are part of the x86-64 extension even though their
461     // super-registers are old 32-bits.
462     Reserved.set(X86::SIL);
463     Reserved.set(X86::DIL);
464     Reserved.set(X86::BPL);
465     Reserved.set(X86::SPL);
466 
467     for (unsigned n = 0; n != 8; ++n) {
468       // R8, R9, ...
469       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
470         Reserved.set(*AI);
471 
472       // XMM8, XMM9, ...
473       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
474         Reserved.set(*AI);
475     }
476   }
477   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
478     for (unsigned n = 16; n != 32; ++n) {
479       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
480         Reserved.set(*AI);
481     }
482   }
483 
484   return Reserved;
485 }
486 
487 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
488   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
489   // because the calling convention defines the EFLAGS register as NOT
490   // preserved.
491   //
492   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
493   // an assert to track this and clear the register afterwards to avoid
494   // unnecessary crashes during release builds.
495   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
496          "EFLAGS are not live-out from a patchpoint.");
497 
498   // Also clean other registers that don't need preserving (IP).
499   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
500     Mask[Reg / 32] &= ~(1U << (Reg % 32));
501 }
502 
503 //===----------------------------------------------------------------------===//
504 // Stack Frame Processing methods
505 //===----------------------------------------------------------------------===//
506 
507 static bool CantUseSP(const MachineFrameInfo *MFI) {
508   return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
509 }
510 
511 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
512    const MachineFrameInfo *MFI = MF.getFrameInfo();
513 
514    if (!EnableBasePointer)
515      return false;
516 
517    // When we need stack realignment, we can't address the stack from the frame
518    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
519    // can't address variables from the stack pointer.  MS inline asm can
520    // reference locals while also adjusting the stack pointer.  When we can't
521    // use both the SP and the FP, we need a separate base pointer register.
522    bool CantUseFP = needsStackRealignment(MF);
523    return CantUseFP && CantUseSP(MFI);
524 }
525 
526 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
527   if (!TargetRegisterInfo::canRealignStack(MF))
528     return false;
529 
530   const MachineFrameInfo *MFI = MF.getFrameInfo();
531   const MachineRegisterInfo *MRI = &MF.getRegInfo();
532 
533   // Stack realignment requires a frame pointer.  If we already started
534   // register allocation with frame pointer elimination, it is too late now.
535   if (!MRI->canReserveReg(FramePtr))
536     return false;
537 
538   // If a base pointer is necessary.  Check that it isn't too late to reserve
539   // it.
540   if (CantUseSP(MFI))
541     return MRI->canReserveReg(BasePtr);
542   return true;
543 }
544 
545 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
546                                            unsigned Reg, int &FrameIdx) const {
547   // Since X86 defines assignCalleeSavedSpillSlots which always return true
548   // this function neither used nor tested.
549   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
550 }
551 
552 void
553 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
554                                      int SPAdj, unsigned FIOperandNum,
555                                      RegScavenger *RS) const {
556   MachineInstr &MI = *II;
557   MachineFunction &MF = *MI.getParent()->getParent();
558   const X86FrameLowering *TFI = getFrameLowering(MF);
559   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
560   unsigned BasePtr;
561 
562   unsigned Opc = MI.getOpcode();
563   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
564                     Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
565 
566   if (hasBasePointer(MF))
567     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
568   else if (needsStackRealignment(MF))
569     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
570   else if (AfterFPPop)
571     BasePtr = StackPtr;
572   else
573     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
574 
575   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
576   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
577   // offset is from the traditional base pointer location.  On 64-bit, the
578   // offset is from the SP at the end of the prologue, not the FP location. This
579   // matches the behavior of llvm.frameaddress.
580   unsigned IgnoredFrameReg;
581   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
582     MachineOperand &FI = MI.getOperand(FIOperandNum);
583     int Offset;
584     Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
585     FI.ChangeToImmediate(Offset);
586     return;
587   }
588 
589   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
590   // register as source operand, semantic is the same and destination is
591   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
592   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
593     BasePtr = getX86SubSuperRegister(BasePtr, 64);
594 
595   // This must be part of a four operand memory reference.  Replace the
596   // FrameIndex with base register with EBP.  Add an offset to the offset.
597   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
598 
599   // Now add the frame object offset to the offset from EBP.
600   int FIOffset;
601   if (AfterFPPop) {
602     // Tail call jmp happens after FP is popped.
603     const MachineFrameInfo *MFI = MF.getFrameInfo();
604     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
605   } else
606     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
607 
608   if (BasePtr == StackPtr)
609     FIOffset += SPAdj;
610 
611   // The frame index format for stackmaps and patchpoints is different from the
612   // X86 format. It only has a FI and an offset.
613   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
614     assert(BasePtr == FramePtr && "Expected the FP as base register");
615     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
616     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
617     return;
618   }
619 
620   if (MI.getOperand(FIOperandNum+3).isImm()) {
621     // Offset is a 32-bit integer.
622     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
623     int Offset = FIOffset + Imm;
624     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
625            "Requesting 64-bit offset in 32-bit immediate!");
626     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
627   } else {
628     // Offset is symbolic. This is extremely rare.
629     uint64_t Offset = FIOffset +
630       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
631     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
632   }
633 }
634 
635 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
636   const X86FrameLowering *TFI = getFrameLowering(MF);
637   return TFI->hasFP(MF) ? FramePtr : StackPtr;
638 }
639 
640 unsigned
641 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
642   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
643   unsigned FrameReg = getFrameRegister(MF);
644   if (Subtarget.isTarget64BitILP32())
645     FrameReg = getX86SubSuperRegister(FrameReg, 32);
646   return FrameReg;
647 }
648 
649 unsigned llvm::get512BitSuperRegister(unsigned Reg) {
650   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
651     return X86::ZMM0 + (Reg - X86::XMM0);
652   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
653     return X86::ZMM0 + (Reg - X86::YMM0);
654   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
655     return Reg;
656   llvm_unreachable("Unexpected SIMD register");
657 }
658