1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/ValueTypes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
44 
45 using namespace llvm;
46 
47 cl::opt<bool>
48 ForceStackAlign("force-align-stack",
49                  cl::desc("Force align the stack to the minimum alignment"
50                            " needed for the function."),
51                  cl::init(false), cl::Hidden);
52 
53 static cl::opt<bool>
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55           cl::desc("Enable use of a base pointer for complex stack frames"));
56 
57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
58   : X86GenRegisterInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
59                          ? X86::RIP : X86::EIP),
60                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
61                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
62                        (tm.getSubtarget<X86Subtarget>().is64Bit()
63                          ? X86::RIP : X86::EIP)),
64                        TM(tm) {
65   X86_MC::InitLLVM2SEHRegisterMapping(this);
66 
67   // Cache some information.
68   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
69   Is64Bit = Subtarget->is64Bit();
70   IsWin64 = Subtarget->isTargetWin64();
71 
72   if (Is64Bit) {
73     SlotSize = 8;
74     StackPtr = X86::RSP;
75     FramePtr = X86::RBP;
76   } else {
77     SlotSize = 4;
78     StackPtr = X86::ESP;
79     FramePtr = X86::EBP;
80   }
81   // Use a callee-saved register as the base pointer.  These registers must
82   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
83   // requires GOT in the EBX register before function calls via PLT GOT pointer.
84   BasePtr = Is64Bit ? X86::RBX : X86::ESI;
85 }
86 
87 /// getCompactUnwindRegNum - This function maps the register to the number for
88 /// compact unwind encoding. Return -1 if the register isn't valid.
89 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
90   switch (getLLVMRegNum(RegNum, isEH)) {
91   case X86::EBX: case X86::RBX: return 1;
92   case X86::ECX: case X86::R12: return 2;
93   case X86::EDX: case X86::R13: return 3;
94   case X86::EDI: case X86::R14: return 4;
95   case X86::ESI: case X86::R15: return 5;
96   case X86::EBP: case X86::RBP: return 6;
97   }
98 
99   return -1;
100 }
101 
102 bool
103 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
104   // ExeDepsFixer and PostRAScheduler require liveness.
105   return true;
106 }
107 
108 int
109 X86RegisterInfo::getSEHRegNum(unsigned i) const {
110   return getEncodingValue(i);
111 }
112 
113 const TargetRegisterClass *
114 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
115                                        unsigned Idx) const {
116   // The sub_8bit sub-register index is more constrained in 32-bit mode.
117   // It behaves just like the sub_8bit_hi index.
118   if (!Is64Bit && Idx == X86::sub_8bit)
119     Idx = X86::sub_8bit_hi;
120 
121   // Forward to TableGen's default version.
122   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
123 }
124 
125 const TargetRegisterClass *
126 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
127                                           const TargetRegisterClass *B,
128                                           unsigned SubIdx) const {
129   // The sub_8bit sub-register index is more constrained in 32-bit mode.
130   if (!Is64Bit && SubIdx == X86::sub_8bit) {
131     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
132     if (!A)
133       return 0;
134   }
135   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
136 }
137 
138 const TargetRegisterClass*
139 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
140   // Don't allow super-classes of GR8_NOREX.  This class is only used after
141   // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
142   // to the full GR8 register class in 64-bit mode, so we cannot allow the
143   // reigster class inflation.
144   //
145   // The GR8_NOREX class is always used in a way that won't be constrained to a
146   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
147   // full GR8 class.
148   if (RC == &X86::GR8_NOREXRegClass)
149     return RC;
150 
151   const TargetRegisterClass *Super = RC;
152   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
153   do {
154     switch (Super->getID()) {
155     case X86::GR8RegClassID:
156     case X86::GR16RegClassID:
157     case X86::GR32RegClassID:
158     case X86::GR64RegClassID:
159     case X86::FR32RegClassID:
160     case X86::FR64RegClassID:
161     case X86::RFP32RegClassID:
162     case X86::RFP64RegClassID:
163     case X86::RFP80RegClassID:
164     case X86::VR128RegClassID:
165     case X86::VR256RegClassID:
166       // Don't return a super-class that would shrink the spill size.
167       // That can happen with the vector and float classes.
168       if (Super->getSize() == RC->getSize())
169         return Super;
170     }
171     Super = *I++;
172   } while (Super);
173   return RC;
174 }
175 
176 const TargetRegisterClass *
177 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
178                                                                          const {
179   const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
180   switch (Kind) {
181   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
182   case 0: // Normal GPRs.
183     if (Subtarget.isTarget64BitLP64())
184       return &X86::GR64RegClass;
185     return &X86::GR32RegClass;
186   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
187     if (Subtarget.isTarget64BitLP64())
188       return &X86::GR64_NOSPRegClass;
189     return &X86::GR32_NOSPRegClass;
190   case 2: // Available for tailcall (not callee-saved GPRs).
191     if (Subtarget.isTargetWin64())
192       return &X86::GR64_TCW64RegClass;
193     else if (Subtarget.is64Bit())
194       return &X86::GR64_TCRegClass;
195 
196     const Function *F = MF.getFunction();
197     bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
198     if (hasHipeCC)
199       return &X86::GR32RegClass;
200     return &X86::GR32_TCRegClass;
201   }
202 }
203 
204 const TargetRegisterClass *
205 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
206   if (RC == &X86::CCRRegClass) {
207     if (Is64Bit)
208       return &X86::GR64RegClass;
209     else
210       return &X86::GR32RegClass;
211   }
212   return RC;
213 }
214 
215 unsigned
216 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
217                                      MachineFunction &MF) const {
218   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
219 
220   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
221   switch (RC->getID()) {
222   default:
223     return 0;
224   case X86::GR32RegClassID:
225     return 4 - FPDiff;
226   case X86::GR64RegClassID:
227     return 12 - FPDiff;
228   case X86::VR128RegClassID:
229     return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
230   case X86::VR64RegClassID:
231     return 4;
232   }
233 }
234 
235 const uint16_t *
236 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
237   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
238   bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
239 
240   switch (MF->getFunction()->getCallingConv()) {
241   case CallingConv::GHC:
242   case CallingConv::HiPE:
243     return CSR_NoRegs_SaveList;
244   case CallingConv::AnyReg:
245     if (HasAVX)
246       return CSR_64_AllRegs_AVX_SaveList;
247     return CSR_64_AllRegs_SaveList;
248   case CallingConv::PreserveMost:
249     return CSR_64_RT_MostRegs_SaveList;
250   case CallingConv::PreserveAll:
251     if (HasAVX)
252       return CSR_64_RT_AllRegs_AVX_SaveList;
253     return CSR_64_RT_AllRegs_SaveList;
254   case CallingConv::Intel_OCL_BI: {
255     if (HasAVX512 && IsWin64)
256       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
257     if (HasAVX512 && Is64Bit)
258       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
259     if (HasAVX && IsWin64)
260       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
261     if (HasAVX && Is64Bit)
262       return CSR_64_Intel_OCL_BI_AVX_SaveList;
263     if (!HasAVX && !IsWin64 && Is64Bit)
264       return CSR_64_Intel_OCL_BI_SaveList;
265     break;
266   }
267   case CallingConv::Cold:
268     if (Is64Bit)
269       return CSR_64_MostRegs_SaveList;
270     break;
271   default:
272     break;
273   }
274 
275   bool CallsEHReturn = MF->getMMI().callsEHReturn();
276   if (Is64Bit) {
277     if (IsWin64)
278       return CSR_Win64_SaveList;
279     if (CallsEHReturn)
280       return CSR_64EHRet_SaveList;
281     return CSR_64_SaveList;
282   }
283   if (CallsEHReturn)
284     return CSR_32EHRet_SaveList;
285   return CSR_32_SaveList;
286 }
287 
288 const uint32_t*
289 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
290   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
291   bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
292 
293   switch (CC) {
294   case CallingConv::GHC:
295   case CallingConv::HiPE:
296     return CSR_NoRegs_RegMask;
297   case CallingConv::AnyReg:
298     if (HasAVX)
299       return CSR_64_AllRegs_AVX_RegMask;
300     return CSR_64_AllRegs_RegMask;
301   case CallingConv::PreserveMost:
302     return CSR_64_RT_MostRegs_RegMask;
303   case CallingConv::PreserveAll:
304     if (HasAVX)
305       return CSR_64_RT_AllRegs_AVX_RegMask;
306     return CSR_64_RT_AllRegs_RegMask;
307   case CallingConv::Intel_OCL_BI: {
308     if (IsWin64 && HasAVX512)
309       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
310     if (Is64Bit && HasAVX512)
311       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
312     if (IsWin64 && HasAVX)
313       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
314     if (Is64Bit && HasAVX)
315       return CSR_64_Intel_OCL_BI_AVX_RegMask;
316     if (!HasAVX && !IsWin64 && Is64Bit)
317       return CSR_64_Intel_OCL_BI_RegMask;
318   }
319   case CallingConv::Cold:
320     if (Is64Bit)
321       return CSR_64_MostRegs_RegMask;
322     break;
323   default:
324     break;
325   }
326 
327   if (Is64Bit) {
328     if (IsWin64)
329       return CSR_Win64_RegMask;
330     return CSR_64_RegMask;
331   }
332   return CSR_32_RegMask;
333 }
334 
335 const uint32_t*
336 X86RegisterInfo::getNoPreservedMask() const {
337   return CSR_NoRegs_RegMask;
338 }
339 
340 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
341   BitVector Reserved(getNumRegs());
342   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
343 
344   // Set the stack-pointer register and its aliases as reserved.
345   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
346        ++I)
347     Reserved.set(*I);
348 
349   // Set the instruction pointer register and its aliases as reserved.
350   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
351        ++I)
352     Reserved.set(*I);
353 
354   // Set the frame-pointer register and its aliases as reserved if needed.
355   if (TFI->hasFP(MF)) {
356     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
357          ++I)
358       Reserved.set(*I);
359   }
360 
361   // Set the base-pointer register and its aliases as reserved if needed.
362   if (hasBasePointer(MF)) {
363     CallingConv::ID CC = MF.getFunction()->getCallingConv();
364     const uint32_t* RegMask = getCallPreservedMask(CC);
365     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
366       report_fatal_error(
367         "Stack realignment in presence of dynamic allocas is not supported with"
368         "this calling convention.");
369 
370     for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
371          I.isValid(); ++I)
372       Reserved.set(*I);
373   }
374 
375   // Mark the segment registers as reserved.
376   Reserved.set(X86::CS);
377   Reserved.set(X86::SS);
378   Reserved.set(X86::DS);
379   Reserved.set(X86::ES);
380   Reserved.set(X86::FS);
381   Reserved.set(X86::GS);
382 
383   // Mark the floating point stack registers as reserved.
384   for (unsigned n = 0; n != 8; ++n)
385     Reserved.set(X86::ST0 + n);
386 
387   // Reserve the registers that only exist in 64-bit mode.
388   if (!Is64Bit) {
389     // These 8-bit registers are part of the x86-64 extension even though their
390     // super-registers are old 32-bits.
391     Reserved.set(X86::SIL);
392     Reserved.set(X86::DIL);
393     Reserved.set(X86::BPL);
394     Reserved.set(X86::SPL);
395 
396     for (unsigned n = 0; n != 8; ++n) {
397       // R8, R9, ...
398       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
399         Reserved.set(*AI);
400 
401       // XMM8, XMM9, ...
402       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
403         Reserved.set(*AI);
404     }
405   }
406   if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
407     for (unsigned n = 16; n != 32; ++n) {
408       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
409         Reserved.set(*AI);
410     }
411   }
412 
413   return Reserved;
414 }
415 
416 //===----------------------------------------------------------------------===//
417 // Stack Frame Processing methods
418 //===----------------------------------------------------------------------===//
419 
420 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
421    const MachineFrameInfo *MFI = MF.getFrameInfo();
422 
423    if (!EnableBasePointer)
424      return false;
425 
426    // When we need stack realignment, we can't address the stack from the frame
427    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
428    // can't address variables from the stack pointer.  MS inline asm can
429    // reference locals while also adjusting the stack pointer.  When we can't
430    // use both the SP and the FP, we need a separate base pointer register.
431    bool CantUseFP = needsStackRealignment(MF);
432    bool CantUseSP =
433        MFI->hasVarSizedObjects() || MFI->hasInlineAsmWithSPAdjust();
434    return CantUseFP && CantUseSP;
435 }
436 
437 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
438   if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
439     return false;
440 
441   const MachineFrameInfo *MFI = MF.getFrameInfo();
442   const MachineRegisterInfo *MRI = &MF.getRegInfo();
443 
444   // Stack realignment requires a frame pointer.  If we already started
445   // register allocation with frame pointer elimination, it is too late now.
446   if (!MRI->canReserveReg(FramePtr))
447     return false;
448 
449   // If a base pointer is necessary.  Check that it isn't too late to reserve
450   // it.
451   if (MFI->hasVarSizedObjects())
452     return MRI->canReserveReg(BasePtr);
453   return true;
454 }
455 
456 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
457   const MachineFrameInfo *MFI = MF.getFrameInfo();
458   const Function *F = MF.getFunction();
459   unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
460   bool requiresRealignment =
461     ((MFI->getMaxAlignment() > StackAlign) ||
462      F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
463                                      Attribute::StackAlignment));
464 
465   // If we've requested that we force align the stack do so now.
466   if (ForceStackAlign)
467     return canRealignStack(MF);
468 
469   return requiresRealignment && canRealignStack(MF);
470 }
471 
472 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
473                                            unsigned Reg, int &FrameIdx) const {
474   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
475 
476   if (Reg == FramePtr && TFI->hasFP(MF)) {
477     FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
478     return true;
479   }
480   return false;
481 }
482 
483 void
484 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
485                                      int SPAdj, unsigned FIOperandNum,
486                                      RegScavenger *RS) const {
487   assert(SPAdj == 0 && "Unexpected");
488 
489   MachineInstr &MI = *II;
490   MachineFunction &MF = *MI.getParent()->getParent();
491   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
492   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
493   unsigned BasePtr;
494 
495   unsigned Opc = MI.getOpcode();
496   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
497   if (hasBasePointer(MF))
498     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
499   else if (needsStackRealignment(MF))
500     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
501   else if (AfterFPPop)
502     BasePtr = StackPtr;
503   else
504     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
505 
506   // This must be part of a four operand memory reference.  Replace the
507   // FrameIndex with base register with EBP.  Add an offset to the offset.
508   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
509 
510   // Now add the frame object offset to the offset from EBP.
511   int FIOffset;
512   if (AfterFPPop) {
513     // Tail call jmp happens after FP is popped.
514     const MachineFrameInfo *MFI = MF.getFrameInfo();
515     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
516   } else
517     FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
518 
519   if (MI.getOperand(FIOperandNum+3).isImm()) {
520     // Offset is a 32-bit integer.
521     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
522     int Offset = FIOffset + Imm;
523     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
524            "Requesting 64-bit offset in 32-bit immediate!");
525     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
526   } else {
527     // Offset is symbolic. This is extremely rare.
528     uint64_t Offset = FIOffset +
529       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
530     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
531   }
532 }
533 
534 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
535   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
536   return TFI->hasFP(MF) ? FramePtr : StackPtr;
537 }
538 
539 namespace llvm {
540 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
541                                 bool High) {
542   switch (VT) {
543   default: llvm_unreachable("Unexpected VT");
544   case MVT::i8:
545     if (High) {
546       switch (Reg) {
547       default: return getX86SubSuperRegister(Reg, MVT::i64);
548       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
549         return X86::SI;
550       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
551         return X86::DI;
552       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
553         return X86::BP;
554       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
555         return X86::SP;
556       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
557         return X86::AH;
558       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
559         return X86::DH;
560       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
561         return X86::CH;
562       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
563         return X86::BH;
564       }
565     } else {
566       switch (Reg) {
567       default: llvm_unreachable("Unexpected register");
568       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
569         return X86::AL;
570       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
571         return X86::DL;
572       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
573         return X86::CL;
574       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
575         return X86::BL;
576       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
577         return X86::SIL;
578       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
579         return X86::DIL;
580       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
581         return X86::BPL;
582       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
583         return X86::SPL;
584       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
585         return X86::R8B;
586       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
587         return X86::R9B;
588       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
589         return X86::R10B;
590       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
591         return X86::R11B;
592       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
593         return X86::R12B;
594       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
595         return X86::R13B;
596       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
597         return X86::R14B;
598       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
599         return X86::R15B;
600       }
601     }
602   case MVT::i16:
603     switch (Reg) {
604     default: llvm_unreachable("Unexpected register");
605     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
606       return X86::AX;
607     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
608       return X86::DX;
609     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
610       return X86::CX;
611     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
612       return X86::BX;
613     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
614       return X86::SI;
615     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
616       return X86::DI;
617     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
618       return X86::BP;
619     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
620       return X86::SP;
621     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
622       return X86::R8W;
623     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
624       return X86::R9W;
625     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
626       return X86::R10W;
627     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
628       return X86::R11W;
629     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
630       return X86::R12W;
631     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
632       return X86::R13W;
633     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
634       return X86::R14W;
635     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
636       return X86::R15W;
637     }
638   case MVT::i32:
639     switch (Reg) {
640     default: llvm_unreachable("Unexpected register");
641     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
642       return X86::EAX;
643     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
644       return X86::EDX;
645     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
646       return X86::ECX;
647     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
648       return X86::EBX;
649     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
650       return X86::ESI;
651     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
652       return X86::EDI;
653     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
654       return X86::EBP;
655     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
656       return X86::ESP;
657     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
658       return X86::R8D;
659     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
660       return X86::R9D;
661     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
662       return X86::R10D;
663     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
664       return X86::R11D;
665     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
666       return X86::R12D;
667     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
668       return X86::R13D;
669     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
670       return X86::R14D;
671     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
672       return X86::R15D;
673     }
674   case MVT::i64:
675     switch (Reg) {
676     default: llvm_unreachable("Unexpected register");
677     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
678       return X86::RAX;
679     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
680       return X86::RDX;
681     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
682       return X86::RCX;
683     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
684       return X86::RBX;
685     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
686       return X86::RSI;
687     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
688       return X86::RDI;
689     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
690       return X86::RBP;
691     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
692       return X86::RSP;
693     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
694       return X86::R8;
695     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
696       return X86::R9;
697     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
698       return X86::R10;
699     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
700       return X86::R11;
701     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
702       return X86::R12;
703     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
704       return X86::R13;
705     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
706       return X86::R14;
707     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
708       return X86::R15;
709     }
710   }
711 }
712 
713 unsigned get512BitSuperRegister(unsigned Reg) {
714   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
715     return X86::ZMM0 + (Reg - X86::XMM0);
716   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
717     return X86::ZMM0 + (Reg - X86::YMM0);
718   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
719     return Reg;
720   llvm_unreachable("Unexpected SIMD register");
721 }
722 
723 }
724