1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86.h"
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
41 using namespace llvm;
42 
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44                                  const TargetInstrInfo &tii)
45   : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46                          X86::ADJCALLSTACKDOWN64 :
47                          X86::ADJCALLSTACKDOWN32,
48                        tm.getSubtarget<X86Subtarget>().is64Bit() ?
49                          X86::ADJCALLSTACKUP64 :
50                          X86::ADJCALLSTACKUP32),
51     TM(tm), TII(tii) {
52   // Cache some information.
53   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54   Is64Bit = Subtarget->is64Bit();
55   IsWin64 = Subtarget->isTargetWin64();
56   StackAlign = TM.getFrameInfo()->getStackAlignment();
57   if (Is64Bit) {
58     SlotSize = 8;
59     StackPtr = X86::RSP;
60     FramePtr = X86::RBP;
61   } else {
62     SlotSize = 4;
63     StackPtr = X86::ESP;
64     FramePtr = X86::EBP;
65   }
66 }
67 
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
70 
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73   unsigned Flavour = DWARFFlavour::X86_64;
74   if (!Subtarget->is64Bit()) {
75     if (Subtarget->isTargetDarwin()) {
76       if (isEH)
77         Flavour = DWARFFlavour::X86_32_DarwinEH;
78       else
79         Flavour = DWARFFlavour::X86_32_Generic;
80     } else if (Subtarget->isTargetCygMing()) {
81       // Unsupported by now, just quick fallback
82       Flavour = DWARFFlavour::X86_32_Generic;
83     } else {
84       Flavour = DWARFFlavour::X86_32_Generic;
85     }
86   }
87 
88   return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
89 }
90 
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
93 //
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
95   switch(RegNo) {
96   case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97   case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98   case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99   case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100   case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
101     return N86::ESP;
102   case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
103     return N86::EBP;
104   case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
105     return N86::ESI;
106   case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
107     return N86::EDI;
108 
109   case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
110     return N86::EAX;
111   case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
112     return N86::ECX;
113   case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
114     return N86::EDX;
115   case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
116     return N86::EBX;
117   case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
118     return N86::ESP;
119   case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
120     return N86::EBP;
121   case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
122     return N86::ESI;
123   case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
124     return N86::EDI;
125 
126   case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127   case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128     return RegNo-X86::ST0;
129 
130   case X86::XMM0: case X86::XMM8: case X86::MM0:
131     return 0;
132   case X86::XMM1: case X86::XMM9: case X86::MM1:
133     return 1;
134   case X86::XMM2: case X86::XMM10: case X86::MM2:
135     return 2;
136   case X86::XMM3: case X86::XMM11: case X86::MM3:
137     return 3;
138   case X86::XMM4: case X86::XMM12: case X86::MM4:
139     return 4;
140   case X86::XMM5: case X86::XMM13: case X86::MM5:
141     return 5;
142   case X86::XMM6: case X86::XMM14: case X86::MM6:
143     return 6;
144   case X86::XMM7: case X86::XMM15: case X86::MM7:
145     return 7;
146 
147   default:
148     assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149     assert(0 && "Register allocator hasn't allocated reg correctly yet!");
150     return 0;
151   }
152 }
153 
154 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
155   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
156   if (Subtarget->is64Bit())
157     return &X86::GR64RegClass;
158   else
159     return &X86::GR32RegClass;
160 }
161 
162 const TargetRegisterClass *
163 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
164   if (RC == &X86::CCRRegClass) {
165     if (Is64Bit)
166       return &X86::GR64RegClass;
167     else
168       return &X86::GR32RegClass;
169   }
170   return NULL;
171 }
172 
173 const unsigned *
174 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
175   bool callsEHReturn = false;
176 
177   if (MF) {
178     const MachineFrameInfo *MFI = MF->getFrameInfo();
179     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
180     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
181   }
182 
183   static const unsigned CalleeSavedRegs32Bit[] = {
184     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
185   };
186 
187   static const unsigned CalleeSavedRegs32EHRet[] = {
188     X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
189   };
190 
191   static const unsigned CalleeSavedRegs64Bit[] = {
192     X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
193   };
194 
195   static const unsigned CalleeSavedRegs64EHRet[] = {
196     X86::RAX, X86::RDX, X86::RBX, X86::R12,
197     X86::R13, X86::R14, X86::R15, X86::RBP, 0
198   };
199 
200   static const unsigned CalleeSavedRegsWin64[] = {
201     X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
202     X86::R12,   X86::R13,   X86::R14,   X86::R15,
203     X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
204     X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
205     X86::XMM14, X86::XMM15, 0
206   };
207 
208   if (Is64Bit) {
209     if (IsWin64)
210       return CalleeSavedRegsWin64;
211     else
212       return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
213   } else {
214     return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
215   }
216 }
217 
218 const TargetRegisterClass* const*
219 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
220   bool callsEHReturn = false;
221 
222   if (MF) {
223     const MachineFrameInfo *MFI = MF->getFrameInfo();
224     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
226   }
227 
228   static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
229     &X86::GR32RegClass, &X86::GR32RegClass,
230     &X86::GR32RegClass, &X86::GR32RegClass,  0
231   };
232   static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
233     &X86::GR32RegClass, &X86::GR32RegClass,
234     &X86::GR32RegClass, &X86::GR32RegClass,
235     &X86::GR32RegClass, &X86::GR32RegClass,  0
236   };
237   static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
238     &X86::GR64RegClass, &X86::GR64RegClass,
239     &X86::GR64RegClass, &X86::GR64RegClass,
240     &X86::GR64RegClass, &X86::GR64RegClass, 0
241   };
242   static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
243     &X86::GR64RegClass, &X86::GR64RegClass,
244     &X86::GR64RegClass, &X86::GR64RegClass,
245     &X86::GR64RegClass, &X86::GR64RegClass,
246     &X86::GR64RegClass, &X86::GR64RegClass, 0
247   };
248   static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
249     &X86::GR64RegClass,  &X86::GR64RegClass,
250     &X86::GR64RegClass,  &X86::GR64RegClass,
251     &X86::GR64RegClass,  &X86::GR64RegClass,
252     &X86::GR64RegClass,  &X86::GR64RegClass,
253     &X86::VR128RegClass, &X86::VR128RegClass,
254     &X86::VR128RegClass, &X86::VR128RegClass,
255     &X86::VR128RegClass, &X86::VR128RegClass,
256     &X86::VR128RegClass, &X86::VR128RegClass,
257     &X86::VR128RegClass, &X86::VR128RegClass, 0
258   };
259 
260   if (Is64Bit) {
261     if (IsWin64)
262       return CalleeSavedRegClassesWin64;
263     else
264       return (callsEHReturn ?
265               CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
266   } else {
267     return (callsEHReturn ?
268             CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
269   }
270 }
271 
272 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
273   BitVector Reserved(getNumRegs());
274   // Set the stack-pointer register and its aliases as reserved.
275   Reserved.set(X86::RSP);
276   Reserved.set(X86::ESP);
277   Reserved.set(X86::SP);
278   Reserved.set(X86::SPL);
279   // Set the frame-pointer register and its aliases as reserved if needed.
280   if (hasFP(MF)) {
281     Reserved.set(X86::RBP);
282     Reserved.set(X86::EBP);
283     Reserved.set(X86::BP);
284     Reserved.set(X86::BPL);
285   }
286   // Mark the x87 stack registers as reserved, since they don't
287   // behave normally with respect to liveness. We don't fully
288   // model the effects of x87 stack pushes and pops after
289   // stackification.
290   Reserved.set(X86::ST0);
291   Reserved.set(X86::ST1);
292   Reserved.set(X86::ST2);
293   Reserved.set(X86::ST3);
294   Reserved.set(X86::ST4);
295   Reserved.set(X86::ST5);
296   Reserved.set(X86::ST6);
297   Reserved.set(X86::ST7);
298   return Reserved;
299 }
300 
301 //===----------------------------------------------------------------------===//
302 // Stack Frame Processing methods
303 //===----------------------------------------------------------------------===//
304 
305 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
306   unsigned MaxAlign = 0;
307   for (int i = FFI->getObjectIndexBegin(),
308          e = FFI->getObjectIndexEnd(); i != e; ++i) {
309     if (FFI->isDeadObjectIndex(i))
310       continue;
311     unsigned Align = FFI->getObjectAlignment(i);
312     MaxAlign = std::max(MaxAlign, Align);
313   }
314 
315   return MaxAlign;
316 }
317 
318 // hasFP - Return true if the specified function should have a dedicated frame
319 // pointer register.  This is true if the function has variable sized allocas or
320 // if frame pointer elimination is disabled.
321 //
322 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
323   const MachineFrameInfo *MFI = MF.getFrameInfo();
324   const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
325 
326   return (NoFramePointerElim ||
327           needsStackRealignment(MF) ||
328           MFI->hasVarSizedObjects() ||
329           MFI->isFrameAddressTaken() ||
330           MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
331           (MMI && MMI->callsUnwindInit()));
332 }
333 
334 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
335   const MachineFrameInfo *MFI = MF.getFrameInfo();
336 
337   // FIXME: Currently we don't support stack realignment for functions with
338   // variable-sized allocas
339   return (RealignStack &&
340           (MFI->getMaxAlignment() > StackAlign &&
341            !MFI->hasVarSizedObjects()));
342 }
343 
344 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
345   return !MF.getFrameInfo()->hasVarSizedObjects();
346 }
347 
348 int
349 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
350   int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
351   uint64_t StackSize = MF.getFrameInfo()->getStackSize();
352 
353   if (needsStackRealignment(MF)) {
354     if (FI < 0)
355       // Skip the saved EBP
356       Offset += SlotSize;
357     else {
358       unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
359       assert( (-(Offset + StackSize)) % Align == 0);
360       Align = 0;
361       return Offset + StackSize;
362     }
363 
364     // FIXME: Support tail calls
365   } else {
366     if (!hasFP(MF))
367       return Offset + StackSize;
368 
369     // Skip the saved EBP
370     Offset += SlotSize;
371 
372     // Skip the RETADDR move area
373     X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
374     int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
375     if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
376   }
377 
378   return Offset;
379 }
380 
381 void X86RegisterInfo::
382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
383                               MachineBasicBlock::iterator I) const {
384   if (!hasReservedCallFrame(MF)) {
385     // If the stack pointer can be changed after prologue, turn the
386     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
387     // adjcallstackdown instruction into 'add ESP, <amt>'
388     // TODO: consider using push / pop instead of sub + store / add
389     MachineInstr *Old = I;
390     uint64_t Amount = Old->getOperand(0).getImm();
391     if (Amount != 0) {
392       // We need to keep the stack aligned properly.  To do this, we round the
393       // amount of space needed for the outgoing arguments up to the next
394       // alignment boundary.
395       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
396 
397       MachineInstr *New = 0;
398       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
399         New = BuildMI(MF, Old->getDebugLoc(),
400                       TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
401                       StackPtr).addReg(StackPtr).addImm(Amount);
402       } else {
403         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
404         // factor out the amount the callee already popped.
405         uint64_t CalleeAmt = Old->getOperand(1).getImm();
406         Amount -= CalleeAmt;
407         if (Amount) {
408           unsigned Opc = (Amount < 128) ?
409             (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
410             (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
411           New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
412             .addReg(StackPtr).addImm(Amount);
413         }
414       }
415 
416       if (New) {
417         // The EFLAGS implicit def is dead.
418         New->getOperand(3).setIsDead();
419 
420         // Replace the pseudo instruction with a new instruction...
421         MBB.insert(I, New);
422       }
423     }
424   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
425     // If we are performing frame pointer elimination and if the callee pops
426     // something off the stack pointer, add it back.  We do this until we have
427     // more advanced stack pointer tracking ability.
428     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
429       unsigned Opc = (CalleeAmt < 128) ?
430         (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
431         (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
432       MachineInstr *Old = I;
433       MachineInstr *New =
434         BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
435                 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
436       // The EFLAGS implicit def is dead.
437       New->getOperand(3).setIsDead();
438 
439       MBB.insert(I, New);
440     }
441   }
442 
443   MBB.erase(I);
444 }
445 
446 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
447                                           int SPAdj, RegScavenger *RS) const{
448   assert(SPAdj == 0 && "Unexpected");
449 
450   unsigned i = 0;
451   MachineInstr &MI = *II;
452   MachineFunction &MF = *MI.getParent()->getParent();
453   while (!MI.getOperand(i).isFI()) {
454     ++i;
455     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
456   }
457 
458   int FrameIndex = MI.getOperand(i).getIndex();
459 
460   unsigned BasePtr;
461   if (needsStackRealignment(MF))
462     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
463   else
464     BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
465 
466   // This must be part of a four operand memory reference.  Replace the
467   // FrameIndex with base register with EBP.  Add an offset to the offset.
468   MI.getOperand(i).ChangeToRegister(BasePtr, false);
469 
470   // Now add the frame object offset to the offset from EBP.
471   if (MI.getOperand(i+3).isImm()) {
472     // Offset is a 32-bit integer.
473     int Offset = getFrameIndexOffset(MF, FrameIndex) +
474       (int)(MI.getOperand(i+3).getImm());
475 
476      MI.getOperand(i+3).ChangeToImmediate(Offset);
477   } else {
478     // Offset is symbolic. This is extremely rare.
479     uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
480                       (uint64_t)MI.getOperand(i+3).getOffset();
481     MI.getOperand(i+3).setOffset(Offset);
482   }
483 }
484 
485 void
486 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
487                                                       RegScavenger *RS) const {
488   MachineFrameInfo *FFI = MF.getFrameInfo();
489 
490   // Calculate and set max stack object alignment early, so we can decide
491   // whether we will need stack realignment (and thus FP).
492   unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
493                                calculateMaxStackAlignment(FFI));
494 
495   FFI->setMaxAlignment(MaxAlign);
496 }
497 
498 void
499 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
500   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
501   int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
502   if (TailCallReturnAddrDelta < 0) {
503     // create RETURNADDR area
504     //   arg
505     //   arg
506     //   RETADDR
507     //   { ...
508     //     RETADDR area
509     //     ...
510     //   }
511     //   [EBP]
512     MF.getFrameInfo()->
513       CreateFixedObject(-TailCallReturnAddrDelta,
514                         (-1*SlotSize)+TailCallReturnAddrDelta);
515   }
516   if (hasFP(MF)) {
517     assert((TailCallReturnAddrDelta <= 0) &&
518            "The Delta should always be zero or negative");
519     // Create a frame entry for the EBP register that must be saved.
520     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
521                                                         (int)SlotSize * -2+
522                                                        TailCallReturnAddrDelta);
523     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
524            "Slot for EBP register must be last in order to be found!");
525     FrameIdx = 0;
526   }
527 }
528 
529 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
530 /// stack pointer by a constant value.
531 static
532 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
533                   unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
534                   const TargetInstrInfo &TII) {
535   bool isSub = NumBytes < 0;
536   uint64_t Offset = isSub ? -NumBytes : NumBytes;
537   unsigned Opc = isSub
538     ? ((Offset < 128) ?
539        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
540        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
541     : ((Offset < 128) ?
542        (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
543        (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
544   uint64_t Chunk = (1LL << 31) - 1;
545   DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
546                  DebugLoc::getUnknownLoc());
547 
548   while (Offset) {
549     uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
550     MachineInstr *MI =
551       BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
552          .addReg(StackPtr).addImm(ThisVal);
553     // The EFLAGS implicit def is dead.
554     MI->getOperand(3).setIsDead();
555     Offset -= ThisVal;
556   }
557 }
558 
559 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
560 static
561 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
562                       unsigned StackPtr, uint64_t *NumBytes = NULL) {
563   if (MBBI == MBB.begin()) return;
564 
565   MachineBasicBlock::iterator PI = prior(MBBI);
566   unsigned Opc = PI->getOpcode();
567   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
568        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
569       PI->getOperand(0).getReg() == StackPtr) {
570     if (NumBytes)
571       *NumBytes += PI->getOperand(2).getImm();
572     MBB.erase(PI);
573   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
574               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
575              PI->getOperand(0).getReg() == StackPtr) {
576     if (NumBytes)
577       *NumBytes -= PI->getOperand(2).getImm();
578     MBB.erase(PI);
579   }
580 }
581 
582 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
583 static
584 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
585                         MachineBasicBlock::iterator &MBBI,
586                         unsigned StackPtr, uint64_t *NumBytes = NULL) {
587   return;
588 
589   if (MBBI == MBB.end()) return;
590 
591   MachineBasicBlock::iterator NI = next(MBBI);
592   if (NI == MBB.end()) return;
593 
594   unsigned Opc = NI->getOpcode();
595   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
596        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
597       NI->getOperand(0).getReg() == StackPtr) {
598     if (NumBytes)
599       *NumBytes -= NI->getOperand(2).getImm();
600     MBB.erase(NI);
601     MBBI = NI;
602   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
603               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
604              NI->getOperand(0).getReg() == StackPtr) {
605     if (NumBytes)
606       *NumBytes += NI->getOperand(2).getImm();
607     MBB.erase(NI);
608     MBBI = NI;
609   }
610 }
611 
612 /// mergeSPUpdates - Checks the instruction before/after the passed
613 /// instruction. If it is an ADD/SUB instruction it is deleted
614 /// argument and the stack adjustment is returned as a positive value for ADD
615 /// and a negative for SUB.
616 static int mergeSPUpdates(MachineBasicBlock &MBB,
617                            MachineBasicBlock::iterator &MBBI,
618                            unsigned StackPtr,
619                            bool doMergeWithPrevious) {
620 
621   if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
622       (!doMergeWithPrevious && MBBI == MBB.end()))
623     return 0;
624 
625   int Offset = 0;
626 
627   MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
628   MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
629   unsigned Opc = PI->getOpcode();
630   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
631        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
632       PI->getOperand(0).getReg() == StackPtr){
633     Offset += PI->getOperand(2).getImm();
634     MBB.erase(PI);
635     if (!doMergeWithPrevious) MBBI = NI;
636   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
637               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
638              PI->getOperand(0).getReg() == StackPtr) {
639     Offset -= PI->getOperand(2).getImm();
640     MBB.erase(PI);
641     if (!doMergeWithPrevious) MBBI = NI;
642   }
643 
644   return Offset;
645 }
646 
647 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
648                                      unsigned FrameLabelId,
649                                      unsigned ReadyLabelId) const {
650   MachineFrameInfo *MFI = MF.getFrameInfo();
651   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
652   if (!MMI)
653     return;
654 
655   uint64_t StackSize = MFI->getStackSize();
656   std::vector<MachineMove> &Moves = MMI->getFrameMoves();
657   const TargetData *TD = MF.getTarget().getTargetData();
658 
659   // Calculate amount of bytes used for return address storing
660   int stackGrowth =
661     (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
662      TargetFrameInfo::StackGrowsUp ?
663      TD->getPointerSize() : -TD->getPointerSize());
664 
665   if (StackSize) {
666     // Show update of SP.
667     if (hasFP(MF)) {
668       // Adjust SP
669       MachineLocation SPDst(MachineLocation::VirtualFP);
670       MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
671       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
672     } else {
673       MachineLocation SPDst(MachineLocation::VirtualFP);
674       MachineLocation SPSrc(MachineLocation::VirtualFP,
675                             -StackSize+stackGrowth);
676       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
677     }
678   } else {
679     //FIXME: Verify & implement for FP
680     MachineLocation SPDst(StackPtr);
681     MachineLocation SPSrc(StackPtr, stackGrowth);
682     Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
683   }
684 
685   // Add callee saved registers to move list.
686   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
687 
688   // FIXME: This is dirty hack. The code itself is pretty mess right now.
689   // It should be rewritten from scratch and generalized sometimes.
690 
691   // Determine maximum offset (minumum due to stack growth)
692   int64_t MaxOffset = 0;
693   for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
694     MaxOffset = std::min(MaxOffset,
695                          MFI->getObjectOffset(CSI[I].getFrameIdx()));
696 
697   // Calculate offsets
698   int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
699   for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
700     int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
701     unsigned Reg = CSI[I].getReg();
702     Offset = (MaxOffset-Offset+saveAreaOffset);
703     MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
704     MachineLocation CSSrc(Reg);
705     Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
706   }
707 
708   if (hasFP(MF)) {
709     // Save FP
710     MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
711     MachineLocation FPSrc(FramePtr);
712     Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
713   }
714 
715   MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
716   MachineLocation FPSrc(MachineLocation::VirtualFP);
717   Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
718 }
719 
720 
721 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
722   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
723   MachineFrameInfo *MFI = MF.getFrameInfo();
724   const Function* Fn = MF.getFunction();
725   const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
726   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
727   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
728   MachineBasicBlock::iterator MBBI = MBB.begin();
729   bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
730                           !Fn->doesNotThrow() ||
731                           UnwindTablesMandatory;
732   DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
733                  DebugLoc::getUnknownLoc());
734 
735   // Prepare for frame info.
736   unsigned FrameLabelId = 0;
737 
738   // Get the number of bytes to allocate from the FrameInfo.
739   uint64_t StackSize = MFI->getStackSize();
740 
741   // Get desired stack alignment
742   uint64_t MaxAlign  = MFI->getMaxAlignment();
743 
744   // Add RETADDR move area to callee saved frame size.
745   int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
746   if (TailCallReturnAddrDelta < 0)
747     X86FI->setCalleeSavedFrameSize(
748           X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
749 
750   // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
751   // function, and use up to 128 bytes of stack space, don't have a frame
752   // pointer, calls, or dynamic alloca then we do not need to adjust the
753   // stack pointer (we fit in the Red Zone).
754   bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
755   if (Is64Bit && !DisableRedZone &&
756       !needsStackRealignment(MF) &&
757       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
758       !MFI->hasCalls() &&                          // No calls.
759       !Subtarget->isTargetWin64()) {               // Win64 has no Red Zone
760     uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
761     if (hasFP(MF)) MinSize += SlotSize;
762     StackSize = std::max(MinSize,
763                          StackSize > 128 ? StackSize - 128 : 0);
764     MFI->setStackSize(StackSize);
765   }
766 
767   // Insert stack pointer adjustment for later moving of return addr.  Only
768   // applies to tail call optimized functions where the callee argument stack
769   // size is bigger than the callers.
770   if (TailCallReturnAddrDelta < 0) {
771     MachineInstr *MI =
772       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
773               StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
774     // The EFLAGS implicit def is dead.
775     MI->getOperand(3).setIsDead();
776   }
777 
778   uint64_t NumBytes = 0;
779   if (hasFP(MF)) {
780     // Calculate required stack adjustment
781     uint64_t FrameSize = StackSize - SlotSize;
782     if (needsStackRealignment(MF))
783       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
784 
785     NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
786 
787     // Get the offset of the stack slot for the EBP register... which is
788     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
789     // Update the frame offset adjustment.
790     MFI->setOffsetAdjustment(-NumBytes);
791 
792     // Save EBP into the appropriate stack slot...
793     BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
794       .addReg(FramePtr, RegState::Kill);
795 
796     if (needsFrameMoves) {
797       // Mark effective beginning of when frame pointer becomes valid.
798       FrameLabelId = MMI->NextLabelID();
799       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
800     }
801 
802     // Update EBP with the new base value...
803     BuildMI(MBB, MBBI, DL,
804             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
805         .addReg(StackPtr);
806 
807     // Mark the FramePtr as live-in in every block except the entry.
808     for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
809          I != E; ++I)
810       I->addLiveIn(FramePtr);
811 
812     // Realign stack
813     if (needsStackRealignment(MF)) {
814       MachineInstr *MI =
815         BuildMI(MBB, MBBI, DL,
816                 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
817                 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
818       // The EFLAGS implicit def is dead.
819       MI->getOperand(3).setIsDead();
820     }
821   } else {
822     NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
823   }
824 
825   unsigned ReadyLabelId = 0;
826   if (needsFrameMoves) {
827     // Mark effective beginning of when frame pointer is ready.
828     ReadyLabelId = MMI->NextLabelID();
829     BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
830   }
831 
832   // Skip the callee-saved push instructions.
833   while (MBBI != MBB.end() &&
834          (MBBI->getOpcode() == X86::PUSH32r ||
835           MBBI->getOpcode() == X86::PUSH64r))
836     ++MBBI;
837 
838   if (MBBI != MBB.end())
839     DL = MBBI->getDebugLoc();
840 
841   // Adjust stack pointer: ESP -= numbytes.
842   if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
843     // Check, whether EAX is livein for this function.
844     bool isEAXAlive = false;
845     for (MachineRegisterInfo::livein_iterator
846            II = MF.getRegInfo().livein_begin(),
847            EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
848       unsigned Reg = II->first;
849       isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
850                     Reg == X86::AH || Reg == X86::AL);
851     }
852 
853     // Function prologue calls _alloca to probe the stack when allocating more
854     // than 4k bytes in one go. Touching the stack at 4K increments is necessary
855     // to ensure that the guard pages used by the OS virtual memory manager are
856     // allocated in correct sequence.
857     if (!isEAXAlive) {
858       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
859         .addImm(NumBytes);
860       BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
861         .addExternalSymbol("_alloca");
862     } else {
863       // Save EAX
864       BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
865         .addReg(X86::EAX, RegState::Kill);
866 
867       // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
868       // allocated bytes for EAX.
869       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
870         .addImm(NumBytes - 4);
871       BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
872         .addExternalSymbol("_alloca");
873 
874       // Restore EAX
875       MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
876                                               X86::EAX),
877                                       StackPtr, false, NumBytes - 4);
878       MBB.insert(MBBI, MI);
879     }
880   } else if (NumBytes) {
881     // If there is an SUB32ri of ESP immediately before this instruction, merge
882     // the two. This can be the case when tail call elimination is enabled and
883     // the callee has more arguments then the caller.
884     NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
885 
886     // If there is an ADD32ri or SUB32ri of ESP immediately after this
887     // instruction, merge the two instructions.
888     mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
889 
890     if (NumBytes)
891       emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
892   }
893 
894   if (needsFrameMoves)
895     emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
896 }
897 
898 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
899                                    MachineBasicBlock &MBB) const {
900   const MachineFrameInfo *MFI = MF.getFrameInfo();
901   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
902   MachineBasicBlock::iterator MBBI = prior(MBB.end());
903   unsigned RetOpcode = MBBI->getOpcode();
904   DebugLoc DL = MBBI->getDebugLoc();
905 
906   switch (RetOpcode) {
907   case X86::RET:
908   case X86::RETI:
909   case X86::TCRETURNdi:
910   case X86::TCRETURNri:
911   case X86::TCRETURNri64:
912   case X86::TCRETURNdi64:
913   case X86::EH_RETURN:
914   case X86::EH_RETURN64:
915   case X86::TAILJMPd:
916   case X86::TAILJMPr:
917   case X86::TAILJMPm: break;  // These are ok
918   default:
919     assert(0 && "Can only insert epilog into returning blocks");
920   }
921 
922   // Get the number of bytes to allocate from the FrameInfo
923   uint64_t StackSize = MFI->getStackSize();
924   uint64_t MaxAlign  = MFI->getMaxAlignment();
925   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
926   uint64_t NumBytes = 0;
927 
928   if (hasFP(MF)) {
929     // Calculate required stack adjustment
930     uint64_t FrameSize = StackSize - SlotSize;
931     if (needsStackRealignment(MF))
932       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
933 
934     NumBytes = FrameSize - CSSize;
935 
936     // pop EBP.
937     BuildMI(MBB, MBBI, DL,
938             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
939   } else {
940     NumBytes = StackSize - CSSize;
941   }
942 
943   // Skip the callee-saved pop instructions.
944   MachineBasicBlock::iterator LastCSPop = MBBI;
945   while (MBBI != MBB.begin()) {
946     MachineBasicBlock::iterator PI = prior(MBBI);
947     unsigned Opc = PI->getOpcode();
948     if (Opc != X86::POP32r && Opc != X86::POP64r &&
949         !PI->getDesc().isTerminator())
950       break;
951     --MBBI;
952   }
953 
954   DL = MBBI->getDebugLoc();
955 
956   // If there is an ADD32ri or SUB32ri of ESP immediately before this
957   // instruction, merge the two instructions.
958   if (NumBytes || MFI->hasVarSizedObjects())
959     mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
960 
961   // If dynamic alloca is used, then reset esp to point to the last callee-saved
962   // slot before popping them off! Same applies for the case, when stack was
963   // realigned
964   if (needsStackRealignment(MF)) {
965     // We cannot use LEA here, because stack pointer was realigned. We need to
966     // deallocate local frame back
967     if (CSSize) {
968       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
969       MBBI = prior(LastCSPop);
970     }
971 
972     BuildMI(MBB, MBBI, DL,
973             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
974             StackPtr).addReg(FramePtr);
975   } else if (MFI->hasVarSizedObjects()) {
976     if (CSSize) {
977       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
978       MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
979                                          FramePtr, false, -CSSize);
980       MBB.insert(MBBI, MI);
981     } else
982       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
983               StackPtr).addReg(FramePtr);
984 
985   } else {
986     // adjust stack pointer back: ESP += numbytes
987     if (NumBytes)
988       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
989   }
990 
991   // We're returning from function via eh_return.
992   if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
993     MBBI = prior(MBB.end());
994     MachineOperand &DestAddr  = MBBI->getOperand(0);
995     assert(DestAddr.isReg() && "Offset should be in register!");
996     BuildMI(MBB, MBBI, DL,
997             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
998             StackPtr).addReg(DestAddr.getReg());
999   // Tail call return: adjust the stack pointer and jump to callee
1000   } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1001              RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1002     MBBI = prior(MBB.end());
1003     MachineOperand &JumpTarget = MBBI->getOperand(0);
1004     MachineOperand &StackAdjust = MBBI->getOperand(1);
1005     assert(StackAdjust.isImm() && "Expecting immediate value.");
1006 
1007     // Adjust stack pointer.
1008     int StackAdj = StackAdjust.getImm();
1009     int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1010     int Offset = 0;
1011     assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1012     // Incoporate the retaddr area.
1013     Offset = StackAdj-MaxTCDelta;
1014     assert(Offset >= 0 && "Offset should never be negative");
1015 
1016     if (Offset) {
1017       // Check for possible merge with preceeding ADD instruction.
1018       Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1019       emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1020     }
1021 
1022     // Jump to label or value in register.
1023     if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1024       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1025         addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1026     else if (RetOpcode== X86::TCRETURNri64)
1027       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1028     else
1029        BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1030 
1031     // Delete the pseudo instruction TCRETURN.
1032     MBB.erase(MBBI);
1033   } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1034              (X86FI->getTCReturnAddrDelta() < 0)) {
1035     // Add the return addr area delta back since we are not tail calling.
1036     int delta = -1*X86FI->getTCReturnAddrDelta();
1037     MBBI = prior(MBB.end());
1038     // Check for possible merge with preceeding ADD instruction.
1039     delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1040     emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1041   }
1042 }
1043 
1044 unsigned X86RegisterInfo::getRARegister() const {
1045   if (Is64Bit)
1046     return X86::RIP;  // Should have dwarf #16
1047   else
1048     return X86::EIP;  // Should have dwarf #8
1049 }
1050 
1051 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1052   return hasFP(MF) ? FramePtr : StackPtr;
1053 }
1054 
1055 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1056                                                                          const {
1057   // Calculate amount of bytes used for return address storing
1058   int stackGrowth = (Is64Bit ? -8 : -4);
1059 
1060   // Initial state of the frame pointer is esp+4.
1061   MachineLocation Dst(MachineLocation::VirtualFP);
1062   MachineLocation Src(StackPtr, stackGrowth);
1063   Moves.push_back(MachineMove(0, Dst, Src));
1064 
1065   // Add return address to move list
1066   MachineLocation CSDst(StackPtr, stackGrowth);
1067   MachineLocation CSSrc(getRARegister());
1068   Moves.push_back(MachineMove(0, CSDst, CSSrc));
1069 }
1070 
1071 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1072   assert(0 && "What is the exception register");
1073   return 0;
1074 }
1075 
1076 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1077   assert(0 && "What is the exception handler register");
1078   return 0;
1079 }
1080 
1081 namespace llvm {
1082 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1083   switch (VT.getSimpleVT()) {
1084   default: return Reg;
1085   case MVT::i8:
1086     if (High) {
1087       switch (Reg) {
1088       default: return 0;
1089       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1090         return X86::AH;
1091       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1092         return X86::DH;
1093       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1094         return X86::CH;
1095       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1096         return X86::BH;
1097       }
1098     } else {
1099       switch (Reg) {
1100       default: return 0;
1101       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1102         return X86::AL;
1103       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1104         return X86::DL;
1105       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1106         return X86::CL;
1107       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1108         return X86::BL;
1109       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1110         return X86::SIL;
1111       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1112         return X86::DIL;
1113       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1114         return X86::BPL;
1115       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1116         return X86::SPL;
1117       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1118         return X86::R8B;
1119       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1120         return X86::R9B;
1121       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1122         return X86::R10B;
1123       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1124         return X86::R11B;
1125       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1126         return X86::R12B;
1127       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1128         return X86::R13B;
1129       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1130         return X86::R14B;
1131       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1132         return X86::R15B;
1133       }
1134     }
1135   case MVT::i16:
1136     switch (Reg) {
1137     default: return Reg;
1138     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1139       return X86::AX;
1140     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1141       return X86::DX;
1142     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1143       return X86::CX;
1144     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1145       return X86::BX;
1146     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1147       return X86::SI;
1148     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1149       return X86::DI;
1150     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1151       return X86::BP;
1152     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1153       return X86::SP;
1154     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1155       return X86::R8W;
1156     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1157       return X86::R9W;
1158     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1159       return X86::R10W;
1160     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1161       return X86::R11W;
1162     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1163       return X86::R12W;
1164     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1165       return X86::R13W;
1166     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1167       return X86::R14W;
1168     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1169       return X86::R15W;
1170     }
1171   case MVT::i32:
1172     switch (Reg) {
1173     default: return Reg;
1174     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1175       return X86::EAX;
1176     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1177       return X86::EDX;
1178     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1179       return X86::ECX;
1180     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1181       return X86::EBX;
1182     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1183       return X86::ESI;
1184     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1185       return X86::EDI;
1186     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1187       return X86::EBP;
1188     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1189       return X86::ESP;
1190     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1191       return X86::R8D;
1192     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1193       return X86::R9D;
1194     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1195       return X86::R10D;
1196     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1197       return X86::R11D;
1198     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1199       return X86::R12D;
1200     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1201       return X86::R13D;
1202     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1203       return X86::R14D;
1204     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1205       return X86::R15D;
1206     }
1207   case MVT::i64:
1208     switch (Reg) {
1209     default: return Reg;
1210     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1211       return X86::RAX;
1212     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1213       return X86::RDX;
1214     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1215       return X86::RCX;
1216     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1217       return X86::RBX;
1218     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1219       return X86::RSI;
1220     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1221       return X86::RDI;
1222     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1223       return X86::RBP;
1224     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1225       return X86::RSP;
1226     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1227       return X86::R8;
1228     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1229       return X86::R9;
1230     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1231       return X86::R10;
1232     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1233       return X86::R11;
1234     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1235       return X86::R12;
1236     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1237       return X86::R13;
1238     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1239       return X86::R14;
1240     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1241       return X86::R15;
1242     }
1243   }
1244 
1245   return Reg;
1246 }
1247 }
1248 
1249 #include "X86GenRegisterInfo.inc"
1250 
1251 namespace {
1252   struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1253     static char ID;
1254     MSAC() : MachineFunctionPass(&ID) {}
1255 
1256     virtual bool runOnMachineFunction(MachineFunction &MF) {
1257       MachineFrameInfo *FFI = MF.getFrameInfo();
1258       MachineRegisterInfo &RI = MF.getRegInfo();
1259 
1260       // Calculate max stack alignment of all already allocated stack objects.
1261       unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1262 
1263       // Be over-conservative: scan over all vreg defs and find, whether vector
1264       // registers are used. If yes - there is probability, that vector register
1265       // will be spilled and thus stack needs to be aligned properly.
1266       for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1267            RegNum < RI.getLastVirtReg(); ++RegNum)
1268         MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1269 
1270       FFI->setMaxAlignment(MaxAlign);
1271 
1272       return false;
1273     }
1274 
1275     virtual const char *getPassName() const {
1276       return "X86 Maximal Stack Alignment Calculator";
1277     }
1278   };
1279 
1280   char MSAC::ID = 0;
1281 }
1282 
1283 FunctionPass*
1284 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }
1285