1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
12 // on X86.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "X86RegisterInfo.h"
17 #include "X86FrameLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/MachineValueType.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
46 
47 static cl::opt<bool>
48 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49           cl::desc("Enable use of a base pointer for complex stack frames"));
50 
51 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53                          X86_MC::getDwarfRegFlavour(TT, false),
54                          X86_MC::getDwarfRegFlavour(TT, true),
55                          (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56   X86_MC::InitLLVM2SEHRegisterMapping(this);
57 
58   // Cache some information.
59   Is64Bit = TT.isArch64Bit();
60   IsWin64 = Is64Bit && TT.isOSWindows();
61 
62   // Use a callee-saved register as the base pointer.  These registers must
63   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
64   // requires GOT in the EBX register before function calls via PLT GOT pointer.
65   if (Is64Bit) {
66     SlotSize = 8;
67     // This matches the simplified 32-bit pointer code in the data layout
68     // computation.
69     // FIXME: Should use the data layout?
70     bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71     StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72     FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73     BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
74   } else {
75     SlotSize = 4;
76     StackPtr = X86::ESP;
77     FramePtr = X86::EBP;
78     BasePtr = X86::ESI;
79   }
80 }
81 
82 bool
83 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84   // ExeDepsFixer and PostRAScheduler require liveness.
85   return true;
86 }
87 
88 int
89 X86RegisterInfo::getSEHRegNum(unsigned i) const {
90   return getEncodingValue(i);
91 }
92 
93 const TargetRegisterClass *
94 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95                                        unsigned Idx) const {
96   // The sub_8bit sub-register index is more constrained in 32-bit mode.
97   // It behaves just like the sub_8bit_hi index.
98   if (!Is64Bit && Idx == X86::sub_8bit)
99     Idx = X86::sub_8bit_hi;
100 
101   // Forward to TableGen's default version.
102   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
103 }
104 
105 const TargetRegisterClass *
106 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107                                           const TargetRegisterClass *B,
108                                           unsigned SubIdx) const {
109   // The sub_8bit sub-register index is more constrained in 32-bit mode.
110   if (!Is64Bit && SubIdx == X86::sub_8bit) {
111     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
112     if (!A)
113       return nullptr;
114   }
115   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
116 }
117 
118 const TargetRegisterClass *
119 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120                                            const MachineFunction &MF) const {
121   // Don't allow super-classes of GR8_NOREX.  This class is only used after
122   // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
123   // to the full GR8 register class in 64-bit mode, so we cannot allow the
124   // reigster class inflation.
125   //
126   // The GR8_NOREX class is always used in a way that won't be constrained to a
127   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128   // full GR8 class.
129   if (RC == &X86::GR8_NOREXRegClass)
130     return RC;
131 
132   const TargetRegisterClass *Super = RC;
133   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
134   do {
135     switch (Super->getID()) {
136     case X86::GR8RegClassID:
137     case X86::GR16RegClassID:
138     case X86::GR32RegClassID:
139     case X86::GR64RegClassID:
140     case X86::FR32RegClassID:
141     case X86::FR64RegClassID:
142     case X86::RFP32RegClassID:
143     case X86::RFP64RegClassID:
144     case X86::RFP80RegClassID:
145     case X86::VR128RegClassID:
146     case X86::VR256RegClassID:
147       // Don't return a super-class that would shrink the spill size.
148       // That can happen with the vector and float classes.
149       if (Super->getSize() == RC->getSize())
150         return Super;
151     }
152     Super = *I++;
153   } while (Super);
154   return RC;
155 }
156 
157 const TargetRegisterClass *
158 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159                                     unsigned Kind) const {
160   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
161   switch (Kind) {
162   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163   case 0: // Normal GPRs.
164     if (Subtarget.isTarget64BitLP64())
165       return &X86::GR64RegClass;
166     return &X86::GR32RegClass;
167   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168     if (Subtarget.isTarget64BitLP64())
169       return &X86::GR64_NOSPRegClass;
170     return &X86::GR32_NOSPRegClass;
171   case 2: // NOREX GPRs.
172     if (Subtarget.isTarget64BitLP64())
173       return &X86::GR64_NOREXRegClass;
174     return &X86::GR32_NOREXRegClass;
175   case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
176     if (Subtarget.isTarget64BitLP64())
177       return &X86::GR64_NOREX_NOSPRegClass;
178     return &X86::GR32_NOREX_NOSPRegClass;
179   case 4: // Available for tailcall (not callee-saved GPRs).
180     return getGPRsForTailCall(MF);
181   }
182 }
183 
184 const TargetRegisterClass *
185 X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
186   const Function *F = MF.getFunction();
187   if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
188     return &X86::GR64_TCW64RegClass;
189   else if (Is64Bit)
190     return &X86::GR64_TCRegClass;
191 
192   bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
193   if (hasHipeCC)
194     return &X86::GR32RegClass;
195   return &X86::GR32_TCRegClass;
196 }
197 
198 const TargetRegisterClass *
199 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200   if (RC == &X86::CCRRegClass) {
201     if (Is64Bit)
202       return &X86::GR64RegClass;
203     else
204       return &X86::GR32RegClass;
205   }
206   return RC;
207 }
208 
209 unsigned
210 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211                                      MachineFunction &MF) const {
212   const X86FrameLowering *TFI = getFrameLowering(MF);
213 
214   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215   switch (RC->getID()) {
216   default:
217     return 0;
218   case X86::GR32RegClassID:
219     return 4 - FPDiff;
220   case X86::GR64RegClassID:
221     return 12 - FPDiff;
222   case X86::VR128RegClassID:
223     return Is64Bit ? 10 : 4;
224   case X86::VR64RegClassID:
225     return 4;
226   }
227 }
228 
229 const MCPhysReg *
230 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231   const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
232   bool HasAVX = Subtarget.hasAVX();
233   bool HasAVX512 = Subtarget.hasAVX512();
234   bool CallsEHReturn = MF->getMMI().callsEHReturn();
235 
236   assert(MF && "MachineFunction required");
237   switch (MF->getFunction()->getCallingConv()) {
238   case CallingConv::GHC:
239   case CallingConv::HiPE:
240     return CSR_NoRegs_SaveList;
241   case CallingConv::AnyReg:
242     if (HasAVX)
243       return CSR_64_AllRegs_AVX_SaveList;
244     return CSR_64_AllRegs_SaveList;
245   case CallingConv::PreserveMost:
246     return CSR_64_RT_MostRegs_SaveList;
247   case CallingConv::PreserveAll:
248     if (HasAVX)
249       return CSR_64_RT_AllRegs_AVX_SaveList;
250     return CSR_64_RT_AllRegs_SaveList;
251   case CallingConv::CXX_FAST_TLS:
252     if (Is64Bit)
253       return CSR_64_TLS_Darwin_SaveList;
254     break;
255   case CallingConv::Intel_OCL_BI: {
256     if (HasAVX512 && IsWin64)
257       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
258     if (HasAVX512 && Is64Bit)
259       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
260     if (HasAVX && IsWin64)
261       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
262     if (HasAVX && Is64Bit)
263       return CSR_64_Intel_OCL_BI_AVX_SaveList;
264     if (!HasAVX && !IsWin64 && Is64Bit)
265       return CSR_64_Intel_OCL_BI_SaveList;
266     break;
267   }
268   case CallingConv::HHVM:
269     return CSR_64_HHVM_SaveList;
270   case CallingConv::Cold:
271     if (Is64Bit)
272       return CSR_64_MostRegs_SaveList;
273     break;
274   case CallingConv::X86_64_Win64:
275     return CSR_Win64_SaveList;
276   case CallingConv::X86_64_SysV:
277     if (CallsEHReturn)
278       return CSR_64EHRet_SaveList;
279     return CSR_64_SaveList;
280   default:
281     break;
282   }
283 
284   if (Is64Bit) {
285     if (IsWin64)
286       return CSR_Win64_SaveList;
287     if (CallsEHReturn)
288       return CSR_64EHRet_SaveList;
289     return CSR_64_SaveList;
290   }
291   if (CallsEHReturn)
292     return CSR_32EHRet_SaveList;
293   return CSR_32_SaveList;
294 }
295 
296 const uint32_t *
297 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
298                                       CallingConv::ID CC) const {
299   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
300   bool HasAVX = Subtarget.hasAVX();
301   bool HasAVX512 = Subtarget.hasAVX512();
302 
303   switch (CC) {
304   case CallingConv::GHC:
305   case CallingConv::HiPE:
306     return CSR_NoRegs_RegMask;
307   case CallingConv::AnyReg:
308     if (HasAVX)
309       return CSR_64_AllRegs_AVX_RegMask;
310     return CSR_64_AllRegs_RegMask;
311   case CallingConv::PreserveMost:
312     return CSR_64_RT_MostRegs_RegMask;
313   case CallingConv::PreserveAll:
314     if (HasAVX)
315       return CSR_64_RT_AllRegs_AVX_RegMask;
316     return CSR_64_RT_AllRegs_RegMask;
317   case CallingConv::CXX_FAST_TLS:
318     if (Is64Bit)
319       return CSR_64_TLS_Darwin_RegMask;
320     break;
321   case CallingConv::Intel_OCL_BI: {
322     if (HasAVX512 && IsWin64)
323       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
324     if (HasAVX512 && Is64Bit)
325       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
326     if (HasAVX && IsWin64)
327       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
328     if (HasAVX && Is64Bit)
329       return CSR_64_Intel_OCL_BI_AVX_RegMask;
330     if (!HasAVX && !IsWin64 && Is64Bit)
331       return CSR_64_Intel_OCL_BI_RegMask;
332     break;
333   }
334   case CallingConv::HHVM:
335     return CSR_64_HHVM_RegMask;
336   case CallingConv::Cold:
337     if (Is64Bit)
338       return CSR_64_MostRegs_RegMask;
339     break;
340   default:
341     break;
342   case CallingConv::X86_64_Win64:
343     return CSR_Win64_RegMask;
344   case CallingConv::X86_64_SysV:
345     return CSR_64_RegMask;
346   }
347 
348   // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
349   // callsEHReturn().
350   if (Is64Bit) {
351     if (IsWin64)
352       return CSR_Win64_RegMask;
353     return CSR_64_RegMask;
354   }
355   return CSR_32_RegMask;
356 }
357 
358 const uint32_t*
359 X86RegisterInfo::getNoPreservedMask() const {
360   return CSR_NoRegs_RegMask;
361 }
362 
363 const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
364   return CSR_64_TLS_Darwin_RegMask;
365 }
366 
367 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
368   BitVector Reserved(getNumRegs());
369   const X86FrameLowering *TFI = getFrameLowering(MF);
370 
371   // Set the stack-pointer register and its aliases as reserved.
372   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
373        ++I)
374     Reserved.set(*I);
375 
376   // Set the instruction pointer register and its aliases as reserved.
377   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
378        ++I)
379     Reserved.set(*I);
380 
381   // Set the frame-pointer register and its aliases as reserved if needed.
382   if (TFI->hasFP(MF)) {
383     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
384          ++I)
385       Reserved.set(*I);
386   }
387 
388   // Set the base-pointer register and its aliases as reserved if needed.
389   if (hasBasePointer(MF)) {
390     CallingConv::ID CC = MF.getFunction()->getCallingConv();
391     const uint32_t *RegMask = getCallPreservedMask(MF, CC);
392     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
393       report_fatal_error(
394         "Stack realignment in presence of dynamic allocas is not supported with"
395         "this calling convention.");
396 
397     unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
398                                               false);
399     for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
400          I.isValid(); ++I)
401       Reserved.set(*I);
402   }
403 
404   // Mark the segment registers as reserved.
405   Reserved.set(X86::CS);
406   Reserved.set(X86::SS);
407   Reserved.set(X86::DS);
408   Reserved.set(X86::ES);
409   Reserved.set(X86::FS);
410   Reserved.set(X86::GS);
411 
412   // Mark the floating point stack registers as reserved.
413   for (unsigned n = 0; n != 8; ++n)
414     Reserved.set(X86::ST0 + n);
415 
416   // Reserve the registers that only exist in 64-bit mode.
417   if (!Is64Bit) {
418     // These 8-bit registers are part of the x86-64 extension even though their
419     // super-registers are old 32-bits.
420     Reserved.set(X86::SIL);
421     Reserved.set(X86::DIL);
422     Reserved.set(X86::BPL);
423     Reserved.set(X86::SPL);
424 
425     for (unsigned n = 0; n != 8; ++n) {
426       // R8, R9, ...
427       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
428         Reserved.set(*AI);
429 
430       // XMM8, XMM9, ...
431       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
432         Reserved.set(*AI);
433     }
434   }
435   if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
436     for (unsigned n = 16; n != 32; ++n) {
437       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
438         Reserved.set(*AI);
439     }
440   }
441 
442   return Reserved;
443 }
444 
445 void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
446   // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
447   // because the calling convention defines the EFLAGS register as NOT
448   // preserved.
449   //
450   // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
451   // an assert to track this and clear the register afterwards to avoid
452   // unnecessary crashes during release builds.
453   assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
454          "EFLAGS are not live-out from a patchpoint.");
455 
456   // Also clean other registers that don't need preserving (IP).
457   for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
458     Mask[Reg / 32] &= ~(1U << (Reg % 32));
459 }
460 
461 //===----------------------------------------------------------------------===//
462 // Stack Frame Processing methods
463 //===----------------------------------------------------------------------===//
464 
465 static bool CantUseSP(const MachineFrameInfo *MFI) {
466   return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
467 }
468 
469 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
470    const MachineFrameInfo *MFI = MF.getFrameInfo();
471 
472    if (!EnableBasePointer)
473      return false;
474 
475    // When we need stack realignment, we can't address the stack from the frame
476    // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
477    // can't address variables from the stack pointer.  MS inline asm can
478    // reference locals while also adjusting the stack pointer.  When we can't
479    // use both the SP and the FP, we need a separate base pointer register.
480    bool CantUseFP = needsStackRealignment(MF);
481    return CantUseFP && CantUseSP(MFI);
482 }
483 
484 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
485   if (!TargetRegisterInfo::canRealignStack(MF))
486     return false;
487 
488   const MachineFrameInfo *MFI = MF.getFrameInfo();
489   const MachineRegisterInfo *MRI = &MF.getRegInfo();
490 
491   // Stack realignment requires a frame pointer.  If we already started
492   // register allocation with frame pointer elimination, it is too late now.
493   if (!MRI->canReserveReg(FramePtr))
494     return false;
495 
496   // If a base pointer is necessary.  Check that it isn't too late to reserve
497   // it.
498   if (CantUseSP(MFI))
499     return MRI->canReserveReg(BasePtr);
500   return true;
501 }
502 
503 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
504                                            unsigned Reg, int &FrameIdx) const {
505   // Since X86 defines assignCalleeSavedSpillSlots which always return true
506   // this function neither used nor tested.
507   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
508 }
509 
510 void
511 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
512                                      int SPAdj, unsigned FIOperandNum,
513                                      RegScavenger *RS) const {
514   MachineInstr &MI = *II;
515   MachineFunction &MF = *MI.getParent()->getParent();
516   const X86FrameLowering *TFI = getFrameLowering(MF);
517   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
518   unsigned BasePtr;
519 
520   unsigned Opc = MI.getOpcode();
521   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
522                     Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
523 
524   if (hasBasePointer(MF))
525     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
526   else if (needsStackRealignment(MF))
527     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
528   else if (AfterFPPop)
529     BasePtr = StackPtr;
530   else
531     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
532 
533   // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
534   // simple FP case, and doesn't work with stack realignment. On 32-bit, the
535   // offset is from the traditional base pointer location.  On 64-bit, the
536   // offset is from the SP at the end of the prologue, not the FP location. This
537   // matches the behavior of llvm.frameaddress.
538   unsigned IgnoredFrameReg;
539   if (Opc == TargetOpcode::LOCAL_ESCAPE) {
540     MachineOperand &FI = MI.getOperand(FIOperandNum);
541     int Offset;
542     Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
543     FI.ChangeToImmediate(Offset);
544     return;
545   }
546 
547   // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
548   // register as source operand, semantic is the same and destination is
549   // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
550   if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
551     BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
552 
553   // This must be part of a four operand memory reference.  Replace the
554   // FrameIndex with base register with EBP.  Add an offset to the offset.
555   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
556 
557   // Now add the frame object offset to the offset from EBP.
558   int FIOffset;
559   if (AfterFPPop) {
560     // Tail call jmp happens after FP is popped.
561     const MachineFrameInfo *MFI = MF.getFrameInfo();
562     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
563   } else
564     FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
565 
566   if (BasePtr == StackPtr)
567     FIOffset += SPAdj;
568 
569   // The frame index format for stackmaps and patchpoints is different from the
570   // X86 format. It only has a FI and an offset.
571   if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
572     assert(BasePtr == FramePtr && "Expected the FP as base register");
573     int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
574     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
575     return;
576   }
577 
578   if (MI.getOperand(FIOperandNum+3).isImm()) {
579     // Offset is a 32-bit integer.
580     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
581     int Offset = FIOffset + Imm;
582     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
583            "Requesting 64-bit offset in 32-bit immediate!");
584     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
585   } else {
586     // Offset is symbolic. This is extremely rare.
587     uint64_t Offset = FIOffset +
588       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
589     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
590   }
591 }
592 
593 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
594   const X86FrameLowering *TFI = getFrameLowering(MF);
595   return TFI->hasFP(MF) ? FramePtr : StackPtr;
596 }
597 
598 unsigned
599 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
600   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
601   unsigned FrameReg = getFrameRegister(MF);
602   if (Subtarget.isTarget64BitILP32())
603     FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
604   return FrameReg;
605 }
606 
607 namespace llvm {
608 unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
609                                       bool High) {
610   switch (VT) {
611   default: return 0;
612   case MVT::i8:
613     if (High) {
614       switch (Reg) {
615       default: return getX86SubSuperRegister(Reg, MVT::i64);
616       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
617         return X86::SI;
618       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
619         return X86::DI;
620       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
621         return X86::BP;
622       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
623         return X86::SP;
624       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
625         return X86::AH;
626       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
627         return X86::DH;
628       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
629         return X86::CH;
630       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
631         return X86::BH;
632       }
633     } else {
634       switch (Reg) {
635       default: return 0;
636       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
637         return X86::AL;
638       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
639         return X86::DL;
640       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
641         return X86::CL;
642       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
643         return X86::BL;
644       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
645         return X86::SIL;
646       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
647         return X86::DIL;
648       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
649         return X86::BPL;
650       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
651         return X86::SPL;
652       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
653         return X86::R8B;
654       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
655         return X86::R9B;
656       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
657         return X86::R10B;
658       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
659         return X86::R11B;
660       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
661         return X86::R12B;
662       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
663         return X86::R13B;
664       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
665         return X86::R14B;
666       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
667         return X86::R15B;
668       }
669     }
670   case MVT::i16:
671     switch (Reg) {
672     default: return 0;
673     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
674       return X86::AX;
675     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
676       return X86::DX;
677     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
678       return X86::CX;
679     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
680       return X86::BX;
681     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
682       return X86::SI;
683     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
684       return X86::DI;
685     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
686       return X86::BP;
687     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
688       return X86::SP;
689     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
690       return X86::R8W;
691     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
692       return X86::R9W;
693     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
694       return X86::R10W;
695     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
696       return X86::R11W;
697     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
698       return X86::R12W;
699     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
700       return X86::R13W;
701     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
702       return X86::R14W;
703     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
704       return X86::R15W;
705     }
706   case MVT::i32:
707     switch (Reg) {
708     default: return 0;
709     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
710       return X86::EAX;
711     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
712       return X86::EDX;
713     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
714       return X86::ECX;
715     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
716       return X86::EBX;
717     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
718       return X86::ESI;
719     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
720       return X86::EDI;
721     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
722       return X86::EBP;
723     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
724       return X86::ESP;
725     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
726       return X86::R8D;
727     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
728       return X86::R9D;
729     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
730       return X86::R10D;
731     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
732       return X86::R11D;
733     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
734       return X86::R12D;
735     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
736       return X86::R13D;
737     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
738       return X86::R14D;
739     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
740       return X86::R15D;
741     }
742   case MVT::i64:
743     switch (Reg) {
744     default: return 0;
745     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
746       return X86::RAX;
747     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
748       return X86::RDX;
749     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
750       return X86::RCX;
751     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
752       return X86::RBX;
753     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
754       return X86::RSI;
755     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
756       return X86::RDI;
757     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
758       return X86::RBP;
759     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
760       return X86::RSP;
761     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
762       return X86::R8;
763     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
764       return X86::R9;
765     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
766       return X86::R10;
767     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
768       return X86::R11;
769     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
770       return X86::R12;
771     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
772       return X86::R13;
773     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
774       return X86::R14;
775     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
776       return X86::R15;
777     }
778   }
779 }
780 
781 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
782                                 bool High) {
783   unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
784   if (Res == 0)
785     llvm_unreachable("Unexpected register or VT");
786   return Res;
787 }
788 
789 unsigned get512BitSuperRegister(unsigned Reg) {
790   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
791     return X86::ZMM0 + (Reg - X86::XMM0);
792   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
793     return X86::ZMM0 + (Reg - X86::YMM0);
794   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
795     return Reg;
796   llvm_unreachable("Unexpected SIMD register");
797 }
798 
799 }
800