1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86AsmPrinter.h" 16 #include "X86RegisterInfo.h" 17 #include "X86ShuffleDecodeConstantPool.h" 18 #include "InstPrinter/X86ATTInstPrinter.h" 19 #include "MCTargetDesc/X86BaseInfo.h" 20 #include "Utils/X86ShuffleDecode.h" 21 #include "llvm/ADT/Optional.h" 22 #include "llvm/ADT/SmallString.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineConstantPool.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 28 #include "llvm/CodeGen/StackMaps.h" 29 #include "llvm/IR/DataLayout.h" 30 #include "llvm/IR/GlobalValue.h" 31 #include "llvm/IR/Mangler.h" 32 #include "llvm/MC/MCAsmInfo.h" 33 #include "llvm/MC/MCCodeEmitter.h" 34 #include "llvm/MC/MCContext.h" 35 #include "llvm/MC/MCExpr.h" 36 #include "llvm/MC/MCFixup.h" 37 #include "llvm/MC/MCInst.h" 38 #include "llvm/MC/MCInstBuilder.h" 39 #include "llvm/MC/MCStreamer.h" 40 #include "llvm/MC/MCSymbol.h" 41 #include "llvm/Support/TargetRegistry.h" 42 using namespace llvm; 43 44 namespace { 45 46 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 47 class X86MCInstLower { 48 MCContext &Ctx; 49 const MachineFunction &MF; 50 const TargetMachine &TM; 51 const MCAsmInfo &MAI; 52 X86AsmPrinter &AsmPrinter; 53 public: 54 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter); 55 56 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI, 57 const MachineOperand &MO) const; 58 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 59 60 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 61 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 62 63 private: 64 MachineModuleInfoMachO &getMachOMMI() const; 65 Mangler *getMang() const { 66 return AsmPrinter.Mang; 67 } 68 }; 69 70 } // end anonymous namespace 71 72 // Emit a minimal sequence of nops spanning NumBytes bytes. 73 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 74 const MCSubtargetInfo &STI); 75 76 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst, 77 const MCSubtargetInfo &STI, 78 MCCodeEmitter *CodeEmitter) { 79 if (InShadow) { 80 SmallString<256> Code; 81 SmallVector<MCFixup, 4> Fixups; 82 raw_svector_ostream VecOS(Code); 83 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI); 84 CurrentShadowSize += Code.size(); 85 if (CurrentShadowSize >= RequiredShadowSize) 86 InShadow = false; // The shadow is big enough. Stop counting. 87 } 88 } 89 90 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( 91 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) { 92 if (InShadow && CurrentShadowSize < RequiredShadowSize) { 93 InShadow = false; 94 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize, 95 MF->getSubtarget<X86Subtarget>().is64Bit(), STI); 96 } 97 } 98 99 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { 100 OutStreamer->EmitInstruction(Inst, getSubtargetInfo()); 101 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); 102 } 103 104 X86MCInstLower::X86MCInstLower(const MachineFunction &mf, 105 X86AsmPrinter &asmprinter) 106 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()), 107 AsmPrinter(asmprinter) {} 108 109 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 110 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 111 } 112 113 114 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 115 /// operand to an MCSymbol. 116 MCSymbol *X86MCInstLower:: 117 GetSymbolFromOperand(const MachineOperand &MO) const { 118 const DataLayout &DL = MF.getDataLayout(); 119 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 120 121 MCSymbol *Sym = nullptr; 122 SmallString<128> Name; 123 StringRef Suffix; 124 125 switch (MO.getTargetFlags()) { 126 case X86II::MO_DLLIMPORT: 127 // Handle dllimport linkage. 128 Name += "__imp_"; 129 break; 130 case X86II::MO_DARWIN_NONLAZY: 131 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 132 Suffix = "$non_lazy_ptr"; 133 break; 134 } 135 136 if (!Suffix.empty()) 137 Name += DL.getPrivateGlobalPrefix(); 138 139 if (MO.isGlobal()) { 140 const GlobalValue *GV = MO.getGlobal(); 141 AsmPrinter.getNameWithPrefix(Name, GV); 142 } else if (MO.isSymbol()) { 143 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); 144 } else if (MO.isMBB()) { 145 assert(Suffix.empty()); 146 Sym = MO.getMBB()->getSymbol(); 147 } 148 149 Name += Suffix; 150 if (!Sym) 151 Sym = Ctx.getOrCreateSymbol(Name); 152 153 // If the target flags on the operand changes the name of the symbol, do that 154 // before we return the symbol. 155 switch (MO.getTargetFlags()) { 156 default: break; 157 case X86II::MO_DARWIN_NONLAZY: 158 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 159 MachineModuleInfoImpl::StubValueTy &StubSym = 160 getMachOMMI().getGVStubEntry(Sym); 161 if (!StubSym.getPointer()) { 162 assert(MO.isGlobal() && "Extern symbol not handled yet"); 163 StubSym = 164 MachineModuleInfoImpl:: 165 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()), 166 !MO.getGlobal()->hasInternalLinkage()); 167 } 168 break; 169 } 170 } 171 172 return Sym; 173 } 174 175 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 176 MCSymbol *Sym) const { 177 // FIXME: We would like an efficient form for this, so we don't have to do a 178 // lot of extra uniquing. 179 const MCExpr *Expr = nullptr; 180 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 181 182 switch (MO.getTargetFlags()) { 183 default: llvm_unreachable("Unknown target flag on GV operand"); 184 case X86II::MO_NO_FLAG: // No flag. 185 // These affect the name of the symbol, not any suffix. 186 case X86II::MO_DARWIN_NONLAZY: 187 case X86II::MO_DLLIMPORT: 188 break; 189 190 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 191 case X86II::MO_TLVP_PIC_BASE: 192 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 193 // Subtract the pic base. 194 Expr = MCBinaryExpr::createSub(Expr, 195 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), 196 Ctx), 197 Ctx); 198 break; 199 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 200 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 201 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 202 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 203 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 204 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 205 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 206 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 207 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 208 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 209 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 210 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 211 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 212 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 213 case X86II::MO_PIC_BASE_OFFSET: 214 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 215 Expr = MCSymbolRefExpr::create(Sym, Ctx); 216 // Subtract the pic base. 217 Expr = MCBinaryExpr::createSub(Expr, 218 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), 219 Ctx); 220 if (MO.isJTI()) { 221 assert(MAI.doesSetDirectiveSuppressReloc()); 222 // If .set directive is supported, use it to reduce the number of 223 // relocations the assembler will generate for differences between 224 // local labels. This is only safe when the symbols are in the same 225 // section so we are restricting it to jumptable references. 226 MCSymbol *Label = Ctx.createTempSymbol(); 227 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr); 228 Expr = MCSymbolRefExpr::create(Label, Ctx); 229 } 230 break; 231 } 232 233 if (!Expr) 234 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx); 235 236 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 237 Expr = MCBinaryExpr::createAdd(Expr, 238 MCConstantExpr::create(MO.getOffset(), Ctx), 239 Ctx); 240 return MCOperand::createExpr(Expr); 241 } 242 243 244 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 245 /// a short fixed-register form. 246 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 247 unsigned ImmOp = Inst.getNumOperands() - 1; 248 assert(Inst.getOperand(0).isReg() && 249 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 250 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 251 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 252 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 253 254 // Check whether the destination register can be fixed. 255 unsigned Reg = Inst.getOperand(0).getReg(); 256 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 257 return; 258 259 // If so, rewrite the instruction. 260 MCOperand Saved = Inst.getOperand(ImmOp); 261 Inst = MCInst(); 262 Inst.setOpcode(Opcode); 263 Inst.addOperand(Saved); 264 } 265 266 /// \brief If a movsx instruction has a shorter encoding for the used register 267 /// simplify the instruction to use it instead. 268 static void SimplifyMOVSX(MCInst &Inst) { 269 unsigned NewOpcode = 0; 270 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 271 switch (Inst.getOpcode()) { 272 default: 273 llvm_unreachable("Unexpected instruction!"); 274 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 275 if (Op0 == X86::AX && Op1 == X86::AL) 276 NewOpcode = X86::CBW; 277 break; 278 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 279 if (Op0 == X86::EAX && Op1 == X86::AX) 280 NewOpcode = X86::CWDE; 281 break; 282 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 283 if (Op0 == X86::RAX && Op1 == X86::EAX) 284 NewOpcode = X86::CDQE; 285 break; 286 } 287 288 if (NewOpcode != 0) { 289 Inst = MCInst(); 290 Inst.setOpcode(NewOpcode); 291 } 292 } 293 294 /// \brief Simplify things like MOV32rm to MOV32o32a. 295 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 296 unsigned Opcode) { 297 // Don't make these simplifications in 64-bit mode; other assemblers don't 298 // perform them because they make the code larger. 299 if (Printer.getSubtarget().is64Bit()) 300 return; 301 302 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 303 unsigned AddrBase = IsStore; 304 unsigned RegOp = IsStore ? 0 : 5; 305 unsigned AddrOp = AddrBase + 3; 306 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 307 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && 308 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() && 309 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() && 310 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() && 311 (Inst.getOperand(AddrOp).isExpr() || 312 Inst.getOperand(AddrOp).isImm()) && 313 "Unexpected instruction!"); 314 315 // Check whether the destination register can be fixed. 316 unsigned Reg = Inst.getOperand(RegOp).getReg(); 317 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 318 return; 319 320 // Check whether this is an absolute address. 321 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 322 // to do this here. 323 bool Absolute = true; 324 if (Inst.getOperand(AddrOp).isExpr()) { 325 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 326 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 327 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 328 Absolute = false; 329 } 330 331 if (Absolute && 332 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || 333 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 || 334 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0)) 335 return; 336 337 // If so, rewrite the instruction. 338 MCOperand Saved = Inst.getOperand(AddrOp); 339 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg); 340 Inst = MCInst(); 341 Inst.setOpcode(Opcode); 342 Inst.addOperand(Saved); 343 Inst.addOperand(Seg); 344 } 345 346 static unsigned getRetOpcode(const X86Subtarget &Subtarget) { 347 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL; 348 } 349 350 Optional<MCOperand> 351 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI, 352 const MachineOperand &MO) const { 353 switch (MO.getType()) { 354 default: 355 MI->dump(); 356 llvm_unreachable("unknown operand type"); 357 case MachineOperand::MO_Register: 358 // Ignore all implicit register operands. 359 if (MO.isImplicit()) 360 return None; 361 return MCOperand::createReg(MO.getReg()); 362 case MachineOperand::MO_Immediate: 363 return MCOperand::createImm(MO.getImm()); 364 case MachineOperand::MO_MachineBasicBlock: 365 case MachineOperand::MO_GlobalAddress: 366 case MachineOperand::MO_ExternalSymbol: 367 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 368 case MachineOperand::MO_MCSymbol: 369 return LowerSymbolOperand(MO, MO.getMCSymbol()); 370 case MachineOperand::MO_JumpTableIndex: 371 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 372 case MachineOperand::MO_ConstantPoolIndex: 373 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 374 case MachineOperand::MO_BlockAddress: 375 return LowerSymbolOperand( 376 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 377 case MachineOperand::MO_RegisterMask: 378 // Ignore call clobbers. 379 return None; 380 } 381 } 382 383 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 384 OutMI.setOpcode(MI->getOpcode()); 385 386 for (const MachineOperand &MO : MI->operands()) 387 if (auto MaybeMCOp = LowerMachineOperand(MI, MO)) 388 OutMI.addOperand(MaybeMCOp.getValue()); 389 390 // Handle a few special cases to eliminate operand modifiers. 391 ReSimplify: 392 switch (OutMI.getOpcode()) { 393 case X86::LEA64_32r: 394 case X86::LEA64r: 395 case X86::LEA16r: 396 case X86::LEA32r: 397 // LEA should have a segment register, but it must be empty. 398 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 399 "Unexpected # of LEA operands"); 400 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 401 "LEA has segment specified!"); 402 break; 403 404 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 405 // if one of the registers is extended, but other isn't. 406 case X86::VMOVZPQILo2PQIrr: 407 case X86::VMOVAPDrr: 408 case X86::VMOVAPDYrr: 409 case X86::VMOVAPSrr: 410 case X86::VMOVAPSYrr: 411 case X86::VMOVDQArr: 412 case X86::VMOVDQAYrr: 413 case X86::VMOVDQUrr: 414 case X86::VMOVDQUYrr: 415 case X86::VMOVUPDrr: 416 case X86::VMOVUPDYrr: 417 case X86::VMOVUPSrr: 418 case X86::VMOVUPSYrr: { 419 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 420 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 421 unsigned NewOpc; 422 switch (OutMI.getOpcode()) { 423 default: llvm_unreachable("Invalid opcode"); 424 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; 425 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 426 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 427 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 428 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 429 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 430 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 431 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 432 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 433 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 434 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 435 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 436 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 437 } 438 OutMI.setOpcode(NewOpc); 439 } 440 break; 441 } 442 case X86::VMOVSDrr: 443 case X86::VMOVSSrr: { 444 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 445 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 446 unsigned NewOpc; 447 switch (OutMI.getOpcode()) { 448 default: llvm_unreachable("Invalid opcode"); 449 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 450 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 451 } 452 OutMI.setOpcode(NewOpc); 453 } 454 break; 455 } 456 457 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 458 // inputs modeled as normal uses instead of implicit uses. As such, truncate 459 // off all but the first operand (the callee). FIXME: Change isel. 460 case X86::TAILJMPr64: 461 case X86::TAILJMPr64_REX: 462 case X86::CALL64r: 463 case X86::CALL64pcrel32: { 464 unsigned Opcode = OutMI.getOpcode(); 465 MCOperand Saved = OutMI.getOperand(0); 466 OutMI = MCInst(); 467 OutMI.setOpcode(Opcode); 468 OutMI.addOperand(Saved); 469 break; 470 } 471 472 case X86::EH_RETURN: 473 case X86::EH_RETURN64: { 474 OutMI = MCInst(); 475 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 476 break; 477 } 478 479 case X86::CLEANUPRET: { 480 // Replace CATCHRET with the appropriate RET. 481 OutMI = MCInst(); 482 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget())); 483 break; 484 } 485 486 case X86::CATCHRET: { 487 // Replace CATCHRET with the appropriate RET. 488 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget(); 489 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; 490 OutMI = MCInst(); 491 OutMI.setOpcode(getRetOpcode(Subtarget)); 492 OutMI.addOperand(MCOperand::createReg(ReturnReg)); 493 break; 494 } 495 496 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. 497 case X86::TAILJMPr: 498 case X86::TAILJMPd: 499 case X86::TAILJMPd64: { 500 unsigned Opcode; 501 switch (OutMI.getOpcode()) { 502 default: llvm_unreachable("Invalid opcode"); 503 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 504 case X86::TAILJMPd: 505 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 506 } 507 508 MCOperand Saved = OutMI.getOperand(0); 509 OutMI = MCInst(); 510 OutMI.setOpcode(Opcode); 511 OutMI.addOperand(Saved); 512 break; 513 } 514 515 case X86::DEC16r: 516 case X86::DEC32r: 517 case X86::INC16r: 518 case X86::INC32r: 519 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions. 520 if (!AsmPrinter.getSubtarget().is64Bit()) { 521 unsigned Opcode; 522 switch (OutMI.getOpcode()) { 523 default: llvm_unreachable("Invalid opcode"); 524 case X86::DEC16r: Opcode = X86::DEC16r_alt; break; 525 case X86::DEC32r: Opcode = X86::DEC32r_alt; break; 526 case X86::INC16r: Opcode = X86::INC16r_alt; break; 527 case X86::INC32r: Opcode = X86::INC32r_alt; break; 528 } 529 OutMI.setOpcode(Opcode); 530 } 531 break; 532 533 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 534 // this with an ugly goto in case the resultant OR uses EAX and needs the 535 // short form. 536 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 537 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 538 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 539 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 540 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 541 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 542 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 543 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 544 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 545 546 // Atomic load and store require a separate pseudo-inst because Acquire 547 // implies mayStore and Release implies mayLoad; fix these to regular MOV 548 // instructions here 549 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 550 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 551 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 552 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 553 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 554 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 555 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 556 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 557 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify; 558 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify; 559 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify; 560 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify; 561 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify; 562 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify; 563 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify; 564 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify; 565 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify; 566 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify; 567 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify; 568 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify; 569 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify; 570 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify; 571 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify; 572 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify; 573 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify; 574 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify; 575 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify; 576 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify; 577 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify; 578 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify; 579 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify; 580 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify; 581 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify; 582 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify; 583 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify; 584 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify; 585 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify; 586 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify; 587 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify; 588 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify; 589 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify; 590 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify; 591 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify; 592 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify; 593 594 // We don't currently select the correct instruction form for instructions 595 // which have a short %eax, etc. form. Handle this by custom lowering, for 596 // now. 597 // 598 // Note, we are currently not handling the following instructions: 599 // MOV64ao8, MOV64o8a 600 // XCHG16ar, XCHG32ar, XCHG64ar 601 case X86::MOV8mr_NOREX: 602 case X86::MOV8mr: 603 case X86::MOV8rm_NOREX: 604 case X86::MOV8rm: 605 case X86::MOV16mr: 606 case X86::MOV16rm: 607 case X86::MOV32mr: 608 case X86::MOV32rm: { 609 unsigned NewOpc; 610 switch (OutMI.getOpcode()) { 611 default: llvm_unreachable("Invalid opcode"); 612 case X86::MOV8mr_NOREX: 613 case X86::MOV8mr: NewOpc = X86::MOV8o32a; break; 614 case X86::MOV8rm_NOREX: 615 case X86::MOV8rm: NewOpc = X86::MOV8ao32; break; 616 case X86::MOV16mr: NewOpc = X86::MOV16o32a; break; 617 case X86::MOV16rm: NewOpc = X86::MOV16ao32; break; 618 case X86::MOV32mr: NewOpc = X86::MOV32o32a; break; 619 case X86::MOV32rm: NewOpc = X86::MOV32ao32; break; 620 } 621 SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc); 622 break; 623 } 624 625 case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32: 626 case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32: 627 case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32: 628 case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32: 629 case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32: 630 case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32: 631 case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32: 632 case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32: 633 case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: { 634 unsigned NewOpc; 635 switch (OutMI.getOpcode()) { 636 default: llvm_unreachable("Invalid opcode"); 637 case X86::ADC8ri: NewOpc = X86::ADC8i8; break; 638 case X86::ADC16ri: NewOpc = X86::ADC16i16; break; 639 case X86::ADC32ri: NewOpc = X86::ADC32i32; break; 640 case X86::ADC64ri32: NewOpc = X86::ADC64i32; break; 641 case X86::ADD8ri: NewOpc = X86::ADD8i8; break; 642 case X86::ADD16ri: NewOpc = X86::ADD16i16; break; 643 case X86::ADD32ri: NewOpc = X86::ADD32i32; break; 644 case X86::ADD64ri32: NewOpc = X86::ADD64i32; break; 645 case X86::AND8ri: NewOpc = X86::AND8i8; break; 646 case X86::AND16ri: NewOpc = X86::AND16i16; break; 647 case X86::AND32ri: NewOpc = X86::AND32i32; break; 648 case X86::AND64ri32: NewOpc = X86::AND64i32; break; 649 case X86::CMP8ri: NewOpc = X86::CMP8i8; break; 650 case X86::CMP16ri: NewOpc = X86::CMP16i16; break; 651 case X86::CMP32ri: NewOpc = X86::CMP32i32; break; 652 case X86::CMP64ri32: NewOpc = X86::CMP64i32; break; 653 case X86::OR8ri: NewOpc = X86::OR8i8; break; 654 case X86::OR16ri: NewOpc = X86::OR16i16; break; 655 case X86::OR32ri: NewOpc = X86::OR32i32; break; 656 case X86::OR64ri32: NewOpc = X86::OR64i32; break; 657 case X86::SBB8ri: NewOpc = X86::SBB8i8; break; 658 case X86::SBB16ri: NewOpc = X86::SBB16i16; break; 659 case X86::SBB32ri: NewOpc = X86::SBB32i32; break; 660 case X86::SBB64ri32: NewOpc = X86::SBB64i32; break; 661 case X86::SUB8ri: NewOpc = X86::SUB8i8; break; 662 case X86::SUB16ri: NewOpc = X86::SUB16i16; break; 663 case X86::SUB32ri: NewOpc = X86::SUB32i32; break; 664 case X86::SUB64ri32: NewOpc = X86::SUB64i32; break; 665 case X86::TEST8ri: NewOpc = X86::TEST8i8; break; 666 case X86::TEST16ri: NewOpc = X86::TEST16i16; break; 667 case X86::TEST32ri: NewOpc = X86::TEST32i32; break; 668 case X86::TEST64ri32: NewOpc = X86::TEST64i32; break; 669 case X86::XOR8ri: NewOpc = X86::XOR8i8; break; 670 case X86::XOR16ri: NewOpc = X86::XOR16i16; break; 671 case X86::XOR32ri: NewOpc = X86::XOR32i32; break; 672 case X86::XOR64ri32: NewOpc = X86::XOR64i32; break; 673 } 674 SimplifyShortImmForm(OutMI, NewOpc); 675 break; 676 } 677 678 // Try to shrink some forms of movsx. 679 case X86::MOVSX16rr8: 680 case X86::MOVSX32rr16: 681 case X86::MOVSX64rr32: 682 SimplifyMOVSX(OutMI); 683 break; 684 } 685 } 686 687 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering, 688 const MachineInstr &MI) { 689 690 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 691 MI.getOpcode() == X86::TLS_base_addr64; 692 693 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 694 695 MCContext &context = OutStreamer->getContext(); 696 697 if (needsPadding) 698 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 699 700 MCSymbolRefExpr::VariantKind SRVK; 701 switch (MI.getOpcode()) { 702 case X86::TLS_addr32: 703 case X86::TLS_addr64: 704 SRVK = MCSymbolRefExpr::VK_TLSGD; 705 break; 706 case X86::TLS_base_addr32: 707 SRVK = MCSymbolRefExpr::VK_TLSLDM; 708 break; 709 case X86::TLS_base_addr64: 710 SRVK = MCSymbolRefExpr::VK_TLSLD; 711 break; 712 default: 713 llvm_unreachable("unexpected opcode"); 714 } 715 716 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 717 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context); 718 719 MCInst LEA; 720 if (is64Bits) { 721 LEA.setOpcode(X86::LEA64r); 722 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest 723 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base 724 LEA.addOperand(MCOperand::createImm(1)); // scale 725 LEA.addOperand(MCOperand::createReg(0)); // index 726 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 727 LEA.addOperand(MCOperand::createReg(0)); // seg 728 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 729 LEA.setOpcode(X86::LEA32r); 730 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 731 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base 732 LEA.addOperand(MCOperand::createImm(1)); // scale 733 LEA.addOperand(MCOperand::createReg(0)); // index 734 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 735 LEA.addOperand(MCOperand::createReg(0)); // seg 736 } else { 737 LEA.setOpcode(X86::LEA32r); 738 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest 739 LEA.addOperand(MCOperand::createReg(0)); // base 740 LEA.addOperand(MCOperand::createImm(1)); // scale 741 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index 742 LEA.addOperand(MCOperand::createExpr(symRef)); // disp 743 LEA.addOperand(MCOperand::createReg(0)); // seg 744 } 745 EmitAndCountInstruction(LEA); 746 747 if (needsPadding) { 748 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 749 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 750 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX)); 751 } 752 753 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 754 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name); 755 const MCSymbolRefExpr *tlsRef = 756 MCSymbolRefExpr::create(tlsGetAddr, 757 MCSymbolRefExpr::VK_PLT, 758 context); 759 760 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 761 : X86::CALLpcrel32) 762 .addExpr(tlsRef)); 763 } 764 765 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes 766 /// bytes. Return the size of nop emitted. 767 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 768 const MCSubtargetInfo &STI) { 769 // This works only for 64bit. For 32bit we have to do additional checking if 770 // the CPU supports multi-byte nops. 771 assert(Is64Bit && "EmitNops only supports X86-64"); 772 773 unsigned NopSize; 774 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; 775 Opc = IndexReg = Displacement = SegmentReg = 0; 776 BaseReg = X86::RAX; 777 ScaleVal = 1; 778 switch (NumBytes) { 779 case 0: llvm_unreachable("Zero nops?"); break; 780 case 1: NopSize = 1; Opc = X86::NOOP; break; 781 case 2: NopSize = 2; Opc = X86::XCHG16ar; break; 782 case 3: NopSize = 3; Opc = X86::NOOPL; break; 783 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break; 784 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8; 785 IndexReg = X86::RAX; break; 786 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8; 787 IndexReg = X86::RAX; break; 788 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break; 789 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512; 790 IndexReg = X86::RAX; break; 791 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512; 792 IndexReg = X86::RAX; break; 793 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512; 794 IndexReg = X86::RAX; SegmentReg = X86::CS; break; 795 } 796 797 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U); 798 NopSize += NumPrefixes; 799 for (unsigned i = 0; i != NumPrefixes; ++i) 800 OS.EmitBytes("\x66"); 801 802 switch (Opc) { 803 default: 804 llvm_unreachable("Unexpected opcode"); 805 break; 806 case X86::NOOP: 807 OS.EmitInstruction(MCInstBuilder(Opc), STI); 808 break; 809 case X86::XCHG16ar: 810 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI); 811 break; 812 case X86::NOOPL: 813 case X86::NOOPW: 814 OS.EmitInstruction(MCInstBuilder(Opc) 815 .addReg(BaseReg) 816 .addImm(ScaleVal) 817 .addReg(IndexReg) 818 .addImm(Displacement) 819 .addReg(SegmentReg), 820 STI); 821 break; 822 } 823 assert(NopSize <= NumBytes && "We overemitted?"); 824 return NopSize; 825 } 826 827 /// \brief Emit the optimal amount of multi-byte nops on X86. 828 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, 829 const MCSubtargetInfo &STI) { 830 unsigned NopsToEmit = NumBytes; 831 (void)NopsToEmit; 832 while (NumBytes) { 833 NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI); 834 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!"); 835 } 836 } 837 838 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, 839 X86MCInstLower &MCIL) { 840 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64"); 841 842 StatepointOpers SOpers(&MI); 843 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { 844 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(), 845 getSubtargetInfo()); 846 } else { 847 // Lower call target and choose correct opcode 848 const MachineOperand &CallTarget = SOpers.getCallTarget(); 849 MCOperand CallTargetMCOp; 850 unsigned CallOpcode; 851 switch (CallTarget.getType()) { 852 case MachineOperand::MO_GlobalAddress: 853 case MachineOperand::MO_ExternalSymbol: 854 CallTargetMCOp = MCIL.LowerSymbolOperand( 855 CallTarget, MCIL.GetSymbolFromOperand(CallTarget)); 856 CallOpcode = X86::CALL64pcrel32; 857 // Currently, we only support relative addressing with statepoints. 858 // Otherwise, we'll need a scratch register to hold the target 859 // address. You'll fail asserts during load & relocation if this 860 // symbol is to far away. (TODO: support non-relative addressing) 861 break; 862 case MachineOperand::MO_Immediate: 863 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); 864 CallOpcode = X86::CALL64pcrel32; 865 // Currently, we only support relative addressing with statepoints. 866 // Otherwise, we'll need a scratch register to hold the target 867 // immediate. You'll fail asserts during load & relocation if this 868 // address is to far away. (TODO: support non-relative addressing) 869 break; 870 case MachineOperand::MO_Register: 871 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); 872 CallOpcode = X86::CALL64r; 873 break; 874 default: 875 llvm_unreachable("Unsupported operand type in statepoint call target"); 876 break; 877 } 878 879 // Emit call 880 MCInst CallInst; 881 CallInst.setOpcode(CallOpcode); 882 CallInst.addOperand(CallTargetMCOp); 883 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo()); 884 } 885 886 // Record our statepoint node in the same section used by STACKMAP 887 // and PATCHPOINT 888 SM.recordStatepoint(MI); 889 } 890 891 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI, 892 X86MCInstLower &MCIL) { 893 // FAULTING_LOAD_OP <def>, <MBB handler>, <load opcode>, <load operands> 894 895 unsigned LoadDefRegister = MI.getOperand(0).getReg(); 896 MCSymbol *HandlerLabel = MI.getOperand(1).getMBB()->getSymbol(); 897 unsigned LoadOpcode = MI.getOperand(2).getImm(); 898 unsigned LoadOperandsBeginIdx = 3; 899 900 FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel); 901 902 MCInst LoadMI; 903 LoadMI.setOpcode(LoadOpcode); 904 905 if (LoadDefRegister != X86::NoRegister) 906 LoadMI.addOperand(MCOperand::createReg(LoadDefRegister)); 907 908 for (auto I = MI.operands_begin() + LoadOperandsBeginIdx, 909 E = MI.operands_end(); 910 I != E; ++I) 911 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I)) 912 LoadMI.addOperand(MaybeOperand.getValue()); 913 914 OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo()); 915 } 916 917 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, 918 X86MCInstLower &MCIL) { 919 // PATCHABLE_OP minsize, opcode, operands 920 921 unsigned MinSize = MI.getOperand(0).getImm(); 922 unsigned Opcode = MI.getOperand(1).getImm(); 923 924 MCInst MCI; 925 MCI.setOpcode(Opcode); 926 for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end())) 927 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) 928 MCI.addOperand(MaybeOperand.getValue()); 929 930 SmallString<256> Code; 931 SmallVector<MCFixup, 4> Fixups; 932 raw_svector_ostream VecOS(Code); 933 CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo()); 934 935 if (Code.size() < MinSize) { 936 if (MinSize == 2 && Opcode == X86::PUSH64r) { 937 // This is an optimization that lets us get away without emitting a nop in 938 // many cases. 939 // 940 // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two 941 // bytes too, so the check on MinSize is important. 942 MCI.setOpcode(X86::PUSH64rmr); 943 } else { 944 unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(), 945 getSubtargetInfo()); 946 assert(NopSize == MinSize && "Could not implement MinSize!"); 947 (void) NopSize; 948 } 949 } 950 951 OutStreamer->EmitInstruction(MCI, getSubtargetInfo()); 952 } 953 954 // Lower a stackmap of the form: 955 // <id>, <shadowBytes>, ... 956 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 957 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 958 SM.recordStackMap(MI); 959 unsigned NumShadowBytes = MI.getOperand(1).getImm(); 960 SMShadowTracker.reset(NumShadowBytes); 961 } 962 963 // Lower a patchpoint of the form: 964 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ... 965 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 966 X86MCInstLower &MCIL) { 967 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64"); 968 969 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 970 971 SM.recordPatchPoint(MI); 972 973 PatchPointOpers opers(&MI); 974 unsigned ScratchIdx = opers.getNextScratchIdx(); 975 unsigned EncodedBytes = 0; 976 const MachineOperand &CalleeMO = 977 opers.getMetaOper(PatchPointOpers::TargetPos); 978 979 // Check for null target. If target is non-null (i.e. is non-zero or is 980 // symbolic) then emit a call. 981 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) { 982 MCOperand CalleeMCOp; 983 switch (CalleeMO.getType()) { 984 default: 985 /// FIXME: Add a verifier check for bad callee types. 986 llvm_unreachable("Unrecognized callee operand type."); 987 case MachineOperand::MO_Immediate: 988 if (CalleeMO.getImm()) 989 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm()); 990 break; 991 case MachineOperand::MO_ExternalSymbol: 992 case MachineOperand::MO_GlobalAddress: 993 CalleeMCOp = 994 MCIL.LowerSymbolOperand(CalleeMO, 995 MCIL.GetSymbolFromOperand(CalleeMO)); 996 break; 997 } 998 999 // Emit MOV to materialize the target address and the CALL to target. 1000 // This is encoded with 12-13 bytes, depending on which register is used. 1001 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg(); 1002 if (X86II::isX86_64ExtendedReg(ScratchReg)) 1003 EncodedBytes = 13; 1004 else 1005 EncodedBytes = 12; 1006 1007 EmitAndCountInstruction( 1008 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1009 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1010 } 1011 1012 // Emit padding. 1013 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm(); 1014 assert(NumBytes >= EncodedBytes && 1015 "Patchpoint can't request size less than the length of a call."); 1016 1017 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(), 1018 getSubtargetInfo()); 1019 } 1020 1021 // Returns instruction preceding MBBI in MachineFunction. 1022 // If MBBI is the first instruction of the first basic block, returns null. 1023 static MachineBasicBlock::const_iterator 1024 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) { 1025 const MachineBasicBlock *MBB = MBBI->getParent(); 1026 while (MBBI == MBB->begin()) { 1027 if (MBB == &MBB->getParent()->front()) 1028 return nullptr; 1029 MBB = MBB->getPrevNode(); 1030 MBBI = MBB->end(); 1031 } 1032 return --MBBI; 1033 } 1034 1035 static const Constant *getConstantFromPool(const MachineInstr &MI, 1036 const MachineOperand &Op) { 1037 if (!Op.isCPI()) 1038 return nullptr; 1039 1040 ArrayRef<MachineConstantPoolEntry> Constants = 1041 MI.getParent()->getParent()->getConstantPool()->getConstants(); 1042 const MachineConstantPoolEntry &ConstantEntry = 1043 Constants[Op.getIndex()]; 1044 1045 // Bail if this is a machine constant pool entry, we won't be able to dig out 1046 // anything useful. 1047 if (ConstantEntry.isMachineConstantPoolEntry()) 1048 return nullptr; 1049 1050 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal); 1051 assert((!C || ConstantEntry.getType() == C->getType()) && 1052 "Expected a constant of the same type!"); 1053 return C; 1054 } 1055 1056 static std::string getShuffleComment(const MachineOperand &DstOp, 1057 const MachineOperand &SrcOp1, 1058 const MachineOperand &SrcOp2, 1059 ArrayRef<int> Mask) { 1060 std::string Comment; 1061 1062 // Compute the name for a register. This is really goofy because we have 1063 // multiple instruction printers that could (in theory) use different 1064 // names. Fortunately most people use the ATT style (outside of Windows) 1065 // and they actually agree on register naming here. Ultimately, this is 1066 // a comment, and so its OK if it isn't perfect. 1067 auto GetRegisterName = [](unsigned RegNum) -> StringRef { 1068 return X86ATTInstPrinter::getRegisterName(RegNum); 1069 }; 1070 1071 // TODO: Add support for specifying an AVX512 style mask register in the comment. 1072 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem"; 1073 StringRef Src1Name = 1074 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem"; 1075 StringRef Src2Name = 1076 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; 1077 1078 // One source operand, fix the mask to print all elements in one span. 1079 SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end()); 1080 if (Src1Name == Src2Name) 1081 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) 1082 if (ShuffleMask[i] >= e) 1083 ShuffleMask[i] -= e; 1084 1085 raw_string_ostream CS(Comment); 1086 CS << DstName << " = "; 1087 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) { 1088 if (i != 0) 1089 CS << ","; 1090 if (ShuffleMask[i] == SM_SentinelZero) { 1091 CS << "zero"; 1092 continue; 1093 } 1094 1095 // Otherwise, it must come from src1 or src2. Print the span of elements 1096 // that comes from this src. 1097 bool isSrc1 = ShuffleMask[i] < (int)e; 1098 CS << (isSrc1 ? Src1Name : Src2Name) << '['; 1099 1100 bool IsFirst = true; 1101 while (i != e && ShuffleMask[i] != SM_SentinelZero && 1102 (ShuffleMask[i] < (int)e) == isSrc1) { 1103 if (!IsFirst) 1104 CS << ','; 1105 else 1106 IsFirst = false; 1107 if (ShuffleMask[i] == SM_SentinelUndef) 1108 CS << "u"; 1109 else 1110 CS << ShuffleMask[i] % (int)e; 1111 ++i; 1112 } 1113 CS << ']'; 1114 --i; // For loop increments element #. 1115 } 1116 CS.flush(); 1117 1118 return Comment; 1119 } 1120 1121 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 1122 X86MCInstLower MCInstLowering(*MF, *this); 1123 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo(); 1124 1125 switch (MI->getOpcode()) { 1126 case TargetOpcode::DBG_VALUE: 1127 llvm_unreachable("Should be handled target independently"); 1128 1129 // Emit nothing here but a comment if we can. 1130 case X86::Int_MemBarrier: 1131 OutStreamer->emitRawComment("MEMBARRIER"); 1132 return; 1133 1134 1135 case X86::EH_RETURN: 1136 case X86::EH_RETURN64: { 1137 // Lower these as normal, but add some comments. 1138 unsigned Reg = MI->getOperand(0).getReg(); 1139 OutStreamer->AddComment(StringRef("eh_return, addr: %") + 1140 X86ATTInstPrinter::getRegisterName(Reg)); 1141 break; 1142 } 1143 case X86::CLEANUPRET: { 1144 // Lower these as normal, but add some comments. 1145 OutStreamer->AddComment("CLEANUPRET"); 1146 break; 1147 } 1148 1149 case X86::CATCHRET: { 1150 // Lower these as normal, but add some comments. 1151 OutStreamer->AddComment("CATCHRET"); 1152 break; 1153 } 1154 1155 case X86::TAILJMPr: 1156 case X86::TAILJMPm: 1157 case X86::TAILJMPd: 1158 case X86::TAILJMPr64: 1159 case X86::TAILJMPm64: 1160 case X86::TAILJMPd64: 1161 case X86::TAILJMPr64_REX: 1162 case X86::TAILJMPm64_REX: 1163 case X86::TAILJMPd64_REX: 1164 // Lower these as normal, but add some comments. 1165 OutStreamer->AddComment("TAILCALL"); 1166 break; 1167 1168 case X86::TLS_addr32: 1169 case X86::TLS_addr64: 1170 case X86::TLS_base_addr32: 1171 case X86::TLS_base_addr64: 1172 return LowerTlsAddr(MCInstLowering, *MI); 1173 1174 case X86::MOVPC32r: { 1175 // This is a pseudo op for a two instruction sequence with a label, which 1176 // looks like: 1177 // call "L1$pb" 1178 // "L1$pb": 1179 // popl %esi 1180 1181 // Emit the call. 1182 MCSymbol *PICBase = MF->getPICBaseSymbol(); 1183 // FIXME: We would like an efficient form for this, so we don't have to do a 1184 // lot of extra uniquing. 1185 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32) 1186 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext))); 1187 1188 const X86FrameLowering* FrameLowering = 1189 MF->getSubtarget<X86Subtarget>().getFrameLowering(); 1190 bool hasFP = FrameLowering->hasFP(*MF); 1191 1192 // TODO: This is needed only if we require precise CFA. 1193 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() && 1194 !OutStreamer->getDwarfFrameInfos().back().End; 1195 1196 int stackGrowth = -RI->getSlotSize(); 1197 1198 if (HasActiveDwarfFrame && !hasFP) { 1199 OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth); 1200 } 1201 1202 // Emit the label. 1203 OutStreamer->EmitLabel(PICBase); 1204 1205 // popl $reg 1206 EmitAndCountInstruction(MCInstBuilder(X86::POP32r) 1207 .addReg(MI->getOperand(0).getReg())); 1208 1209 if (HasActiveDwarfFrame && !hasFP) { 1210 OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth); 1211 } 1212 return; 1213 } 1214 1215 case X86::ADD32ri: { 1216 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 1217 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 1218 break; 1219 1220 // Okay, we have something like: 1221 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 1222 1223 // For this, we want to print something like: 1224 // MYGLOBAL + (. - PICBASE) 1225 // However, we can't generate a ".", so just emit a new label here and refer 1226 // to it. 1227 MCSymbol *DotSym = OutContext.createTempSymbol(); 1228 OutStreamer->EmitLabel(DotSym); 1229 1230 // Now that we have emitted the label, lower the complex operand expression. 1231 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 1232 1233 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext); 1234 const MCExpr *PICBase = 1235 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext); 1236 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext); 1237 1238 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext), 1239 DotExpr, OutContext); 1240 1241 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri) 1242 .addReg(MI->getOperand(0).getReg()) 1243 .addReg(MI->getOperand(1).getReg()) 1244 .addExpr(DotExpr)); 1245 return; 1246 } 1247 case TargetOpcode::STATEPOINT: 1248 return LowerSTATEPOINT(*MI, MCInstLowering); 1249 1250 case TargetOpcode::FAULTING_LOAD_OP: 1251 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering); 1252 1253 case TargetOpcode::PATCHABLE_OP: 1254 return LowerPATCHABLE_OP(*MI, MCInstLowering); 1255 1256 case TargetOpcode::STACKMAP: 1257 return LowerSTACKMAP(*MI); 1258 1259 case TargetOpcode::PATCHPOINT: 1260 return LowerPATCHPOINT(*MI, MCInstLowering); 1261 1262 case X86::MORESTACK_RET: 1263 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1264 return; 1265 1266 case X86::MORESTACK_RET_RESTORE_R10: 1267 // Return, then restore R10. 1268 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget))); 1269 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr) 1270 .addReg(X86::R10) 1271 .addReg(X86::RAX)); 1272 return; 1273 1274 case X86::SEH_PushReg: 1275 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm())); 1276 return; 1277 1278 case X86::SEH_SaveReg: 1279 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1280 MI->getOperand(1).getImm()); 1281 return; 1282 1283 case X86::SEH_SaveXMM: 1284 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1285 MI->getOperand(1).getImm()); 1286 return; 1287 1288 case X86::SEH_StackAlloc: 1289 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm()); 1290 return; 1291 1292 case X86::SEH_SetFrame: 1293 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()), 1294 MI->getOperand(1).getImm()); 1295 return; 1296 1297 case X86::SEH_PushFrame: 1298 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm()); 1299 return; 1300 1301 case X86::SEH_EndPrologue: 1302 OutStreamer->EmitWinCFIEndProlog(); 1303 return; 1304 1305 case X86::SEH_Epilogue: { 1306 MachineBasicBlock::const_iterator MBBI(MI); 1307 // Check if preceded by a call and emit nop if so. 1308 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) { 1309 // Conservatively assume that pseudo instructions don't emit code and keep 1310 // looking for a call. We may emit an unnecessary nop in some cases. 1311 if (!MBBI->isPseudo()) { 1312 if (MBBI->isCall()) 1313 EmitAndCountInstruction(MCInstBuilder(X86::NOOP)); 1314 break; 1315 } 1316 } 1317 return; 1318 } 1319 1320 // Lower PSHUFB and VPERMILP normally but add a comment if we can find 1321 // a constant shuffle mask. We won't be able to do this at the MC layer 1322 // because the mask isn't an immediate. 1323 case X86::PSHUFBrm: 1324 case X86::VPSHUFBrm: 1325 case X86::VPSHUFBYrm: 1326 case X86::VPSHUFBZ128rm: 1327 case X86::VPSHUFBZ128rmk: 1328 case X86::VPSHUFBZ128rmkz: 1329 case X86::VPSHUFBZ256rm: 1330 case X86::VPSHUFBZ256rmk: 1331 case X86::VPSHUFBZ256rmkz: 1332 case X86::VPSHUFBZrm: 1333 case X86::VPSHUFBZrmk: 1334 case X86::VPSHUFBZrmkz: { 1335 if (!OutStreamer->isVerboseAsm()) 1336 break; 1337 unsigned SrcIdx, MaskIdx; 1338 switch (MI->getOpcode()) { 1339 default: llvm_unreachable("Invalid opcode"); 1340 case X86::PSHUFBrm: 1341 case X86::VPSHUFBrm: 1342 case X86::VPSHUFBYrm: 1343 case X86::VPSHUFBZ128rm: 1344 case X86::VPSHUFBZ256rm: 1345 case X86::VPSHUFBZrm: 1346 SrcIdx = 1; MaskIdx = 5; break; 1347 case X86::VPSHUFBZ128rmkz: 1348 case X86::VPSHUFBZ256rmkz: 1349 case X86::VPSHUFBZrmkz: 1350 SrcIdx = 2; MaskIdx = 6; break; 1351 case X86::VPSHUFBZ128rmk: 1352 case X86::VPSHUFBZ256rmk: 1353 case X86::VPSHUFBZrmk: 1354 SrcIdx = 3; MaskIdx = 7; break; 1355 } 1356 1357 assert(MI->getNumOperands() >= 6 && 1358 "We should always have at least 6 operands!"); 1359 const MachineOperand &DstOp = MI->getOperand(0); 1360 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); 1361 const MachineOperand &MaskOp = MI->getOperand(MaskIdx); 1362 1363 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1364 SmallVector<int, 16> Mask; 1365 DecodePSHUFBMask(C, Mask); 1366 if (!Mask.empty()) 1367 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); 1368 } 1369 break; 1370 } 1371 case X86::VPERMILPSrm: 1372 case X86::VPERMILPDrm: 1373 case X86::VPERMILPSYrm: 1374 case X86::VPERMILPDYrm: { 1375 if (!OutStreamer->isVerboseAsm()) 1376 break; 1377 assert(MI->getNumOperands() > 5 && 1378 "We should always have at least 5 operands!"); 1379 const MachineOperand &DstOp = MI->getOperand(0); 1380 const MachineOperand &SrcOp = MI->getOperand(1); 1381 const MachineOperand &MaskOp = MI->getOperand(5); 1382 1383 unsigned ElSize; 1384 switch (MI->getOpcode()) { 1385 default: llvm_unreachable("Invalid opcode"); 1386 case X86::VPERMILPSrm: case X86::VPERMILPSYrm: ElSize = 32; break; 1387 case X86::VPERMILPDrm: case X86::VPERMILPDYrm: ElSize = 64; break; 1388 } 1389 1390 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1391 SmallVector<int, 16> Mask; 1392 DecodeVPERMILPMask(C, ElSize, Mask); 1393 if (!Mask.empty()) 1394 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask)); 1395 } 1396 break; 1397 } 1398 1399 case X86::VPERMIL2PDrm: 1400 case X86::VPERMIL2PSrm: 1401 case X86::VPERMIL2PDrmY: 1402 case X86::VPERMIL2PSrmY: { 1403 if (!OutStreamer->isVerboseAsm()) 1404 break; 1405 assert(MI->getNumOperands() > 7 && 1406 "We should always have at least 7 operands!"); 1407 const MachineOperand &DstOp = MI->getOperand(0); 1408 const MachineOperand &SrcOp1 = MI->getOperand(1); 1409 const MachineOperand &SrcOp2 = MI->getOperand(2); 1410 const MachineOperand &MaskOp = MI->getOperand(6); 1411 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1); 1412 1413 if (!CtrlOp.isImm()) 1414 break; 1415 1416 unsigned ElSize; 1417 switch (MI->getOpcode()) { 1418 default: llvm_unreachable("Invalid opcode"); 1419 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break; 1420 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break; 1421 } 1422 1423 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1424 SmallVector<int, 16> Mask; 1425 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask); 1426 if (!Mask.empty()) 1427 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); 1428 } 1429 break; 1430 } 1431 1432 case X86::VPPERMrrm: { 1433 if (!OutStreamer->isVerboseAsm()) 1434 break; 1435 assert(MI->getNumOperands() > 6 && 1436 "We should always have at least 6 operands!"); 1437 const MachineOperand &DstOp = MI->getOperand(0); 1438 const MachineOperand &SrcOp1 = MI->getOperand(1); 1439 const MachineOperand &SrcOp2 = MI->getOperand(2); 1440 const MachineOperand &MaskOp = MI->getOperand(6); 1441 1442 if (auto *C = getConstantFromPool(*MI, MaskOp)) { 1443 SmallVector<int, 16> Mask; 1444 DecodeVPPERMMask(C, Mask); 1445 if (!Mask.empty()) 1446 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); 1447 } 1448 break; 1449 } 1450 1451 #define MOV_CASE(Prefix, Suffix) \ 1452 case X86::Prefix##MOVAPD##Suffix##rm: \ 1453 case X86::Prefix##MOVAPS##Suffix##rm: \ 1454 case X86::Prefix##MOVUPD##Suffix##rm: \ 1455 case X86::Prefix##MOVUPS##Suffix##rm: \ 1456 case X86::Prefix##MOVDQA##Suffix##rm: \ 1457 case X86::Prefix##MOVDQU##Suffix##rm: 1458 1459 #define MOV_AVX512_CASE(Suffix) \ 1460 case X86::VMOVDQA64##Suffix##rm: \ 1461 case X86::VMOVDQA32##Suffix##rm: \ 1462 case X86::VMOVDQU64##Suffix##rm: \ 1463 case X86::VMOVDQU32##Suffix##rm: \ 1464 case X86::VMOVDQU16##Suffix##rm: \ 1465 case X86::VMOVDQU8##Suffix##rm: \ 1466 case X86::VMOVAPS##Suffix##rm: \ 1467 case X86::VMOVAPD##Suffix##rm: \ 1468 case X86::VMOVUPS##Suffix##rm: \ 1469 case X86::VMOVUPD##Suffix##rm: 1470 1471 #define CASE_ALL_MOV_RM() \ 1472 MOV_CASE(, ) /* SSE */ \ 1473 MOV_CASE(V, ) /* AVX-128 */ \ 1474 MOV_CASE(V, Y) /* AVX-256 */ \ 1475 MOV_AVX512_CASE(Z) \ 1476 MOV_AVX512_CASE(Z256) \ 1477 MOV_AVX512_CASE(Z128) 1478 1479 // For loads from a constant pool to a vector register, print the constant 1480 // loaded. 1481 CASE_ALL_MOV_RM() 1482 if (!OutStreamer->isVerboseAsm()) 1483 break; 1484 if (MI->getNumOperands() > 4) 1485 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) { 1486 std::string Comment; 1487 raw_string_ostream CS(Comment); 1488 const MachineOperand &DstOp = MI->getOperand(0); 1489 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = "; 1490 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) { 1491 CS << "["; 1492 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) { 1493 if (i != 0) 1494 CS << ","; 1495 if (CDS->getElementType()->isIntegerTy()) 1496 CS << CDS->getElementAsInteger(i); 1497 else if (CDS->getElementType()->isFloatTy()) 1498 CS << CDS->getElementAsFloat(i); 1499 else if (CDS->getElementType()->isDoubleTy()) 1500 CS << CDS->getElementAsDouble(i); 1501 else 1502 CS << "?"; 1503 } 1504 CS << "]"; 1505 OutStreamer->AddComment(CS.str()); 1506 } else if (auto *CV = dyn_cast<ConstantVector>(C)) { 1507 CS << "<"; 1508 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) { 1509 if (i != 0) 1510 CS << ","; 1511 Constant *COp = CV->getOperand(i); 1512 if (isa<UndefValue>(COp)) { 1513 CS << "u"; 1514 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) { 1515 if (CI->getBitWidth() <= 64) { 1516 CS << CI->getZExtValue(); 1517 } else { 1518 // print multi-word constant as (w0,w1) 1519 const auto &Val = CI->getValue(); 1520 CS << "("; 1521 for (int i = 0, N = Val.getNumWords(); i < N; ++i) { 1522 if (i > 0) 1523 CS << ","; 1524 CS << Val.getRawData()[i]; 1525 } 1526 CS << ")"; 1527 } 1528 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) { 1529 SmallString<32> Str; 1530 CF->getValueAPF().toString(Str); 1531 CS << Str; 1532 } else { 1533 CS << "?"; 1534 } 1535 } 1536 CS << ">"; 1537 OutStreamer->AddComment(CS.str()); 1538 } 1539 } 1540 break; 1541 } 1542 1543 MCInst TmpInst; 1544 MCInstLowering.Lower(MI, TmpInst); 1545 1546 // Stackmap shadows cannot include branch targets, so we can count the bytes 1547 // in a call towards the shadow, but must ensure that the no thread returns 1548 // in to the stackmap shadow. The only way to achieve this is if the call 1549 // is at the end of the shadow. 1550 if (MI->isCall()) { 1551 // Count then size of the call towards the shadow 1552 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get()); 1553 // Then flush the shadow so that we fill with nops before the call, not 1554 // after it. 1555 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); 1556 // Then emit the call 1557 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo()); 1558 return; 1559 } 1560 1561 EmitAndCountInstruction(TmpInst); 1562 } 1563