1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 using namespace llvm;
39 
40 namespace {
41 
42 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
43 class X86MCInstLower {
44   MCContext &Ctx;
45   const MachineFunction &MF;
46   const TargetMachine &TM;
47   const MCAsmInfo &MAI;
48   X86AsmPrinter &AsmPrinter;
49 public:
50   X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
51 
52   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
53 
54   MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
55   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
56 
57 private:
58   MachineModuleInfoMachO &getMachOMMI() const;
59   Mangler *getMang() const {
60     return AsmPrinter.Mang;
61   }
62 };
63 
64 } // end anonymous namespace
65 
66 // Emit a minimal sequence of nops spanning NumBytes bytes.
67 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
68                      const MCSubtargetInfo &STI);
69 
70 namespace llvm {
71    X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
72      : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
73 
74   X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
75 
76   void
77   X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &MF) {
78     CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
79         *TM.getSubtargetImpl()->getInstrInfo(),
80         *TM.getSubtargetImpl()->getRegisterInfo(), *TM.getSubtargetImpl(),
81         MF.getContext()));
82   }
83 
84   void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
85                                                    const MCSubtargetInfo &STI) {
86     if (InShadow) {
87       SmallString<256> Code;
88       SmallVector<MCFixup, 4> Fixups;
89       raw_svector_ostream VecOS(Code);
90       CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
91       VecOS.flush();
92       CurrentShadowSize += Code.size();
93       if (CurrentShadowSize >= RequiredShadowSize)
94         InShadow = false; // The shadow is big enough. Stop counting.
95     }
96   }
97 
98   void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
99     MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
100     if (InShadow && CurrentShadowSize < RequiredShadowSize) {
101       InShadow = false;
102       EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
103                TM.getSubtarget<X86Subtarget>().is64Bit(), STI);
104     }
105   }
106 
107   void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
108     OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
109     SMShadowTracker.count(Inst, getSubtargetInfo());
110   }
111 } // end llvm namespace
112 
113 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
114                                X86AsmPrinter &asmprinter)
115 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
116   MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
117 
118 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
119   return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
120 }
121 
122 
123 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
124 /// operand to an MCSymbol.
125 MCSymbol *X86MCInstLower::
126 GetSymbolFromOperand(const MachineOperand &MO) const {
127   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
128   assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
129 
130   SmallString<128> Name;
131   StringRef Suffix;
132 
133   switch (MO.getTargetFlags()) {
134   case X86II::MO_DLLIMPORT:
135     // Handle dllimport linkage.
136     Name += "__imp_";
137     break;
138   case X86II::MO_DARWIN_STUB:
139     Suffix = "$stub";
140     break;
141   case X86II::MO_DARWIN_NONLAZY:
142   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
143   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
144     Suffix = "$non_lazy_ptr";
145     break;
146   }
147 
148   if (!Suffix.empty())
149     Name += DL->getPrivateGlobalPrefix();
150 
151   unsigned PrefixLen = Name.size();
152 
153   if (MO.isGlobal()) {
154     const GlobalValue *GV = MO.getGlobal();
155     AsmPrinter.getNameWithPrefix(Name, GV);
156   } else if (MO.isSymbol()) {
157     getMang()->getNameWithPrefix(Name, MO.getSymbolName());
158   } else if (MO.isMBB()) {
159     Name += MO.getMBB()->getSymbol()->getName();
160   }
161   unsigned OrigLen = Name.size() - PrefixLen;
162 
163   Name += Suffix;
164   MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
165 
166   StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
167 
168   // If the target flags on the operand changes the name of the symbol, do that
169   // before we return the symbol.
170   switch (MO.getTargetFlags()) {
171   default: break;
172   case X86II::MO_DARWIN_NONLAZY:
173   case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
174     MachineModuleInfoImpl::StubValueTy &StubSym =
175       getMachOMMI().getGVStubEntry(Sym);
176     if (!StubSym.getPointer()) {
177       assert(MO.isGlobal() && "Extern symbol not handled yet");
178       StubSym =
179         MachineModuleInfoImpl::
180         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
181                     !MO.getGlobal()->hasInternalLinkage());
182     }
183     break;
184   }
185   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
186     MachineModuleInfoImpl::StubValueTy &StubSym =
187       getMachOMMI().getHiddenGVStubEntry(Sym);
188     if (!StubSym.getPointer()) {
189       assert(MO.isGlobal() && "Extern symbol not handled yet");
190       StubSym =
191         MachineModuleInfoImpl::
192         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
193                     !MO.getGlobal()->hasInternalLinkage());
194     }
195     break;
196   }
197   case X86II::MO_DARWIN_STUB: {
198     MachineModuleInfoImpl::StubValueTy &StubSym =
199       getMachOMMI().getFnStubEntry(Sym);
200     if (StubSym.getPointer())
201       return Sym;
202 
203     if (MO.isGlobal()) {
204       StubSym =
205         MachineModuleInfoImpl::
206         StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
207                     !MO.getGlobal()->hasInternalLinkage());
208     } else {
209       StubSym =
210         MachineModuleInfoImpl::
211         StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
212     }
213     break;
214   }
215   }
216 
217   return Sym;
218 }
219 
220 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
221                                              MCSymbol *Sym) const {
222   // FIXME: We would like an efficient form for this, so we don't have to do a
223   // lot of extra uniquing.
224   const MCExpr *Expr = nullptr;
225   MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
226 
227   switch (MO.getTargetFlags()) {
228   default: llvm_unreachable("Unknown target flag on GV operand");
229   case X86II::MO_NO_FLAG:    // No flag.
230   // These affect the name of the symbol, not any suffix.
231   case X86II::MO_DARWIN_NONLAZY:
232   case X86II::MO_DLLIMPORT:
233   case X86II::MO_DARWIN_STUB:
234     break;
235 
236   case X86II::MO_TLVP:      RefKind = MCSymbolRefExpr::VK_TLVP; break;
237   case X86II::MO_TLVP_PIC_BASE:
238     Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
239     // Subtract the pic base.
240     Expr = MCBinaryExpr::CreateSub(Expr,
241                                   MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
242                                                            Ctx),
243                                    Ctx);
244     break;
245   case X86II::MO_SECREL:    RefKind = MCSymbolRefExpr::VK_SECREL; break;
246   case X86II::MO_TLSGD:     RefKind = MCSymbolRefExpr::VK_TLSGD; break;
247   case X86II::MO_TLSLD:     RefKind = MCSymbolRefExpr::VK_TLSLD; break;
248   case X86II::MO_TLSLDM:    RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
249   case X86II::MO_GOTTPOFF:  RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
250   case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
251   case X86II::MO_TPOFF:     RefKind = MCSymbolRefExpr::VK_TPOFF; break;
252   case X86II::MO_DTPOFF:    RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
253   case X86II::MO_NTPOFF:    RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
254   case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
255   case X86II::MO_GOTPCREL:  RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
256   case X86II::MO_GOT:       RefKind = MCSymbolRefExpr::VK_GOT; break;
257   case X86II::MO_GOTOFF:    RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
258   case X86II::MO_PLT:       RefKind = MCSymbolRefExpr::VK_PLT; break;
259   case X86II::MO_PIC_BASE_OFFSET:
260   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
261   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
262     Expr = MCSymbolRefExpr::Create(Sym, Ctx);
263     // Subtract the pic base.
264     Expr = MCBinaryExpr::CreateSub(Expr,
265                             MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
266                                    Ctx);
267     if (MO.isJTI() && MAI.hasSetDirective()) {
268       // If .set directive is supported, use it to reduce the number of
269       // relocations the assembler will generate for differences between
270       // local labels. This is only safe when the symbols are in the same
271       // section so we are restricting it to jumptable references.
272       MCSymbol *Label = Ctx.CreateTempSymbol();
273       AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
274       Expr = MCSymbolRefExpr::Create(Label, Ctx);
275     }
276     break;
277   }
278 
279   if (!Expr)
280     Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
281 
282   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
283     Expr = MCBinaryExpr::CreateAdd(Expr,
284                                    MCConstantExpr::Create(MO.getOffset(), Ctx),
285                                    Ctx);
286   return MCOperand::CreateExpr(Expr);
287 }
288 
289 
290 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
291 /// a short fixed-register form.
292 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
293   unsigned ImmOp = Inst.getNumOperands() - 1;
294   assert(Inst.getOperand(0).isReg() &&
295          (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
296          ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
297            Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
298           Inst.getNumOperands() == 2) && "Unexpected instruction!");
299 
300   // Check whether the destination register can be fixed.
301   unsigned Reg = Inst.getOperand(0).getReg();
302   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
303     return;
304 
305   // If so, rewrite the instruction.
306   MCOperand Saved = Inst.getOperand(ImmOp);
307   Inst = MCInst();
308   Inst.setOpcode(Opcode);
309   Inst.addOperand(Saved);
310 }
311 
312 /// \brief If a movsx instruction has a shorter encoding for the used register
313 /// simplify the instruction to use it instead.
314 static void SimplifyMOVSX(MCInst &Inst) {
315   unsigned NewOpcode = 0;
316   unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
317   switch (Inst.getOpcode()) {
318   default:
319     llvm_unreachable("Unexpected instruction!");
320   case X86::MOVSX16rr8:  // movsbw %al, %ax   --> cbtw
321     if (Op0 == X86::AX && Op1 == X86::AL)
322       NewOpcode = X86::CBW;
323     break;
324   case X86::MOVSX32rr16: // movswl %ax, %eax  --> cwtl
325     if (Op0 == X86::EAX && Op1 == X86::AX)
326       NewOpcode = X86::CWDE;
327     break;
328   case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
329     if (Op0 == X86::RAX && Op1 == X86::EAX)
330       NewOpcode = X86::CDQE;
331     break;
332   }
333 
334   if (NewOpcode != 0) {
335     Inst = MCInst();
336     Inst.setOpcode(NewOpcode);
337   }
338 }
339 
340 /// \brief Simplify things like MOV32rm to MOV32o32a.
341 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
342                                   unsigned Opcode) {
343   // Don't make these simplifications in 64-bit mode; other assemblers don't
344   // perform them because they make the code larger.
345   if (Printer.getSubtarget().is64Bit())
346     return;
347 
348   bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
349   unsigned AddrBase = IsStore;
350   unsigned RegOp = IsStore ? 0 : 5;
351   unsigned AddrOp = AddrBase + 3;
352   assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
353          Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
354          Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
355          Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
356          Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
357          (Inst.getOperand(AddrOp).isExpr() ||
358           Inst.getOperand(AddrOp).isImm()) &&
359          "Unexpected instruction!");
360 
361   // Check whether the destination register can be fixed.
362   unsigned Reg = Inst.getOperand(RegOp).getReg();
363   if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
364     return;
365 
366   // Check whether this is an absolute address.
367   // FIXME: We know TLVP symbol refs aren't, but there should be a better way
368   // to do this here.
369   bool Absolute = true;
370   if (Inst.getOperand(AddrOp).isExpr()) {
371     const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
372     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
373       if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
374         Absolute = false;
375   }
376 
377   if (Absolute &&
378       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
379        Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
380        Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
381     return;
382 
383   // If so, rewrite the instruction.
384   MCOperand Saved = Inst.getOperand(AddrOp);
385   MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
386   Inst = MCInst();
387   Inst.setOpcode(Opcode);
388   Inst.addOperand(Saved);
389   Inst.addOperand(Seg);
390 }
391 
392 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
393 {
394 	return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
395 }
396 
397 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
398   OutMI.setOpcode(MI->getOpcode());
399 
400   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
401     const MachineOperand &MO = MI->getOperand(i);
402 
403     MCOperand MCOp;
404     switch (MO.getType()) {
405     default:
406       MI->dump();
407       llvm_unreachable("unknown operand type");
408     case MachineOperand::MO_Register:
409       // Ignore all implicit register operands.
410       if (MO.isImplicit()) continue;
411       MCOp = MCOperand::CreateReg(MO.getReg());
412       break;
413     case MachineOperand::MO_Immediate:
414       MCOp = MCOperand::CreateImm(MO.getImm());
415       break;
416     case MachineOperand::MO_MachineBasicBlock:
417     case MachineOperand::MO_GlobalAddress:
418     case MachineOperand::MO_ExternalSymbol:
419       MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
420       break;
421     case MachineOperand::MO_JumpTableIndex:
422       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
423       break;
424     case MachineOperand::MO_ConstantPoolIndex:
425       MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
426       break;
427     case MachineOperand::MO_BlockAddress:
428       MCOp = LowerSymbolOperand(MO,
429                      AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
430       break;
431     case MachineOperand::MO_RegisterMask:
432       // Ignore call clobbers.
433       continue;
434     }
435 
436     OutMI.addOperand(MCOp);
437   }
438 
439   // Handle a few special cases to eliminate operand modifiers.
440 ReSimplify:
441   switch (OutMI.getOpcode()) {
442   case X86::LEA64_32r:
443   case X86::LEA64r:
444   case X86::LEA16r:
445   case X86::LEA32r:
446     // LEA should have a segment register, but it must be empty.
447     assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
448            "Unexpected # of LEA operands");
449     assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
450            "LEA has segment specified!");
451     break;
452 
453   case X86::MOV32ri64:
454     OutMI.setOpcode(X86::MOV32ri);
455     break;
456 
457   // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
458   // if one of the registers is extended, but other isn't.
459   case X86::VMOVAPDrr:
460   case X86::VMOVAPDYrr:
461   case X86::VMOVAPSrr:
462   case X86::VMOVAPSYrr:
463   case X86::VMOVDQArr:
464   case X86::VMOVDQAYrr:
465   case X86::VMOVDQUrr:
466   case X86::VMOVDQUYrr:
467   case X86::VMOVUPDrr:
468   case X86::VMOVUPDYrr:
469   case X86::VMOVUPSrr:
470   case X86::VMOVUPSYrr: {
471     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
472         X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
473       unsigned NewOpc;
474       switch (OutMI.getOpcode()) {
475       default: llvm_unreachable("Invalid opcode");
476       case X86::VMOVAPDrr:  NewOpc = X86::VMOVAPDrr_REV;  break;
477       case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
478       case X86::VMOVAPSrr:  NewOpc = X86::VMOVAPSrr_REV;  break;
479       case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
480       case X86::VMOVDQArr:  NewOpc = X86::VMOVDQArr_REV;  break;
481       case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
482       case X86::VMOVDQUrr:  NewOpc = X86::VMOVDQUrr_REV;  break;
483       case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
484       case X86::VMOVUPDrr:  NewOpc = X86::VMOVUPDrr_REV;  break;
485       case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
486       case X86::VMOVUPSrr:  NewOpc = X86::VMOVUPSrr_REV;  break;
487       case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
488       }
489       OutMI.setOpcode(NewOpc);
490     }
491     break;
492   }
493   case X86::VMOVSDrr:
494   case X86::VMOVSSrr: {
495     if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
496         X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
497       unsigned NewOpc;
498       switch (OutMI.getOpcode()) {
499       default: llvm_unreachable("Invalid opcode");
500       case X86::VMOVSDrr:   NewOpc = X86::VMOVSDrr_REV;   break;
501       case X86::VMOVSSrr:   NewOpc = X86::VMOVSSrr_REV;   break;
502       }
503       OutMI.setOpcode(NewOpc);
504     }
505     break;
506   }
507 
508   // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
509   // inputs modeled as normal uses instead of implicit uses.  As such, truncate
510   // off all but the first operand (the callee).  FIXME: Change isel.
511   case X86::TAILJMPr64:
512   case X86::CALL64r:
513   case X86::CALL64pcrel32: {
514     unsigned Opcode = OutMI.getOpcode();
515     MCOperand Saved = OutMI.getOperand(0);
516     OutMI = MCInst();
517     OutMI.setOpcode(Opcode);
518     OutMI.addOperand(Saved);
519     break;
520   }
521 
522   case X86::EH_RETURN:
523   case X86::EH_RETURN64: {
524     OutMI = MCInst();
525     OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
526     break;
527   }
528 
529   // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
530   case X86::TAILJMPr:
531   case X86::TAILJMPd:
532   case X86::TAILJMPd64: {
533     unsigned Opcode;
534     switch (OutMI.getOpcode()) {
535     default: llvm_unreachable("Invalid opcode");
536     case X86::TAILJMPr: Opcode = X86::JMP32r; break;
537     case X86::TAILJMPd:
538     case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
539     }
540 
541     MCOperand Saved = OutMI.getOperand(0);
542     OutMI = MCInst();
543     OutMI.setOpcode(Opcode);
544     OutMI.addOperand(Saved);
545     break;
546   }
547 
548   // These are pseudo-ops for OR to help with the OR->ADD transformation.  We do
549   // this with an ugly goto in case the resultant OR uses EAX and needs the
550   // short form.
551   case X86::ADD16rr_DB:   OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
552   case X86::ADD32rr_DB:   OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
553   case X86::ADD64rr_DB:   OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
554   case X86::ADD16ri_DB:   OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
555   case X86::ADD32ri_DB:   OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
556   case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
557   case X86::ADD16ri8_DB:  OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
558   case X86::ADD32ri8_DB:  OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
559   case X86::ADD64ri8_DB:  OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
560 
561   // The assembler backend wants to see branches in their small form and relax
562   // them to their large form.  The JIT can only handle the large form because
563   // it does not do relaxation.  For now, translate the large form to the
564   // small one here.
565   case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
566   case X86::JO_4:  OutMI.setOpcode(X86::JO_1); break;
567   case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
568   case X86::JB_4:  OutMI.setOpcode(X86::JB_1); break;
569   case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
570   case X86::JE_4:  OutMI.setOpcode(X86::JE_1); break;
571   case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
572   case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
573   case X86::JA_4:  OutMI.setOpcode(X86::JA_1); break;
574   case X86::JS_4:  OutMI.setOpcode(X86::JS_1); break;
575   case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
576   case X86::JP_4:  OutMI.setOpcode(X86::JP_1); break;
577   case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
578   case X86::JL_4:  OutMI.setOpcode(X86::JL_1); break;
579   case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
580   case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
581   case X86::JG_4:  OutMI.setOpcode(X86::JG_1); break;
582 
583   // Atomic load and store require a separate pseudo-inst because Acquire
584   // implies mayStore and Release implies mayLoad; fix these to regular MOV
585   // instructions here
586   case X86::ACQUIRE_MOV8rm:  OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
587   case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
588   case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
589   case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
590   case X86::RELEASE_MOV8mr:  OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
591   case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
592   case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
593   case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
594 
595   // We don't currently select the correct instruction form for instructions
596   // which have a short %eax, etc. form. Handle this by custom lowering, for
597   // now.
598   //
599   // Note, we are currently not handling the following instructions:
600   // MOV64ao8, MOV64o8a
601   // XCHG16ar, XCHG32ar, XCHG64ar
602   case X86::MOV8mr_NOREX:
603   case X86::MOV8mr:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
604   case X86::MOV8rm_NOREX:
605   case X86::MOV8rm:     SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
606   case X86::MOV16mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
607   case X86::MOV16rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
608   case X86::MOV32mr:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
609   case X86::MOV32rm:    SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
610 
611   case X86::ADC8ri:     SimplifyShortImmForm(OutMI, X86::ADC8i8);    break;
612   case X86::ADC16ri:    SimplifyShortImmForm(OutMI, X86::ADC16i16);  break;
613   case X86::ADC32ri:    SimplifyShortImmForm(OutMI, X86::ADC32i32);  break;
614   case X86::ADC64ri32:  SimplifyShortImmForm(OutMI, X86::ADC64i32);  break;
615   case X86::ADD8ri:     SimplifyShortImmForm(OutMI, X86::ADD8i8);    break;
616   case X86::ADD16ri:    SimplifyShortImmForm(OutMI, X86::ADD16i16);  break;
617   case X86::ADD32ri:    SimplifyShortImmForm(OutMI, X86::ADD32i32);  break;
618   case X86::ADD64ri32:  SimplifyShortImmForm(OutMI, X86::ADD64i32);  break;
619   case X86::AND8ri:     SimplifyShortImmForm(OutMI, X86::AND8i8);    break;
620   case X86::AND16ri:    SimplifyShortImmForm(OutMI, X86::AND16i16);  break;
621   case X86::AND32ri:    SimplifyShortImmForm(OutMI, X86::AND32i32);  break;
622   case X86::AND64ri32:  SimplifyShortImmForm(OutMI, X86::AND64i32);  break;
623   case X86::CMP8ri:     SimplifyShortImmForm(OutMI, X86::CMP8i8);    break;
624   case X86::CMP16ri:    SimplifyShortImmForm(OutMI, X86::CMP16i16);  break;
625   case X86::CMP32ri:    SimplifyShortImmForm(OutMI, X86::CMP32i32);  break;
626   case X86::CMP64ri32:  SimplifyShortImmForm(OutMI, X86::CMP64i32);  break;
627   case X86::OR8ri:      SimplifyShortImmForm(OutMI, X86::OR8i8);     break;
628   case X86::OR16ri:     SimplifyShortImmForm(OutMI, X86::OR16i16);   break;
629   case X86::OR32ri:     SimplifyShortImmForm(OutMI, X86::OR32i32);   break;
630   case X86::OR64ri32:   SimplifyShortImmForm(OutMI, X86::OR64i32);   break;
631   case X86::SBB8ri:     SimplifyShortImmForm(OutMI, X86::SBB8i8);    break;
632   case X86::SBB16ri:    SimplifyShortImmForm(OutMI, X86::SBB16i16);  break;
633   case X86::SBB32ri:    SimplifyShortImmForm(OutMI, X86::SBB32i32);  break;
634   case X86::SBB64ri32:  SimplifyShortImmForm(OutMI, X86::SBB64i32);  break;
635   case X86::SUB8ri:     SimplifyShortImmForm(OutMI, X86::SUB8i8);    break;
636   case X86::SUB16ri:    SimplifyShortImmForm(OutMI, X86::SUB16i16);  break;
637   case X86::SUB32ri:    SimplifyShortImmForm(OutMI, X86::SUB32i32);  break;
638   case X86::SUB64ri32:  SimplifyShortImmForm(OutMI, X86::SUB64i32);  break;
639   case X86::TEST8ri:    SimplifyShortImmForm(OutMI, X86::TEST8i8);   break;
640   case X86::TEST16ri:   SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
641   case X86::TEST32ri:   SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
642   case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
643   case X86::XOR8ri:     SimplifyShortImmForm(OutMI, X86::XOR8i8);    break;
644   case X86::XOR16ri:    SimplifyShortImmForm(OutMI, X86::XOR16i16);  break;
645   case X86::XOR32ri:    SimplifyShortImmForm(OutMI, X86::XOR32i32);  break;
646   case X86::XOR64ri32:  SimplifyShortImmForm(OutMI, X86::XOR64i32);  break;
647 
648   // Try to shrink some forms of movsx.
649   case X86::MOVSX16rr8:
650   case X86::MOVSX32rr16:
651   case X86::MOVSX64rr32:
652     SimplifyMOVSX(OutMI);
653     break;
654   }
655 }
656 
657 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
658                                  const MachineInstr &MI) {
659 
660   bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
661                   MI.getOpcode() == X86::TLS_base_addr64;
662 
663   bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
664 
665   MCContext &context = OutStreamer.getContext();
666 
667   if (needsPadding)
668     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
669 
670   MCSymbolRefExpr::VariantKind SRVK;
671   switch (MI.getOpcode()) {
672     case X86::TLS_addr32:
673     case X86::TLS_addr64:
674       SRVK = MCSymbolRefExpr::VK_TLSGD;
675       break;
676     case X86::TLS_base_addr32:
677       SRVK = MCSymbolRefExpr::VK_TLSLDM;
678       break;
679     case X86::TLS_base_addr64:
680       SRVK = MCSymbolRefExpr::VK_TLSLD;
681       break;
682     default:
683       llvm_unreachable("unexpected opcode");
684   }
685 
686   MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
687   const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
688 
689   MCInst LEA;
690   if (is64Bits) {
691     LEA.setOpcode(X86::LEA64r);
692     LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
693     LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
694     LEA.addOperand(MCOperand::CreateImm(1));        // scale
695     LEA.addOperand(MCOperand::CreateReg(0));        // index
696     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
697     LEA.addOperand(MCOperand::CreateReg(0));        // seg
698   } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
699     LEA.setOpcode(X86::LEA32r);
700     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
701     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
702     LEA.addOperand(MCOperand::CreateImm(1));        // scale
703     LEA.addOperand(MCOperand::CreateReg(0));        // index
704     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
705     LEA.addOperand(MCOperand::CreateReg(0));        // seg
706   } else {
707     LEA.setOpcode(X86::LEA32r);
708     LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
709     LEA.addOperand(MCOperand::CreateReg(0));        // base
710     LEA.addOperand(MCOperand::CreateImm(1));        // scale
711     LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
712     LEA.addOperand(MCOperand::CreateExpr(symRef));  // disp
713     LEA.addOperand(MCOperand::CreateReg(0));        // seg
714   }
715   EmitAndCountInstruction(LEA);
716 
717   if (needsPadding) {
718     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
719     EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
720     EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
721   }
722 
723   StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
724   MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
725   const MCSymbolRefExpr *tlsRef =
726     MCSymbolRefExpr::Create(tlsGetAddr,
727                             MCSymbolRefExpr::VK_PLT,
728                             context);
729 
730   EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
731                                                  : X86::CALLpcrel32)
732                             .addExpr(tlsRef));
733 }
734 
735 /// \brief Emit the optimal amount of multi-byte nops on X86.
736 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
737   // This works only for 64bit. For 32bit we have to do additional checking if
738   // the CPU supports multi-byte nops.
739   assert(Is64Bit && "EmitNops only supports X86-64");
740   while (NumBytes) {
741     unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
742     Opc = IndexReg = Displacement = SegmentReg = 0;
743     BaseReg = X86::RAX; ScaleVal = 1;
744     switch (NumBytes) {
745     case  0: llvm_unreachable("Zero nops?"); break;
746     case  1: NumBytes -=  1; Opc = X86::NOOP; break;
747     case  2: NumBytes -=  2; Opc = X86::XCHG16ar; break;
748     case  3: NumBytes -=  3; Opc = X86::NOOPL; break;
749     case  4: NumBytes -=  4; Opc = X86::NOOPL; Displacement = 8; break;
750     case  5: NumBytes -=  5; Opc = X86::NOOPL; Displacement = 8;
751              IndexReg = X86::RAX; break;
752     case  6: NumBytes -=  6; Opc = X86::NOOPW; Displacement = 8;
753              IndexReg = X86::RAX; break;
754     case  7: NumBytes -=  7; Opc = X86::NOOPL; Displacement = 512; break;
755     case  8: NumBytes -=  8; Opc = X86::NOOPL; Displacement = 512;
756              IndexReg = X86::RAX; break;
757     case  9: NumBytes -=  9; Opc = X86::NOOPW; Displacement = 512;
758              IndexReg = X86::RAX; break;
759     default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
760              IndexReg = X86::RAX; SegmentReg = X86::CS; break;
761     }
762 
763     unsigned NumPrefixes = std::min(NumBytes, 5U);
764     NumBytes -= NumPrefixes;
765     for (unsigned i = 0; i != NumPrefixes; ++i)
766       OS.EmitBytes("\x66");
767 
768     switch (Opc) {
769     default: llvm_unreachable("Unexpected opcode"); break;
770     case X86::NOOP:
771       OS.EmitInstruction(MCInstBuilder(Opc), STI);
772       break;
773     case X86::XCHG16ar:
774       OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
775       break;
776     case X86::NOOPL:
777     case X86::NOOPW:
778       OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
779                          .addImm(ScaleVal).addReg(IndexReg)
780                          .addImm(Displacement).addReg(SegmentReg), STI);
781       break;
782     }
783   } // while (NumBytes)
784 }
785 
786 // Lower a stackmap of the form:
787 // <id>, <shadowBytes>, ...
788 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
789   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
790   SM.recordStackMap(MI);
791   unsigned NumShadowBytes = MI.getOperand(1).getImm();
792   SMShadowTracker.reset(NumShadowBytes);
793 }
794 
795 // Lower a patchpoint of the form:
796 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
797 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
798   assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
799 
800   SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
801 
802   SM.recordPatchPoint(MI);
803 
804   PatchPointOpers opers(&MI);
805   unsigned ScratchIdx = opers.getNextScratchIdx();
806   unsigned EncodedBytes = 0;
807   int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
808   if (CallTarget) {
809     // Emit MOV to materialize the target address and the CALL to target.
810     // This is encoded with 12-13 bytes, depending on which register is used.
811     unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
812     if (X86II::isX86_64ExtendedReg(ScratchReg))
813       EncodedBytes = 13;
814     else
815       EncodedBytes = 12;
816     EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
817                                                        .addImm(CallTarget));
818     EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
819   }
820   // Emit padding.
821   unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
822   assert(NumBytes >= EncodedBytes &&
823          "Patchpoint can't request size less than the length of a call.");
824 
825   EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
826            getSubtargetInfo());
827 }
828 
829 // Returns instruction preceding MBBI in MachineFunction.
830 // If MBBI is the first instruction of the first basic block, returns null.
831 static MachineBasicBlock::const_iterator
832 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
833   const MachineBasicBlock *MBB = MBBI->getParent();
834   while (MBBI == MBB->begin()) {
835     if (MBB == MBB->getParent()->begin())
836       return nullptr;
837     MBB = MBB->getPrevNode();
838     MBBI = MBB->end();
839   }
840   return --MBBI;
841 }
842 
843 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
844   X86MCInstLower MCInstLowering(*MF, *this);
845   const X86RegisterInfo *RI = static_cast<const X86RegisterInfo *>(
846       TM.getSubtargetImpl()->getRegisterInfo());
847 
848   switch (MI->getOpcode()) {
849   case TargetOpcode::DBG_VALUE:
850     llvm_unreachable("Should be handled target independently");
851 
852   // Emit nothing here but a comment if we can.
853   case X86::Int_MemBarrier:
854     OutStreamer.emitRawComment("MEMBARRIER");
855     return;
856 
857 
858   case X86::EH_RETURN:
859   case X86::EH_RETURN64: {
860     // Lower these as normal, but add some comments.
861     unsigned Reg = MI->getOperand(0).getReg();
862     OutStreamer.AddComment(StringRef("eh_return, addr: %") +
863                            X86ATTInstPrinter::getRegisterName(Reg));
864     break;
865   }
866   case X86::TAILJMPr:
867   case X86::TAILJMPd:
868   case X86::TAILJMPd64:
869     // Lower these as normal, but add some comments.
870     OutStreamer.AddComment("TAILCALL");
871     break;
872 
873   case X86::TLS_addr32:
874   case X86::TLS_addr64:
875   case X86::TLS_base_addr32:
876   case X86::TLS_base_addr64:
877     return LowerTlsAddr(MCInstLowering, *MI);
878 
879   case X86::MOVPC32r: {
880     // This is a pseudo op for a two instruction sequence with a label, which
881     // looks like:
882     //     call "L1$pb"
883     // "L1$pb":
884     //     popl %esi
885 
886     // Emit the call.
887     MCSymbol *PICBase = MF->getPICBaseSymbol();
888     // FIXME: We would like an efficient form for this, so we don't have to do a
889     // lot of extra uniquing.
890     EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
891       .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
892 
893     // Emit the label.
894     OutStreamer.EmitLabel(PICBase);
895 
896     // popl $reg
897     EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
898                             .addReg(MI->getOperand(0).getReg()));
899     return;
900   }
901 
902   case X86::ADD32ri: {
903     // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
904     if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
905       break;
906 
907     // Okay, we have something like:
908     //  EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
909 
910     // For this, we want to print something like:
911     //   MYGLOBAL + (. - PICBASE)
912     // However, we can't generate a ".", so just emit a new label here and refer
913     // to it.
914     MCSymbol *DotSym = OutContext.CreateTempSymbol();
915     OutStreamer.EmitLabel(DotSym);
916 
917     // Now that we have emitted the label, lower the complex operand expression.
918     MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
919 
920     const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
921     const MCExpr *PICBase =
922       MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
923     DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
924 
925     DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
926                                       DotExpr, OutContext);
927 
928     EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
929       .addReg(MI->getOperand(0).getReg())
930       .addReg(MI->getOperand(1).getReg())
931       .addExpr(DotExpr));
932     return;
933   }
934 
935   case TargetOpcode::STACKMAP:
936     return LowerSTACKMAP(*MI);
937 
938   case TargetOpcode::PATCHPOINT:
939     return LowerPATCHPOINT(*MI);
940 
941   case X86::MORESTACK_RET:
942     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
943     return;
944 
945   case X86::MORESTACK_RET_RESTORE_R10:
946     // Return, then restore R10.
947     EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
948     EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
949                             .addReg(X86::R10)
950                             .addReg(X86::RAX));
951     return;
952 
953   case X86::SEH_PushReg:
954     OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
955     return;
956 
957   case X86::SEH_SaveReg:
958     OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
959                                   MI->getOperand(1).getImm());
960     return;
961 
962   case X86::SEH_SaveXMM:
963     OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
964                                   MI->getOperand(1).getImm());
965     return;
966 
967   case X86::SEH_StackAlloc:
968     OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
969     return;
970 
971   case X86::SEH_SetFrame:
972     OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
973                                    MI->getOperand(1).getImm());
974     return;
975 
976   case X86::SEH_PushFrame:
977     OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
978     return;
979 
980   case X86::SEH_EndPrologue:
981     OutStreamer.EmitWinCFIEndProlog();
982     return;
983 
984   case X86::SEH_Epilogue: {
985     MachineBasicBlock::const_iterator MBBI(MI);
986     // Check if preceded by a call and emit nop if so.
987     for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
988       // Conservatively assume that pseudo instructions don't emit code and keep
989       // looking for a call. We may emit an unnecessary nop in some cases.
990       if (!MBBI->isPseudo()) {
991         if (MBBI->isCall())
992           EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
993         break;
994       }
995     }
996     return;
997   }
998 
999   case X86::PSHUFBrm:
1000   case X86::VPSHUFBrm:
1001     // Lower PSHUFB normally but add a comment if we can find a constant
1002     // shuffle mask. We won't be able to do this at the MC layer because the
1003     // mask isn't an immediate.
1004     std::string Comment;
1005     raw_string_ostream CS(Comment);
1006     SmallVector<int, 16> Mask;
1007 
1008     assert(MI->getNumOperands() >= 6 &&
1009            "Wrong number of operands for PSHUFBrm or VPSHUFBrm");
1010     const MachineOperand &DstOp = MI->getOperand(0);
1011     const MachineOperand &SrcOp = MI->getOperand(1);
1012     const MachineOperand &MaskOp = MI->getOperand(5);
1013 
1014     // Compute the name for a register. This is really goofy because we have
1015     // multiple instruction printers that could (in theory) use different
1016     // names. Fortunately most people use the ATT style (outside of Windows)
1017     // and they actually agree on register naming here. Ultimately, this is
1018     // a comment, and so its OK if it isn't perfect.
1019     auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1020       return X86ATTInstPrinter::getRegisterName(RegNum);
1021     };
1022 
1023     StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1024     StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
1025     CS << DstName << " = ";
1026 
1027     if (MaskOp.isCPI()) {
1028       ArrayRef<MachineConstantPoolEntry> Constants =
1029           MI->getParent()->getParent()->getConstantPool()->getConstants();
1030       const MachineConstantPoolEntry &MaskConstantEntry =
1031           Constants[MaskOp.getIndex()];
1032       Type *MaskTy = MaskConstantEntry.getType();
1033       (void)MaskTy;
1034       if (!MaskConstantEntry.isMachineConstantPoolEntry())
1035         if (auto *C = dyn_cast<ConstantDataSequential>(
1036                 MaskConstantEntry.Val.ConstVal)) {
1037           assert(MaskTy == C->getType() &&
1038                  "Expected a constant of the same type!");
1039 
1040           DecodePSHUFBMask(C, Mask);
1041           assert(Mask.size() == MaskTy->getVectorNumElements() &&
1042                  "Shuffle mask has a different size than its type!");
1043         }
1044     }
1045 
1046     if (!Mask.empty()) {
1047       bool NeedComma = false;
1048       bool InSrc = false;
1049       for (int M : Mask) {
1050         // Wrap up any prior entry...
1051         if (M == SM_SentinelZero && InSrc) {
1052           InSrc = false;
1053           CS << "]";
1054         }
1055         if (NeedComma)
1056           CS << ",";
1057         else
1058           NeedComma = true;
1059 
1060         // Print this shuffle...
1061         if (M == SM_SentinelZero) {
1062           CS << "zero";
1063         } else {
1064           if (!InSrc) {
1065             InSrc = true;
1066             CS << SrcName << "[";
1067           }
1068           CS << M;
1069         }
1070       }
1071       if (InSrc)
1072         CS << "]";
1073 
1074       OutStreamer.AddComment(CS.str());
1075     }
1076     break;
1077   }
1078 
1079   MCInst TmpInst;
1080   MCInstLowering.Lower(MI, TmpInst);
1081   EmitAndCountInstruction(TmpInst);
1082 }
1083